JPS6337414B2 - - Google Patents

Description

[Detailed Description of the Invention] According to the present invention, an external data memory (hereinafter referred to as RAM) that can be read and written to
can be easily expanded and this RAM can be used as program memory (conventionally, this is stored in read-only memory (hereinafter referred to as ROM)), making it easy to debug programs or expand the work area. can be done. Also, this
If RAM is non-volatile memory, it can also be used as a file.

Therefore, in addition to making it easier to debug programs, it can also be used as a control computer for communication control, printing printer control, etc., which requires a large work area, which was previously difficult to apply, or for processing a large number of files. It can now be used for automatic meter reading devices that require

The microcomputer to which the present invention is applied is a so-called single-chip microcomputer (hereinafter referred to as SCM), which strictly separates program memory and data memory (also referred to as work area). Lighting is disabled. However, although the data memory can be read and written, it cannot be fetched as a program memory.

The following two points can be cited as problems with the above-mentioned SCM.

First point: External data memory can be expanded in units of 256 bytes, but in order to distinguish between the first 256 bytes and the second, third, ... 256 bytes, it is necessary to read the memory. Alternatively, it is necessary to output the number to the I/O port to designate the number before executing the write, and to cancel this designation after the read or write is completed.

The I/O port connects directly to each controlled object, through which the central processing
Information is transmitted between the unit (hereinafter referred to as CPU) and the controlled object. Therefore, as the number of objects to be controlled increases, there is an upper limit to the number of I/O ports, which is generally about 64.

Therefore, in the conventional method, when an external data memory is added, the upper limit value of the number of controlled objects decreases.

Second point: As mentioned in the prior art section, SCM
External data memory and program memory are strictly separated, so even if you were aware of the shortcomings mentioned in the first point and added more RAM, there was no way to use it as program memory.

In fact, when developing a program for the SCM,
Normally, a program is created on a trial basis, and then it is run and then modified several times to complete the process. Therefore, in the past, it was necessary to repeatedly modify the ROM in which the program was stored. This has the disadvantage that it requires a considerable amount of time and man-hours, reducing the efficiency of program development.

The present invention has been made in view of the above-mentioned drawbacks, and its purpose is to prevent the number of control objects that can be connected from decreasing even if external data memory (RAM) is added, and to increase the capacity of the RAM. To provide a program development device which allows programs to be stored and executed in a computer and which is highly efficient in debugging programs.

In order to achieve the above object, the present invention is characterized by defining a write sequence for an external data memory, writing or modifying a program in this memory by treating it as data, and then treating the memory as a program memory. , the program written there can be executed.

As can be easily inferred from the above, this device considers the RAM to be a data memory during the write sequence, so it is impossible to execute a program on the RAM during this period. However, since most processing programs do not rewrite their own programs during program execution, this is not a big problem.

An embodiment of the present invention shown in the drawings will be described below. FIG. 1 shows the basic configuration of a program development apparatus according to the present invention and a connection diagram when this is applied to a debugging target. In this figure, 1 is the main controller, 2 is the program development device, 3 is the CPU, and 4 is the main controller.
is the ROM, and 5 is the area where the contents of ROM4 are transferred.
RAM, 6 is the circuit section that creates the write sequence, 7
is an address latch. The program to be debugged by this is stored in ROM4, and this is
After moving it to RAM5, run this program and debug it.

The method of writing to the RAM 5 will be explained in detail later, but here it is assumed that this method has already been established, and first a specific method of transferring the program to the RAM 5 and executing it will be described.

As shown in FIG. 2, there are several switch groups 8, 9, 11, 12,
13 and 14, and a means for reading these setting contents, and the programs shown in the flowcharts of FIGS. 3 and 4 may be stored in the ROM 5. 15 is an input/output port (hereinafter referred to as an I/O port). The actual operating procedure is divided into five steps as follows.

First step: After turning on the test switch 14, the general reset switch (hereinafter abbreviated as GRS switch) 13 is pressed to start the MPL support program shown in the flowchart of FIG. However, the RAM start switch 12 is in a cut-off state.

Second step: With the support of the MPL support program, the write destination address and the data to be written are set in the address switch 8 and data switch 9, respectively, and then the write switch 11 is pressed. repeat this
In the relay area on RAM5,
Write a jump command at the beginning of the program to be moved.

3rd stage: When the RAM start switch 12 is turned on, control moves to the beginning of the program to be moved, and therefore the program on ROM4
Moved to RAM5.

4th stage: If there are any corrections found in the previous debugging, turn on the RAM start switch 12.
shut off, press GRS switch 13,
Under the auspices of the MPL Support Program, RAM5
Modify the above program.

Fifth stage: After replacing the jump destination in the second stage with the start address of the program to be debugged, the RAM start switch 12
The program to be debugged will be executed.

Next, an example of a write sequencer is shown in FIGS. 5 and 6. In this example, the CPU 3 is an 8035 type manufactured by Intel Corporation. Figure 5 is the circuit diagram, Figure 6a is the flowchart of the writing program, Figure 6b is the writing program displayed as a mnemonic, and Figure 7 is the writing program.
The figure is a time chart. In this example, the start signal of the write sequence is generated by issuing a read command to the external data memory using a tamper, but this is done in consideration of not reducing the number of usable I/O ports. Furthermore, the write sequence ends when the write command is executed.

After writing is completed, that is, when the sequence flag 16 is reset, the only access signal to the RAM 5 is the signal PSEN, as shown in FIG. Since this signal PSEN is output when an instruction is fetched, it can be seen that the program on the RAM 5 can be executed. On the other hand, when the sequence flag is set, this signal is not output, making it impossible to execute instructions on the RAM. For this reason, it is desirable to issue a write command as soon as possible when issuing a write sequence start signal to shorten the period of the write sequence. The program shown in FIG. 6 shortens this period to the minimum, and it has been made into a subroutine, so if you want to write to the RAM 5, you can call this subroutine.

As is clear from the above description, according to the present invention, the number of usable I/O ports does not decrease, and
It was possible to add external data memory (RAM) and provided a means for executing programs written on this RAM. By using the means obtained in the present invention, it is possible to modify the program on the RAM during program development, so the efficiency of program development is extremely high and great effects can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a basic configuration diagram of a program development device showing an embodiment of the present invention, and Fig. 2 shows a basic configuration diagram of a program development device showing an embodiment of the present invention.
A connection diagram showing an example of transferring to RAM and executing it.
3 and 4 are flowcharts showing an example of a program stored in the ROM, FIG. 5 is a connection diagram of the program development device showing the write sequencer in detail, and FIG. 6a is a flowchart showing a write program. FIG. 6b is a mnemonic representation of the flowchart shown in FIG. 6a, and FIG. 7 is a time chart of the write operation. 1; Main control device, 2; Program development device,
3; CPU, 4; ROM, 5; RAM, 6; Write sequencer, 7; Address latch, 8; Address switch, 9; Data switch, 10; Read switch, 11; Write switch, 12; Start switch, 13; GRS Switch, 14; Test switch, 15; I/O switch, 16; Sequence flag.

Claims (1)

[Claims] 1. In a program development device that connects an external memory to a single-chip microcomputer where the program memory and data memory are separated and cannot write to the program memory, and debugs the program by fetching instructions from this memory, means for storing a start signal of a write sequence; a gate circuit for supplying a dummy read command as a start signal from the start signal storage means to the external data memory; and an address signal when accessing the memory by the read command signal. The start signal storage means includes a sequence flag that is set by a read signal from the microcomputer and reset by a write signal, and the start signal storage means is configured to include a sequence flag that is set by a read signal from the microcomputer and reset by a write signal. The gate circuit is configured to reset the memory at the same time, and the gate circuit is controlled by the set state signal of the sequence flag to send the write signal to the R/W terminal of the external data memory and the CE.
terminal and transmits the read signal to the address latch, and is controlled by the reset state signal of the sequence flag to transmit the ALE signal to the address latch and the instruction fetch (PSEN) signal to the CE terminal of the external data memory. A program development apparatus characterized in that the external data memory can be used as a program memory during a period other than during a write sequence.