JPS63307797A - Multilayer interconnection substrate and manufacture thereof - Google Patents
Multilayer interconnection substrate and manufacture thereofInfo
- Publication number
- JPS63307797A JPS63307797A JP14307587A JP14307587A JPS63307797A JP S63307797 A JPS63307797 A JP S63307797A JP 14307587 A JP14307587 A JP 14307587A JP 14307587 A JP14307587 A JP 14307587A JP S63307797 A JPS63307797 A JP S63307797A
- Authority
- JP
- Japan
- Prior art keywords
- glass
- polyimide resin
- wiring
- multilayer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 title abstract description 11
- 239000010408 film Substances 0.000 claims abstract description 107
- 239000011521 glass Substances 0.000 claims abstract description 67
- 229920001721 polyimide Polymers 0.000 claims abstract description 60
- 239000009719 polyimide resin Substances 0.000 claims abstract description 53
- 239000010409 thin film Substances 0.000 claims abstract description 36
- 238000010030 laminating Methods 0.000 claims abstract description 11
- 239000011347 resin Substances 0.000 claims abstract description 11
- 229920005989 resin Polymers 0.000 claims abstract description 11
- 238000007747 plating Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 89
- 239000004020 conductor Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 12
- 239000004642 Polyimide Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 5
- 229920003217 poly(methylsilsesquioxane) Polymers 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 3
- 238000007493 shaping process Methods 0.000 abstract 2
- 239000010432 diamond Substances 0.000 description 12
- 238000010438 heat treatment Methods 0.000 description 11
- 239000000919 ceramic Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 229910003460 diamond Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000011049 filling Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000006089 photosensitive glass Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- 101100410786 Arabidopsis thaliana PXG5 gene Proteins 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000005553 drilling Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 101100410785 Arabidopsis thaliana PXG4 gene Proteins 0.000 description 1
- 206010011732 Cyst Diseases 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- FXHOOIRPVKKKFG-UHFFFAOYSA-N N,N-Dimethylacetamide Chemical compound CN(C)C(C)=O FXHOOIRPVKKKFG-UHFFFAOYSA-N 0.000 description 1
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical compound CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- GTDPSWPPOUPBNX-UHFFFAOYSA-N ac1mqpva Chemical compound CC12C(=O)OC(=O)C1(C)C1(C)C2(C)C(=O)OC1=O GTDPSWPPOUPBNX-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 239000013040 bath agent Substances 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000006482 condensation reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 208000031513 cyst Diseases 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 150000004985 diamines Chemical class 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000007496 glass forming Methods 0.000 description 1
- 235000003642 hunger Nutrition 0.000 description 1
- 229960002050 hydrofluoric acid Drugs 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 239000012046 mixed solvent Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 229920001558 organosilicon polymer Polymers 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 235000021395 porridge Nutrition 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000007665 sagging Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 125000006158 tetracarboxylic acid group Chemical group 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 239000005322 wire mesh glass Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、多層配線基板およびその製造方法に係シ、特
に位置精度が高い塔数の微細な層間配線を有する高集積
、大面積の高速信号伝搬処理用配線基板およびその製造
方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a multilayer wiring board and a method for manufacturing the same, particularly a highly integrated, large-area, high-speed board having a large number of fine interlayer wirings with high positional accuracy. The present invention relates to a wiring board for signal propagation processing and a manufacturing method thereof.
〔従来の技術〕
複数個の高集積LSI等が搭載される多層配線基板では
層間配線(以下ダイアと称する。)の数が極めて多く、
電子計算機の中央論理演算ユニットに使用される基板で
はLSI素子は数十個にのぼり、ダイアの数は数万個に
達する。[Prior Art] A multilayer wiring board on which multiple highly integrated LSIs and the like are mounted has an extremely large number of interlayer wirings (hereinafter referred to as dia).
The number of LSI elements on a board used in the central logical operation unit of an electronic computer reaches several tens, and the number of diamonds reaches tens of thousands.
また、上記多層基板では、搭載される各素子への電源供
給のための大容量配線の形成、素子間の高速信号処理の
ための低誘電率絶縁材料による低抵抗配線の多層化、お
よび基板と素子との接続のために基板表面に位置精度の
高い微細な接続端子の形成が必要とされる。In addition, in the multilayer board mentioned above, the formation of large-capacity wiring to supply power to each mounted element, multilayering of low-resistance wiring using a low dielectric constant insulating material for high-speed signal processing between elements, and For connection with elements, it is necessary to form fine connection terminals with high positional accuracy on the substrate surface.
従来、この種の多層配線基板はグリーンシート厚膜法と
呼ばれる焼結セラミックス厚膜回路基板製造技術による
大容量配線の形成と、低誘電率有機ポリマー全層間絶縁
膜として用いる薄膜回路基板i造技術による位置精度の
高いパターン形成によって製造されている。Conventionally, this type of multilayer wiring board has been produced by forming large-capacity wiring using a sintered ceramic thick film circuit board manufacturing technology called the green sheet thick film method, and by using a thin film circuit board manufacturing technology that uses a low dielectric constant organic polymer as an insulating film between all layers. Manufactured by pattern formation with high positional accuracy.
たとえば大容量配線を形成するグリーンシート厚膜法と
は次のようなものである。アルミナを主成分とする粉末
と有機バインダおよび有機浴剤とを混合し、ドクタブレ
ード法により、グリーン(生)シートが作製される。こ
のグリーンシートを必要な大きさに切断し、ダイアのた
めのスルーホールがパンチングあるいはドリリング等の
機械加工によってシートに形成され、次いで各回路パタ
ーンに従い厚膜スクリーン印刷法によ5wあるいはMo
の導電ペーストを上記スルーホールへ充填するとともに
シート上に配線膜が形成される。その後、配MA済みの
所定枚数のシートを圧着積層して1600℃のH,−N
、 −)1.(Jなどの非酸化性雰囲気中で熱処理を行
ない、グリーンシート積層体上焼結してセラミック厚膜
多層配線基板が作製される。For example, the green sheet thick film method for forming large capacity wiring is as follows. A green (green) sheet is produced by mixing powder mainly composed of alumina, an organic binder and an organic bath agent, and using a doctor blade method. This green sheet is cut to the required size, through holes for diamonds are formed in the sheet by mechanical processing such as punching or drilling, and then 5W or Mo is formed by thick film screen printing according to each circuit pattern.
A conductive paste is filled into the through holes, and a wiring film is formed on the sheet. After that, a predetermined number of sheets that have been distributed by MA are laminated under pressure and heated to 1600°C by H, -N.
, -)1. (Heat treatment is performed in a non-oxidizing atmosphere such as J and sintered on the green sheet laminate to produce a ceramic thick film multilayer wiring board.
そしてセラミック基板上のポリイミド樹脂を絶縁層とす
る薄膜多層配線回路はたとえば次のようにして作製され
る。まずセラミック多層配線基板上にポリイミド樹脂を
スピンナ塗布し加熱硬化後、この上にフォトレジストl
1ie加熱硬化して形成する。更にレジスト膜上に厚膜
多層配線回路と薄膜多層配線回路との接続のためのダイ
ア用スルーホールがマスク露光、現像およびプラズマエ
ツチング等により形成され、無電解めっきにより当該ス
ルーホールにCu導体が充填される。続いて、スバッタ
デボジシ曹ンによって基板全面にCr膜とCu膜が形成
され、Cu膜上に感光性レジスト膜を配線導体となる個
所を除いて形成し、配線導体となる部分KCuめりき換
が形成される。次いで前記感光性レジスト膜が除去され
、このレジスト膜の下にあったCu膜、Cr膜がエツチ
ング除去され、ポリイミド樹脂膜上に配線が形成される
。そして再びポリイミド樹脂膜形成、)tトレジスト膜
形成、フォトレジスト膜へのスルーホールパターン形成
、プラズマエツチングによるポリイミド樹脂膜のスルー
ホール形成、スルーホール内部への無電解Cuめっきに
よる導体充填、スパッタテポジションによるCr膜、C
u膜の形成、感光性レジスト膜が配置184体となる個
所を除いて形成され、無電解・めっき、感光性レジスト
膜の除去、感光性レジスト膜下にあったCu膜とCr膜
の除去等の工程全所定回数繰返して薄膜多層回路が形成
されている。A thin film multilayer wiring circuit using polyimide resin as an insulating layer on a ceramic substrate is manufactured, for example, in the following manner. First, polyimide resin is coated on a ceramic multilayer wiring board using a spinner, and after hardening by heating, a photoresist l is applied on top of this.
1ie is formed by heating and curing. Furthermore, a through hole for a diamond for connecting the thick film multilayer wiring circuit and the thin film multilayer wiring circuit is formed on the resist film by mask exposure, development, plasma etching, etc., and the through hole is filled with a Cu conductor by electroless plating. be done. Subsequently, a Cr film and a Cu film are formed on the entire surface of the substrate by spatter deposition, and a photosensitive resist film is formed on the Cu film except for the areas that will become wiring conductors, and KCu metallization is formed on the parts that will become wiring conductors. be done. Next, the photosensitive resist film is removed, and the Cu film and Cr film below this resist film are etched away, and wiring is formed on the polyimide resin film. Then, form a polyimide resin film again, form a resist film, form a through hole pattern on the photoresist film, form a through hole in the polyimide resin film by plasma etching, fill the inside of the through hole with a conductor by electroless Cu plating, and sputter deposition. Cr film, C
U film formation, photosensitive resist film formed except for the 184 locations, electroless plating, removal of the photosensitive resist film, removal of Cu film and Cr film under the photosensitive resist film, etc. A thin film multilayer circuit is formed by repeating all steps a predetermined number of times.
なお、この釉の多層回路基板に関連するものは、たとえ
ば日経エレクトロニクス 1984年8月27日号、p
pl 45〜159に示されている。For information related to this glazed multilayer circuit board, see Nikkei Electronics August 27, 1984 issue, p.
pl 45-159.
上記従来技術では、次のような問題点や限界があった。 The above conventional technology has the following problems and limitations.
第1に、セラミック厚膜多層配線基板のダイアのための
グリーンシートのスルーホール形成が、パンチングやド
リリング等の機械的加工方法によるために全数同時にで
きない。このためスルーホールの数が50穴/cId以
上に増すと共に、スルーホールの間隔が1W以下に狭ま
るに従って、グリーンシートにたるみや歪みが生じ位置
精度が低下すること、およびこのスルーホール加工に多
大な時間を要することがあった。First, the formation of through-holes in the green sheets for the diamonds of the ceramic thick-film multilayer wiring board cannot be performed simultaneously on all the green sheets because mechanical processing methods such as punching and drilling are used. For this reason, as the number of through holes increases to more than 50 holes/cId and the spacing between the through holes narrows to 1W or less, the green sheet becomes sagging and distorted, resulting in a decrease in positional accuracy. Sometimes it took time.
第2に、グリーンシート積層体は熱処理によって15%
程夏焼結収縮するが、この収縮率の精度は高だか±L1
%が量産的な限界であシ、焼結して作製されるセラミッ
ク多層配線基板では必然的に±0.5%をこえる寸法誤
差を生じ、この寸法誤差はたとえば100箇角の基板に
おいて±500μmとなる。Second, the green sheet laminate is reduced to 15% by heat treatment.
Sintering shrinks during summer, but the accuracy of this shrinkage rate is ±L1.
% is the limit for mass production, and ceramic multilayer wiring boards manufactured by sintering inevitably have a dimensional error exceeding ±0.5%, and this dimensional error is, for example, ±500 μm for a board with 100 corners. becomes.
第6に、セラミック厚膜多層配線基板の寸法誤差吸収の
ために薄膜多層回路では技術的に可能な微細な、高密匿
パターン形成のメリットが低減されることがあった。Sixth, in order to absorb dimensional errors in ceramic thick film multilayer wiring boards, the advantage of technically possible formation of fine, highly dense patterns in thin film multilayer circuits may be reduced.
@4に、セラミックスとして従来多用されているアルミ
ナ基板の熱膨張係数(7X 107/T:)とポリイミ
ド側腹の熱膨張係数(2,0X10’/ ℃)の大きな
麦のために、ポリイミド樹脂膜の塗布面積が広くなシ、
また膜厚が厚くなるに・従ってポリイミド粥脂膜がセラ
ミック基板から剥離しやすく、薄膜多層回路の規模およ
び層数に限界があること、等の問題があった。For @4, we used a polyimide resin film because of the large thermal expansion coefficient of the alumina substrate (7 x 107/T:) and the large thermal expansion coefficient of the polyimide flank (2,0 x 10'/°C), which are conventionally widely used as ceramics. The application area is wide,
Further, as the film thickness increases, the polyimide greasy film tends to peel off from the ceramic substrate, and there are also problems such as there being a limit to the scale and number of layers of a thin film multilayer circuit.
本発明の目的は、上述の問題t−解決し、配線の高集積
化が可能であシ、樹脂膜と基板との剥離を防ぐことがで
きる多層配線基板及びその製造方法を提供することにあ
る。An object of the present invention is to provide a multilayer wiring board and a method for manufacturing the same that can solve the above-mentioned problem, enable high integration of wiring, and prevent peeling between the resin film and the board. .
本発明は、上記問題点を解決するための手段として、
配線層と、上下配線間を電気的に接続するダイアを有す
る絶縁層とを交互に積層して形成する多層配線基板にお
いて、
上下絶縁層として、互いに熱膨張係数の近いガラストホ
リイミド樹脂とを選定して、前者にょシガラス厚膜多層
部を形成し、後者にょ夛ポリイミド樹脂薄膜多層部を形
成すると共に、両者を積層し、
上記ガラス厚膜多層部は、複数枚のガラス絶縁層に厚膜
にて各々対応する層上配線およびダイアを設けて積層す
ることにょシ形成し、
上記ポリイミド樹脂薄膜多層部は、ポリイミド樹脂絶縁
Niを、各層毎に薄膜およびめりきにょシ層上配線およ
びダイアを設けて積層することKよシ形成して構成した
ことを特徴とする。The present invention provides a multilayer wiring board formed by alternately stacking wiring layers and insulating layers having dia for electrically connecting the upper and lower wirings, as a means for solving the above-mentioned problems. As a result, glass tophorimide resins having similar coefficients of thermal expansion are selected, and the former forms a glass thick film multilayer part, and the latter forms a polyimide resin thin film multilayer part, and both are laminated. The film multilayer part is formed by laminating a plurality of glass insulating layers with thick film wiring and diamonds on each layer. It is characterized in that it is constructed by forming a thin film and a wiring layer and a diamond layer on each layer and stacking them.
また、本発明は、上記問題点を解決するための手段とし
て、
配線層と、上下配線間を電気的に接続する配線を有する
絶縁層とを交互に積層して多層配線を行なう多層配線基
板の製造方法において、ポリイミド樹脂と熱膨張係数が
近いガラス絶は層を複数枚揃え、該各ガラス絶R層の各
々設定された位Rに、マスクを介してエツチングするこ
とKよシスルーホールを設けた後、厚膜導体を印刷して
層上配線を設けると共に、スルーホールに厚膜導体を充
填してダイアを設け、
上記各ガラス絶縁層を積層して溶融することにより一体
化してガラス厚膜多層部を形成し、上記ガラス厚膜多層
部上K、ポリイミド樹脂絶縁層を積層し、
該ポリイミド側腹絶縁層は、積層される各樹脂層毎にス
ルーホールを設け、かつ、薄膜およびめっきにより層上
配線を設けると共K、該スルーホールを導通させてダイ
アを形成することを特徴とする。Further, as a means for solving the above problems, the present invention provides a multilayer wiring board in which wiring layers and insulating layers having wiring for electrically connecting upper and lower wirings are laminated alternately to perform multilayer wiring. In the manufacturing method, a plurality of glass layers having a coefficient of thermal expansion similar to that of the polyimide resin are arranged, and through holes are formed at predetermined positions R of each glass layer by etching through a mask. After that, thick film conductors are printed to provide layered wiring, the through holes are filled with thick film conductors to form diamonds, and the above glass insulating layers are laminated and melted to form a single glass thick film. A multilayer part is formed, and a polyimide resin insulating layer is laminated on the top layer of the glass thick film multilayer part, and the polyimide side insulating layer is provided with a through hole for each resin layer to be laminated, and is formed by thin film and plating. When an on-layer wiring is provided, the through hole is made conductive to form a dia.
上記ガラス厚膜多層部を構成するガラス絶縁層としては
、好ましくは、熱膨張係数がs、oxl[T’/℃以上
のものを選定する。また、上記ポリイミド樹脂薄膜多層
部を構成するポリイミド樹脂としては、好ましくは、熱
膨張係数が2.0X101/l以下のものを選定する。The glass insulating layer constituting the glass thick film multilayer section is preferably selected from one having a coefficient of thermal expansion of s, oxl[T'/° C. or higher. Further, as the polyimide resin constituting the polyimide resin thin film multilayer section, a polyimide resin having a coefficient of thermal expansion of 2.0 x 101/l or less is preferably selected.
感光性ガラス板をパタニングした遮光マスクを用いて密
着露光し、露光部分圧酸エツチングされやすい微結晶を
析出させ、これを酸エツチングすることによ)高密度で
微細なスルーホールを同時1cff[よく形成すること
ができる。本発明は、このスルーホールを形成し九ガラ
ス板を従来技術のグリーンシート圧伏えて用い、Ag、
Au、 Ag/Pd、Ag/P t、 Au/P t
あるいはCu等の導電ペーストを配線材料とし、厚膜ス
クリーン印刷法で配線、端子の形成およびダイア充積を
行なう。A photosensitive glass plate is closely exposed using a patterned light-shielding mask to precipitate microcrystals that are easily acid-etched under the exposure partial pressure. can be formed. The present invention forms this through hole and uses nine glass plates by compressing the green sheet of the prior art, Ag,
Au, Ag/Pd, Ag/Pt, Au/Pt
Alternatively, a conductive paste such as Cu is used as the wiring material, and wiring, terminal formation, and diamond filling are performed by thick film screen printing.
次いで所定の回路層に応じて配線済みのガラス板を積層
した後、800〜900℃で熱処理してガラス板を一体
化するととも罠、機械的強度の高い結晶化ガラスに変化
させ、配線材料をガラスに焼付ける。熱処理の寸法変化
は一2%以下、その精度は±CLO5%以下であシ、従
来に比べて1桁寸法精度が向上できる。Next, after laminating the wired glass plates according to the predetermined circuit layers, the glass plates are heat-treated at 800 to 900°C to integrate them, and the glass plates are changed into crystallized glass with high mechanical strength, and the wiring material is Baked on glass. The dimensional change due to heat treatment is less than 12%, and its accuracy is less than ±CLO5%, and the dimensional accuracy can be improved by one order of magnitude compared to the conventional method.
以上の作用により、薄膜多層配線回路をよシ高密度、微
細に形成できるようになる。Due to the above-mentioned effects, thin film multilayer wiring circuits can be formed with higher density and finer details.
また、本発明は、ガラス多層配線基板とポリイミド樹脂
の熱膨張係数差をよシ少なくしているので、ガラスの多
層配線基板上に形成するポリイミド樹脂の膜厚を従来に
比べ、よう厚くかつ大面積に形成できるので、高集積、
大規模の多層配線基板が裏通できる。Furthermore, since the present invention greatly reduces the difference in thermal expansion coefficient between the glass multilayer wiring board and the polyimide resin, the film thickness of the polyimide resin formed on the glass multilayer wiring board can be made thicker and larger than before. Since it can be formed over a large area, it is highly integrated,
Large-scale multilayer wiring boards can be back-circuited.
〔実施例〕
本発明の多層配線基板およびその裂遣方法忙ついての実
施例を図面とともに説明する。[Example] An example of a multilayer wiring board and a method for tearing the same according to the present invention will be described with reference to the drawings.
第1図は不発8Aによる多層配線基板の一実施例の構造
を示す断面図である。FIG. 1 is a sectional view showing the structure of an embodiment of a multilayer wiring board based on the misfire 8A.
第1図において、本実施例の多層配線基板は、ガラス厚
膜多層部qと、ポリイミド樹脂#膜多層部Pとを積層し
て構成される。In FIG. 1, the multilayer wiring board of this embodiment is constructed by laminating a glass thick film multilayer part q and a polyimide resin # film multilayer part P.
ガラス厚膜多層部qは、複数枚(本実施例では4枚)の
ガラス絶縁層1に厚膜にて各々対応する層上配線3およ
びダイア2を設けて積層することにより形成される。ガ
ラス絶縁層1を形成するガラスとしては、熱膨張係数が
ポリイミド樹脂のそれと近いものを選定する。本実施例
ではaO×1σ1/℃以上のものを選定している。ダイ
ア2は、後述するように、各ガラス絶縁層IK各々対応
する位置に、エツチングによりスルーホールヲ設ケ、こ
のスルーホールに厚膜導体を充填することにより形成す
る。層上配線3は、各ガラス絶縁層1に各々印刷によ)
形成する。The glass thick film multilayer part q is formed by laminating a plurality of (four in this embodiment) glass insulating layers 1 with corresponding on-layer wiring 3 and dia 2 made of thick film. As the glass forming the glass insulating layer 1, a glass whose coefficient of thermal expansion is close to that of polyimide resin is selected. In this embodiment, a temperature of aO×1σ1/° C. or higher is selected. As will be described later, the dia 2 is formed by etching a through hole at a corresponding position in each glass insulating layer IK and filling the through hole with a thick film conductor. The layer wiring 3 is printed on each glass insulating layer 1)
Form.
また、ガラス厚膜多鳥部Gは、上記各ガラス絶縁層1を
積層して、溶融し、一体化しである。ガラス厚膜多層部
Gの下層となる面には、予め入出力用厚膜端子4が設け
である。この入出力用厚膜端子4は、上記ダイア2と接
続して設けである。Further, the glass thick film multi-layer part G is made by laminating the above-mentioned glass insulating layers 1, melting them, and integrating them. Thick film terminals 4 for input/output are provided in advance on the lower layer surface of the glass thick film multilayer portion G. This input/output thick film terminal 4 is connected to the dia 2 and provided.
また、ガラス厚膜多層部Gの上層となる面には、薄膜回
路接続用厚膜端子5が設けである。Further, on the upper surface of the glass thick film multilayer portion G, a thick film terminal 5 for thin film circuit connection is provided.
上記ポリイミド樹脂薄膜多層部Pは、ポリイミド樹脂絶
縁層6を、各層毎に薄膜およびめっきによυ層上配線8
およびダイア7を設けて積層することにより形成される
。ポリイミド樹脂絶縁層6を形成する樹脂としては、熱
膨張係数が上記ガラス絶縁層1のそれと近いものを選定
する。本実施例では、2.OX 10−’/’C以下の
ものを選定している。The above-mentioned polyimide resin thin film multilayer part P has a polyimide resin insulating layer 6 formed by thin film and plating for each layer to form wiring 8 on the υ layer.
and dia 7 are provided and stacked. As the resin forming the polyimide resin insulating layer 6, a resin whose coefficient of thermal expansion is close to that of the glass insulating layer 1 is selected. In this embodiment, 2. OX 10-'/'C or less is selected.
また、ポリイミド樹脂薄膜多層部Pは、本実施例では、
例えば後述する方法で、ポリイミド樹脂を塗布硬化して
厚さ30μmのポリイミド樹脂絶縁層6を形成し、これ
に層上記Iw8およびダイア7を設けた後、同5I!和
して、ポリイミド樹脂絶縁層6を形成し、多層構造とし
である。本実施例では、25層構造としである。ダイア
7は、ポリイミド樹脂絶縁層6の各々対応する位置に、
後述するよ5忙、プラズマエツチングによりスルーホー
ルを設げ、このスルーホールに無′flL解めっきによ
り0導体を充積することにより形成する。層上配縁8は
ポリイミド樹脂絶縁層6の各層毎に各々対応する位置に
、後述するよう和、スパッタリンク、7fトエツチング
および無電解めりきにより形成する。In addition, in this example, the polyimide resin thin film multilayer part P is as follows:
For example, by applying and curing a polyimide resin by the method described later, a polyimide resin insulating layer 6 having a thickness of 30 μm is formed, and the above-mentioned layers Iw8 and Dia 7 are provided thereon, and then the same 5I! Then, a polyimide resin insulating layer 6 is formed to have a multilayer structure. In this embodiment, a 25-layer structure is used. The diamonds 7 are placed at corresponding positions on the polyimide resin insulating layer 6.
As will be described later, a through hole is provided by plasma etching, and a zero conductor is filled in this through hole by non-flL deplating. The layered edges 8 are formed at corresponding positions on each layer of the polyimide resin insulating layer 6 by etching, sputter linking, 7F etching, and electroless plating, as will be described later.
このポリイミド粥腹絶縁ノー6の最下層に設けられるダ
イア7は、上記ガラス厚膜多層部qの上層に設けられて
いる薄膜回路接続用厚膜端子5と接続される。また、ポ
リイミド樹脂絶縁j−6の最上層には、LSI接続用端
子9およびその他の表面端子10が設けられている。こ
れらの為子9.10は、各々ポリイミド樹脂絶縁層6の
最上層に設けられているダイア7と接続される。The dia 7 provided in the lowermost layer of the polyimide porridge insulation layer 6 is connected to the thick film terminal 5 for thin film circuit connection provided in the upper layer of the glass thick film multilayer part q. Furthermore, LSI connection terminals 9 and other surface terminals 10 are provided on the top layer of the polyimide resin insulation j-6. These elements 9 and 10 are each connected to the dia 7 provided on the top layer of the polyimide resin insulating layer 6.
次忙、上記のように構成される多層配線基板の製造方法
について、上記第1図および第2図を参照して説明する
。Next, a method of manufacturing the multilayer wiring board configured as described above will be explained with reference to FIGS. 1 and 2.
第2図は、多層配線基板の製造プロセスを示すフローチ
ャートである。FIG. 2 is a flowchart showing the manufacturing process of the multilayer wiring board.
本実施例の多層配線基板の製造プロセスは、基本的には
、■厚膜多層配線基板の製作、■薄膜多層配線回路の製
作、■多層配線回路基板の製作の各工程からなる。以下
、この)@に説明する。The manufacturing process of the multilayer wiring board of this embodiment basically consists of the following steps: (1) manufacturing a thick film multilayer wiring board, (2) manufacturing a thin film multilayer wiring circuit, and (2) manufacturing a multilayer wiring circuit board. This)@ will be explained below.
(1) 厚膜多層配線基板の製作
まず、絶縁層1となる微1t(0,01%)の〜および
Auを添加したLi20−AI、03−7SiU、系感
光性ガラス板を、arm−tべき枚数分、次のよ5KL
、て作製する。1400℃で20h上記ガラスを溶融し
、この融液を金型に流し込んで冷却固化したインゴット
状のガラスを切断、研磨し、α25■厚、100■角の
ガラス板とする。(1) Production of thick film multilayer wiring board First, a fine 1t (0.01%) ~ and Au-added Li20-AI, 03-7SiU, photosensitive glass plate, which will serve as the insulating layer 1, is placed on an arm-t The next number is 5KL
, and make it. The above glass is melted at 1400° C. for 20 hours, the melt is poured into a mold, the ingot-shaped glass is cooled and solidified, and is cut and polished to form a glass plate having a thickness of α25 mm and a square size of 100 mm.
次に、上記形成したガラス板について、各別に用意した
Cr−Cr0膜により各回路層に応じてスルーホールパ
ターンヲハタニングした遮光マスクガラスを感光性ガラ
ス板上に密着して置く。この状態でマスクガラスの上方
から紫外線を5分間照射してスルーホールを設けようと
する感光性ガラス板の部分に垂直に紫外線を透過させる
。この透過部分は次の加熱処理によって、低い濃度のぶ
つ酸に溶けやすい結晶が形成される。上記露光済みのガ
ラス板を石英ガラス製の架台に載せ、空気中で530℃
、tshの加熱処理する。続いて上記ガラス板を3%の
ふり酸水溶液中に30分浸漬し、水洗、乾燥する。この
ようにして、最大径0.15■、最小径Q、06露、ピ
ッチα5■のスルーホールを形成する。Next, regarding the glass plate formed above, a light-shielding mask glass in which a through-hole pattern is patterned according to each circuit layer using a separately prepared Cr-Cr0 film is placed in close contact with the photosensitive glass plate. In this state, ultraviolet rays are irradiated from above the mask glass for 5 minutes to transmit the ultraviolet rays perpendicularly to the portion of the photosensitive glass plate where the through holes are to be provided. This transparent portion is subjected to a subsequent heat treatment to form crystals that are easily soluble in low concentrations of butic acid. The exposed glass plate was placed on a quartz glass stand and heated to 530°C in the air.
, tsh is heat-treated. Subsequently, the glass plate was immersed in a 3% fluoric acid aqueous solution for 30 minutes, washed with water, and dried. In this way, a through hole with a maximum diameter of 0.15 mm, a minimum diameter Q of 0.6 mm, and a pitch α of 5 mm is formed.
次に、上記各ガラス板全面に紫外線を4分照射し、高温
熱処理における結晶化に対する前処理を行なう。続いて
、厚膜スクリーン印刷により−ペーストを各々スルーホ
ール内部に充填してダイア2を形成後、各ガラス板表面
に必要な層上配線3の配線パターンをパタニングする。Next, the entire surface of each glass plate is irradiated with ultraviolet rays for 4 minutes to perform pretreatment for crystallization in high-temperature heat treatment. Subsequently, the inside of each through hole is filled with paste by thick film screen printing to form a diamond 2, and then a necessary wiring pattern of the layered wiring 3 is patterned on the surface of each glass plate.
ここで、最下層の裏面の、入出力端子4には、はんだ接
続強度を高めるためK Ag/Pdペーストを用いる。Here, K Ag/Pd paste is used for the input/output terminals 4 on the back surface of the bottom layer in order to increase the solder connection strength.
また、最上層の表面には、層上配線3のパターンととも
に薄膜配線回路部との接続のための端子5を形成してお
く。Further, on the surface of the uppermost layer, a pattern of the upper layer wiring 3 and a terminal 5 for connection with the thin film wiring circuit section are formed.
続いて、所定の層上配線5をパタニングしたガラス板を
回路構成に従って積層して、ガラスの軟化mm(6oo
℃)まで加熱する。ひき続き、軟化温度から結晶化処理
温度(850℃)までは、減圧排気しながら加圧、加熱
処理する。この結果、一体化したガラスの厚膜多層配線
回路基板が得られる。なお、本実施例では、加熱処理に
よるガラス板の寸法変化は、−160±CLO4チであ
シ、熱膨張係数はtIX10’/lであった。Subsequently, glass plates patterned with predetermined on-layer wiring 5 are laminated according to the circuit configuration, and the glass softens by mm (60 mm).
Heat to ℃). Subsequently, from the softening temperature to the crystallization treatment temperature (850° C.), pressurization and heat treatment are carried out while evacuation is under reduced pressure. As a result, an integrated glass thick film multilayer wiring circuit board is obtained. In this example, the dimensional change of the glass plate due to the heat treatment was -160±CLO4, and the thermal expansion coefficient was tIX10'/l.
(2)薄膜多層配線回路の製作 ′まず、ポリイ
ミド樹脂前駆体フェス(有機ジアミン、膏機シリル、有
機テトラカルボン酸二無水物をN−メチルピロリドン1
.N−ジメチルアセトアミドの有機溶剤に痔解し、縮合
反応させたもの)のスピンナ塗布と、乾燥加熱(200
〜360℃、50分)硬化とt−S返し、厚さ50μm
のポリイミド樹脂絶縁層6を、ガラス厚膜多層配線基板
上全面に形成する。(2) Production of thin film multilayer wiring circuit 'First, polyimide resin precursor face (organic diamine, silyl silyl, organic tetracarboxylic dianhydride, N-methylpyrrolidone 1
.. N-dimethylacetamide dissolved in an organic solvent and subjected to a condensation reaction) was applied with a spinner, and dried and heated (200
~360℃, 50 minutes) Curing and t-S return, thickness 50μm
A polyimide resin insulating layer 6 is formed over the entire surface of the glass thick film multilayer wiring board.
このポリイミド樹脂絶縁層6上に、有機ケイ素高分子材
料のP−シメン溶液をスピンナ塗布し、100℃、50
分加熱処理して7rトレジス)fflを形成する。更に
、レジスト層上に、厚膜多層配線回路と薄膜多層配線回
路との接続のためのダイア用スルーホールをマスク露光
してパタニングし、イソプロピルアルコールとトルエン
の混合溶剤で現像した後、イソプロピルアルコールで洗
浄スる。On this polyimide resin insulating layer 6, a P-cymene solution of an organosilicon polymer material was applied using a spinner, and
A 7r tresist) ffl is formed by heat treatment for 10 min. Furthermore, on the resist layer, through-holes for diamonds for connecting the thick-film multilayer wiring circuit and the thin-film multilayer wiring circuit were patterned by mask exposure, developed with a mixed solvent of isopropyl alcohol and toluene, and then patterned with isopropyl alcohol. Wash.
次いで、#R素プラズマエツチングL日ポリイミド樹脂
膜に20μm角のスルーホールを形成する。Next, a 20 μm square through hole is formed in the #R plasma etched polyimide resin film.
なお、ポリイミド樹脂膜の面積は95tm角である。Note that the area of the polyimide resin film is 95 tm square.
続いて、無電解Cuめりきにより当該スルーホールK
Cu導体を充填して、ダイア7を形成する。Subsequently, the through hole K is formed by electroless Cu plating.
A dia 7 is formed by filling with a Cu conductor.
ソシテ、スパッタデボジン1ンによって基板全面に11
00n厚のCr膜そして350 nm厚のCu[を形成
後、Cu膜上に感光性レジスト膜を信号配線導体となる
個所を除いて形成し、信号配線導体となる部分に10μ
m厚のCuめっき模を形成する。次いで、前記感光性l
/シスト膜を除去した後、このレジスト膜の下にあった
Cu膜、Cr膜をエッチング除去して、ポリイミド樹脂
膜上に第1の信号用層上記HI8を形成する。11 on the entire surface of the substrate by sputter deposition 1
After forming a 00 nm thick Cr film and a 350 nm thick Cu film, a photosensitive resist film was formed on the Cu film except for the areas that would become signal wiring conductors, and a 10 μm thick resist film was formed on the areas that would become signal wiring conductors.
A Cu plating pattern with a thickness of m is formed. Then, the photosensitive l
After removing the cyst film, the Cu film and Cr film under the resist film are removed by etching, and the first signal layer HI8 is formed on the polyimide resin film.
そして、再びポリイミド樹脂膜の形成、フォトレジスト
膜形成、フォトレジスト膜へのスルーホールパターン形
成、プラズマエツチングによるポリイミド樹脂膜のスル
ーホール形成、スルーホール内部への無電解Cuめりき
Kよる導体充填、スパッタデボクシ1ンによるCr膜と
Cu膜の形成、感光性レジスト膜を信号配線導体となる
個所を除いて形成し、無電解Cuめりき、感光性レジス
ト膜の除去、感光性レジスト膜下にあったCu膜とCr
膜の除去の工程を数繰返して、25層の薄膜多層回路を
形成する。このようにして得られ九ポリイミド樹脂の厚
さは、750μm、樹脂の熱膨張係数はt5)lO−7
/℃であった。Then, again forming a polyimide resin film, forming a photoresist film, forming a through hole pattern on the photoresist film, forming a through hole in the polyimide resin film by plasma etching, filling the inside of the through hole with a conductor by electroless Cu-plating K, Formation of Cr film and Cu film by sputter deboxing, formation of photosensitive resist film except for areas that will become signal wiring conductors, electroless Cu plating, removal of photosensitive resist film, and formation of photosensitive resist film under the photosensitive resist film. The existing Cu film and Cr
The film removal process is repeated several times to form a 25-layer thin film multilayer circuit. The thickness of the nine polyimide resin thus obtained is 750 μm, and the coefficient of thermal expansion of the resin is t5) lO-7
/℃.
なお、薄膜回路の最上層にはLSIチップ接続用の端子
9、導通検査用端子10等が形成される。Note that terminals 9 for LSI chip connection, terminals 10 for continuity testing, etc. are formed on the top layer of the thin film circuit.
(3) 多層配線回路基板
以上により64個の5++wa角LSIチップを搭載す
る多層配線回路基板を製造することができる。この基板
の熱膨張係数はtIX1cr@/1:でSiチップの熱
膨張係数(4×1ff″?/℃)との差が大きいが、こ
れは熱膨張係数差を吸収する接続方法により解消される
。(3) Multilayer wiring circuit board With the above method, it is possible to manufacture a multilayer wiring circuit board on which 64 5++wa square LSI chips are mounted. The thermal expansion coefficient of this board is tIX1cr@/1: which is a large difference from the thermal expansion coefficient of the Si chip (4 x 1ff''?/℃), but this can be resolved by a connection method that absorbs the difference in thermal expansion coefficient. .
また基板の裏面には入出力ビンがはんだ接続される。Input/output bins are also soldered to the back side of the board.
なお、ポリイミド樹脂の熱膨張係数が2.oxNj”7
℃を超えると基板との剥離を防止する効果が小さい。Note that the thermal expansion coefficient of polyimide resin is 2. oxNj”7
If the temperature exceeds .degree. C., the effect of preventing separation from the substrate is small.
以上説明したように1本発明によれば、(1)高密度で
微細なスルーホールが全面、同時に形成され、また熱処
理による寸法変化が小さく、その精度が従来に比して1
0倍向上したため、厚膜多層配線回路のダイアの位置精
度が向上し、薄膜多層配線回路接合のための端子面積を
小さくできるため、従来和比して大幅に配線の高集積化
を達成することができる。As explained above, according to the present invention, (1) high-density and fine through-holes are formed simultaneously on the entire surface, and the dimensional change due to heat treatment is small, and the accuracy is 1.
Because of the 0x improvement, the positioning accuracy of the diamonds in thick film multilayer wiring circuits is improved, and the terminal area for bonding thin film multilayer wiring circuits can be reduced, making it possible to achieve significantly higher wiring integration than conventional sum. Can be done.
(2)熱膨張係数の大きな(例えば11X101/℃程
度の)ガラス基板を用いるため、ポリイミド樹脂薄膜多
層配線回路との熱膨張係数の差が従来に比して小さくな
)、多層配線基板製造時および温度サイクル等のために
生じる樹脂膜と基板の剥離が無(な夛、配線層数をさら
に増すこと、あるいは薄膜多層配線回路部の1lIIY
!itを更く広げることかできる。(2) Since a glass substrate with a large coefficient of thermal expansion (for example, about 11×101/°C) is used, the difference in coefficient of thermal expansion between the polyimide thin film multilayer wiring circuit and the polyimide resin thin film multilayer wiring circuit is smaller than before. Also, there is no need to peel off the resin film and the substrate due to temperature cycling, etc., further increase the number of wiring layers, or increase the number of wiring layers in the thin film multilayer wiring circuit section.
! It is possible to further expand IT.
第1図は本発明による多層配線基板の断面図、第2因は
本発明による多層配線基板の製造プロセスを示すフロー
チャートである。
1・・・ガラス絶縁層、2・・・ダイア(厚膜)、5・
・・層上配線、4・・・入出力用厚膜端子、5・・・薄
膜回路接続用厚膜漏子、6・・・ポリイミド樹脂絶縁層
、7・・・ダイア(めりき)、8・・・層上配線、9・
・・ぴ工接続用端子、10・・・その他の表面端子。
−、
躬 1 ロ
斗 入出力用層」美憫J 70ゼの飢の表顔端壬5
薄I11回訃凌穀閂膿謁壬FIG. 1 is a sectional view of a multilayer wiring board according to the present invention, and the second factor is a flowchart showing a manufacturing process of the multilayer wiring board according to the present invention. 1...Glass insulating layer, 2...Dia (thick film), 5...
... Layer wiring, 4... Thick film terminal for input/output, 5... Thick film leaker for thin film circuit connection, 6... Polyimide resin insulation layer, 7... Dia (Meriki), 8...・Upper layer wiring, 9・
...Picture connection terminal, 10...Other surface terminals. -, 躬 1 Roto Input/output layer "Mei J 70 Ze's hunger front face Endi 5
The 11th time of Bo I
Claims (1)
する絶縁層とを交互に積層して形成する多層配線基板に
おいて、 上下絶縁層として、互いに熱膨張係数の近いガラスとポ
リイミド樹脂とを選定して、前者によりガラス厚膜多層
部を形成し、後者によりポリイミド樹脂薄膜多層部を形
成すると共に、両者を積層し、 上記ガラス厚膜多層部は、複数枚のガラス絶縁層に厚膜
にて各々対応する層上配線および層間配線を設けて積層
することにより形成し、上記ポリイミド樹脂薄膜多層部
は、ポリイミド樹脂絶縁層を、各層毎に薄膜およびめっ
きにより層上配線および層間配線を設けて積層すること
により形成して構成したことを特徴とする多層配線基板
。 2、上記ガラス厚膜多層部を構成するガラス絶縁層とし
て、熱膨張係数が8.0×10^−^7/℃以上のもの
を選定し、かつ、上記ポリイミド樹脂薄膜多層部を構成
するポリイミド樹脂絶縁層として、熱膨張係数が2.0
×10^−^6/℃以下のものを選定する特許請求の範
囲第1項記載の多層配線基板。 3、配線層と、上下配線間を電気的に接続する配線を有
する絶縁層とを交互に積層して多層配線を行なう多層配
線基板の製造方法において、ポリイミド樹脂と熱膨張係
数が近いガラス絶縁層を複数枚揃え、該各ガラス絶縁層
の各々設定された位置に、マスクを介してエッチングす
ることによりスルーホールを設けた後、厚膜導体を印刷
して層上配線を設けると共に、スルーホールに厚膜導体
を充填して層間配線を設け、上記各ガラス絶縁層を積層
して溶融することにより一体化してガラス厚膜多層部を
形成し、上記ガラス厚膜多層部上に、ポリイミド樹脂絶
縁層を積層し、 該ポリイミド樹脂絶縁層は、積層される各樹脂層毎にス
ルーホールを設け、かつ、薄膜およびめっきにより層上
配線を設けると共に、該スルーホールを導通させて層間
配線を形成することを特徴とする多層配線基板の製造方
法。 4、上記ガラス厚膜多層部を構成するガラス絶縁層とし
て、熱膨張係数が8.0×10^−^7/℃以上のもの
を選定し、かつ、上記ポリイミド樹脂薄膜多層部を構成
するポリイミド樹脂絶縁層として、熱膨張係数が2.0
×10^−^6/℃以下のものを選定する特許請求の範
囲第3項記載の多層配線基板の製造方法。[Claims] 1. In a multilayer wiring board formed by alternately laminating wiring layers and insulating layers having wiring for electrically connecting the upper and lower wirings, the upper and lower insulating layers have thermal expansion coefficients that are different from each other. By selecting similar glass and polyimide resin, the former forms a glass thick film multilayer part, the latter forms a polyimide resin thin film multilayer part, and both are laminated. The polyimide resin thin film multilayer part is formed by laminating a glass insulating layer with thick film on each layer and interlayer wiring. A multilayer wiring board characterized in that it is formed by providing wiring and interlayer wiring and laminating them. 2. As the glass insulating layer constituting the glass thick film multilayer section, select one with a coefficient of thermal expansion of 8.0 x 10^-^7/℃ or more, and the polyimide constituting the polyimide resin thin film multilayer section. As a resin insulation layer, the thermal expansion coefficient is 2.0.
The multilayer wiring board according to claim 1, wherein the multilayer wiring board is selected to have a temperature of not more than ×10^-^6/°C. 3. In a method for manufacturing a multilayer wiring board in which wiring layers and insulating layers having wiring for electrically connecting upper and lower wirings are laminated alternately to perform multilayer wiring, a glass insulating layer having a coefficient of thermal expansion similar to that of a polyimide resin is used. After arranging a plurality of glass insulating layers and etching them through a mask to form through-holes at predetermined positions in each glass insulating layer, a thick film conductor is printed to provide wiring on the layer, and the through-holes are etched. A thick film conductor is filled to provide interlayer wiring, the above glass insulating layers are laminated and melted to form a glass thick film multilayer part, and a polyimide resin insulating layer is formed on the glass thick film multilayer part. The polyimide resin insulating layer is provided with a through hole for each resin layer to be laminated, and an on-layer wiring is provided by thin film and plating, and the through hole is made conductive to form an interlayer wiring. A method for manufacturing a multilayer wiring board, characterized by: 4. Select a glass insulating layer that has a thermal expansion coefficient of 8.0 x 10^-^7/°C or more as the glass insulating layer constituting the glass thick film multilayer part, and a polyimide constituting the polyimide resin thin film multilayer part. As a resin insulation layer, the thermal expansion coefficient is 2.0.
The method for manufacturing a multilayer wiring board according to claim 3, wherein a temperature of not more than ×10^-^6/°C is selected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14307587A JPS63307797A (en) | 1987-06-10 | 1987-06-10 | Multilayer interconnection substrate and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14307587A JPS63307797A (en) | 1987-06-10 | 1987-06-10 | Multilayer interconnection substrate and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63307797A true JPS63307797A (en) | 1988-12-15 |
Family
ID=15330331
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14307587A Pending JPS63307797A (en) | 1987-06-10 | 1987-06-10 | Multilayer interconnection substrate and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63307797A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03196695A (en) * | 1989-12-26 | 1991-08-28 | Fujitsu Ltd | Manufacture of multilayer thin film circuit substrate |
JPH04290494A (en) * | 1990-11-29 | 1992-10-15 | Siemens Nixdorf Inf Syst Ag | Multilayer printed circuit board |
US6399891B1 (en) | 1999-06-29 | 2002-06-04 | Sony Chemicals Corporation | Multilayer boards |
JP2006147932A (en) * | 2004-11-22 | 2006-06-08 | Kyocera Corp | Multilayer wiring board and its manufacturing method |
-
1987
- 1987-06-10 JP JP14307587A patent/JPS63307797A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03196695A (en) * | 1989-12-26 | 1991-08-28 | Fujitsu Ltd | Manufacture of multilayer thin film circuit substrate |
JPH04290494A (en) * | 1990-11-29 | 1992-10-15 | Siemens Nixdorf Inf Syst Ag | Multilayer printed circuit board |
US6399891B1 (en) | 1999-06-29 | 2002-06-04 | Sony Chemicals Corporation | Multilayer boards |
JP2006147932A (en) * | 2004-11-22 | 2006-06-08 | Kyocera Corp | Multilayer wiring board and its manufacturing method |
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