JPS63304358A - Bus control system - Google Patents

Abstract

PURPOSE:To decrease the number of terminals used by a bus connector by using a specific signal of a control signal line to perform the switch to decide a specific one of plural buses to which a common signal line is used. CONSTITUTION:For a memory access given to a MEM 102 from a CPU 101, an address/data signal line 106 is switched and a memory address is validated. Then a memory access is started after a memory request signal is activated on a bus control signal line 104. A wait signal is kept active on the line 104 until the data is fixed and then inactivated when the memory data is validated. Thus a memory access is through. An address strobe signal is activated on an I/O bus control signal line 105 is activated after the line 106 is switched and the address is validated for an access given to an I/O 103 from the CPU 101. Then an I/O access is started. Thus it is possible to decrease the number of terminals used to a bus connector of an information processor to which plural buses are connected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control method, and particularly to a bus control method in an information processing system in which a plurality of buses with different control methods are used between a plurality of information processing devices.

[Conventional technology]

Conventionally, in this type of bus control method, multiple buses with different control methods that connect each information processing device in an information processing system are connected based on different interface technologies depending on the need for data transfer between each information processing device. was designed and controlled.

For example, the central processing unit (hereinafter referred to as C
PU (Central Processing U)
nit) and memory device (hereinafter referred to as MEM (ME
A memory bus for transferring data between the CPU and the input/output device (hereinafter referred to as ILO).
The I10 bus for transferring data between devices (referred to as input output devices) is designed and controlled based on different interface technologies.

That is, since the memory bus is required to have a data transfer rate that allows high-speed access and a wide address space, it requires many signal lines for address/data transfer. On the other hand, the I10 bus is a memory bus that does not require any high data transfer speed or wide address space, but in addition to the address/data signal lines for transferring addresses/data, the I10 bus also has control lines for transferring interrupt signals, etc. Depending on the difference in the need for signal lines (not that the memory bus does not require any control signals), the design and control methods for both buses are different.

FIG. 2 is a block diagram showing the configuration of an example of a conventional bus control system. This bus control system includes a CPU 201, a MEM 202, and an 110203.

A memory bus control signal line 204 and a memory address/data signal line 20 are connected between CP 0201 and MEM 202.
6 (memory bus control signal line 204
and the memory address/data signal line 206 constitute a memory bus).

Between CP 0201 and l10203, there is an I10 bus control line 205 and an I10 address/data signal line 207.
(I10 bus control line 205 and I
10 address/data signal lines 207 constitute an I10 bus).

FIG. 3 is a time chart of signals showing an example of a memory bus control method in the bus control method shown in FIG.

Memory address/data (MADO) transmitted by CPU U2O5 on memory address/data signal line 206
-31), the memory address is valid (MADO-3
1 is set to the value of the determined memory address), and the memory request signal MRQ on the memory bus control signal line 204 is activated (at the same time, it indicates the content of the processing (read/write processing, etc.) requested by the CPU 205. command commercial
D is transmitted onto the memory bus control signal line 204), memory access is started.

In response to this, the MP and M2O2 sides wait until the data is finalized (
The shaded area in MADO-31 in FIG. 3 indicates a state in which data is not determined. 10DO- in Figure 4
15 and MADO-15/10AO-1 in FIG.
5 and MA D16-31/I OD 0-15), the wait signal WAIT is activated on the memory bus control signal line 204, and the MADO
WAIT at the same time that the memory data is valid at -31
becomes inactive, memory access ends, and MA
Memory data code valid for DO-31/
Write processing and the like are performed based on the timing of a clock pulse (not shown).

FIG. 4 is a signal time chart showing an example of the I10 bus control method in the bus control method shown in FIG.

When the address strobe signal As on the I10 bus control control line 205 is activated after the I10 address is made valid by the CPU U2O5 on l0AO-15 transmitted on the I10 address/data signal line 207, the I1
0 access is started.

In response to this, on the l10203 side, I
The response signal DTACK is made inactive on the I10 bus control line 205, and the I10 address/data signal line 2
After I10 data is validated in 10DO-15 transmitted in 07, DTACK becomes active and I10 access is completed, and input/output processing of I10 data is completed by DTACK.
is performed while it is active.

[Problem that the invention seeks to solve]

The disadvantage of the conventional bus control method described above is that in an information processing system that uses multiple buses with different control methods, a large number of terminals are required for the bus connector of an information processing device to which multiple buses are connected. There is.

For example, in the bus control system shown in FIG. 2, the bus connector on the printed circuit board of the cP U2O5 is The CPU 201 and MEM are used independently.
Since 2O2 and l10203 are connected, a bus connector with a large number of usable terminals is CPU2O5.
The disadvantage is that it is required.

In view of the above-mentioned points, an object of the present invention is to provide a bus control system that can reduce the number of used terminals of a bus connector of an information processing device to which a plurality of buses are connected in an information processing system that uses a plurality of buses with different control methods. The purpose is to provide a method.

[Means for solving problems]

The bus control method of the present invention provides, in an information processing system using a plurality of buses with different control methods, a control signal line provided uniquely to each bus of the plurality of buses, and a By activating a common signal line commonly used in the bus and a specific control signal on the control signal line, the content of the signal transmitted by the common signal line can be transferred to any one of the plurality of buses. and a bus control unit that controls the plurality of buses so that they are not used at the same time by performing switching to suit the bus.

[Effect]

In the bus control method of the present invention, a control signal line is provided uniquely to each of the plurality of buses, and a common signal line is commonly used by the plurality of buses.
By enabling a specific control signal on the control signal line, the bus control unit switches the content of the signal transmitted by the common signal line to suit one of the plurality of buses. busses are not used at the same time.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the bus control method of the present invention.
It is configured to include a UIOI, MEM 102, and l10103.

The CP UIOI and the MEM 102 are connected by a memory bus control signal line 104 and an address/data signal line 106 (the memory bus is configured by the memory bus control signal line 104 and the address/data signal line 106). ).

Between CPU101 and l10103,! 10 bus control line 105 and address/data signal line 106 (I10 bus control line 105 and address/data signal line 106).
The data signal line 106 constitutes an I10 bus).

Is the address/data signal line 106 a memory bus system? 1"
A specific memory bus control signal on signal line 104 (a memory bus control signal that indicates that address/data signal line 106 is used in the form of a memory bus) and a specific I10 bus control signal on I10 bus control control line 105. signal (instructing that the address/data signal line 106 is used in the form of an 110 bus) When any of the I10 bus control controllers is valid, the memory bus and I10 bus corresponding to that valid control signal are activated. address for any/
This is a common signal line used as a data signal line.

Next, the operation of the bus-based tlB system of this embodiment configured as described above will be explained. Here, the operation when the memory bus and I10 bus are controlled as shown in the signal time chart of FIG. 5 will be described.

MAD indicating the upper 16 bits of memory address/data
10AO indicating 16 bits of O-15 and I10 address
A common terminal is used for the CPU connector (not shown) through which data is transmitted and received between MAD16-31 and I/O chip, which indicate the lower 16 bits of memory address/data. 10DO-15 indicating 17116 bits is transmitted/received from CPU10I.
The bus connectors above use the same terminals. Whether the address/data signal line 106 connected to these used terminals is used as a memory bus for MADO-15 and MAD16-31 or as an I10 bus for l0AO-15 and l0DO-15. This switching is performed exclusively by cPUlol, which functions as a bus control unit (memory bus and I10
bus) so that they are not used at the same time.

Here, when memory access is first performed from c putot to MEM 102, CPU 101
(by enabling a specific memory bus control signal on the memory bus control signal line 104), the address/data signal line 106 is controlled by MADO-15 and MAD16-3.
1 is used.

Next, MADO-3 on address/data signal line 106
1, the memory address is validated, and the memory request signal MRQ on the memory bus control signal line 104 is activated (at the same time, the command CMD indicating the content of processing (read/write processing, etc.) requested by CPU10I is activated for memory bus control. (transmitted on signal line 104), memory access is initiated.

In response, on the MEM 102 side, the wait signal WAIT is made active on the memory bus control signal line 104 until the data is confirmed, and at the same time when the memory data is valid in MADO-31, WAIT is made inactive and memory access is disabled. read/write processing of memory data that is valid for MADO-31 is performed based on the timing of a clock pulse (not shown) (the period indicated by "memory access" in Fig. 5 is (including the period for this read/write processing, etc.).

On the other hand, ■1 from CP Ulol to l10103
0 access, control of CPLIIOI (specific
(by enabling the bus control), the address/data signal lines 106 are connected to l0AO-15 and 10DO-15.
A switch is made to use it for this purpose.

Then l0AO-1 on address/data signal 1106
After the I10 address is validated at 5, the I10 access is started when the address strobe signal As on the I10 bus control line 105 is activated.

In response to this, on the l10103 side, I
10 bus control control line 105 is made inactive, and after 110 data is made valid in l0DO-15, DTACK is made active and I10
The access is completed and I10 data input/output processing is completed by DTA.
This is performed while CK is active (the period indicated by "10 access" in FIG. 5 includes this input/output processing period).

In this embodiment, a case has been described in which the bus control method of the present invention is implemented in an information processing system configured as shown in FIG. 1, but it goes without saying that the bus control method is not limited to such a configuration.

〔Effect of the invention〕

As explained above, in an information processing system that uses a plurality of buses with different control methods, the present invention provides switching for which of the plurality of buses a common signal line used in common by the plurality of buses is used. By performing this using a specific control signal on the control signal line, there is an effect that the number of used terminals of a bus connector of an information processing device to which a plurality of buses are connected can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of an example of a conventional bus control system, and FIG. 3 is a block diagram showing the configuration of an example of a conventional bus control system. FIG. 4 is a signal time chart showing an example of a memory bus control method in the conventional bus control method shown in FIG.
5 is a signal time chart showing an example of the control method for the 0 bus, and FIG. 5 is a signal time chart showing an example of the control JTJ method for the memory bus and I/○ bus in the bus control method of the present embodiment shown in FIG. It is. In the figure, 101...CPU. 102...MEM. 103...Ilo, 104...Memory bus control signal line, 105.
. . . I10 bus control B signal line, 106 . . . Address/data signal line.

Claims (1)

[Scope of Claims] In an information processing system that uses a plurality of buses with different control methods, a control signal line provided uniquely to each of the plurality of buses and a control signal line that is common to the plurality of buses is provided. a common signal line used for the control signal line; and adapting the content of the signal transmitted by the common signal line for any one of the plurality of buses by activating a specific control signal on the control signal line. a bus control unit that performs switching to prevent the plurality of buses from being used at the same time;