JPS63304356A - Check system for normalcy of dma data - Google Patents

Abstract

PURPOSE:To improve the reliability of the transferred data by adding the check data to the transferred data and collating this check data with the check data transferred previously. CONSTITUTION:A check means 70 is provided to a transferring device 7 to check the errors of a transferred data block DB and to produce the check data CD. While a memory means 60 is provided to a transferred device 6 to hold the data CD. When the block DB is transferred, the device 7 adds the data CD to the block DB and then transfers to the device 6 via a memory access. At the same time, the data CD is separately transferred and stored into the means 60, and collated with the check data CD added previously to the block DB. Thus the normalcy of the block DB is checked. In such a way, the normal transfer of the DMA data is checked and the reliability is improved for the transferred data.

Description

[Detailed Description of the Invention] [Summary] A transfer source device performs an error check on a transfer data block, adds check data to the transfer data block, and performs DMA (D
Direct Memory Access (direct memory access) is used to transfer the test data to the destination device, and 1.In addition to the above, test data alone is also transferred and stored in the storage means of the destination device, and the test data that has been transferred via DMA is transferred to the destination device. The normality of the transferred data is verified by comparing the data with the test data stored in the storage means.

[Industrial application field]

The present invention relates to a normality checking method for DMA data transfer.

The normality check method of the present invention is to (1) check whether or not DMA data transfer between the main body side information processing device and the auxiliary storage device, between the input/output device, or between the auxiliary storage devices is performed normally. It is something.

[Conventional technology]

Conventional 1 For example, when data is transferred by DMA between an information processing device on the main body side and an auxiliary storage device.

It is generally not checked whether the transfer data sent from each is transferred normally. Therefore, if a data block to be transferred is corrupted during transfer, the abnormal data is treated as normal, resulting in a lack of reliability.

On the other hand, a method has also been proposed in which the normality of data transfer is checked by performing a vertical parity check on transfer data and adding a parity bit to the transfer data before transfer.

[Problem that the invention seeks to solve]

The data is transferred, for example, by transferring one byte of data in parallel via a data bus.

When a vertical parity bit is added and transferred, the number of signal lines on the data bus must be increased by one for the parity bit, which is not economical and has the problem of increasing the size of the device.

Therefore, an object of the present invention is to improve the reliability of transferred data by making it possible to check whether DMA data transfer has been performed normally without increasing the number of signal lines for parity bits. The purpose of the present invention is to provide a method for checking the normality of transfer.

[Means for solving problems]

FIG. 1 is a block diagram of the principle according to the present invention.

The present invention is a DMA data transfer method in which a data block is transferred between two or more devices by direct memory access, and the transfer source device 7 performs an error check on the data block DB to be transferred and provides check data CD. A test means 70 for generating test data C is provided, and the test data C is sent to the transfer destination device 6.
A storage means 60 for holding data D is provided, and when transferring the data block DB, the test data CD is added to the transfer data block DB in the transfer source device 7, and the data is transferred to the transfer destination device 6 by direct memory access. The inspection data CD is transferred from the transfer source device 7 to the storage means 60 of the transfer destination device 6 and stored separately from the transfer data block DB, and in the transfer destination device 6, the check data CD stored in the storage device 60 and the direct memory are stored. A DMA configured so that the normality of the transferred data block is checked by comparing it with the check data CD that is added to the transferred data block DB and transferred upon access.
A data transfer health checking scheme is provided.

[For production]

The transfer source device 7 performs an error check on the transferred data block to create a test data CD, and this test data C
D is transferred to the storage means 60 of the destination device 6 and stored therein.

Further, the test data CD is added to the transfer data block DB, and the DMA data is transferred from the transfer source device 7 to the transfer destination device 6. The transfer destination device 6 compares the inspection data CD added to the data block DB to which the DMA data has been transferred with the inspection data CD stored in the storage means 60,
If they match, the transferred data block DB
is judged to be normal, and if it does not match, it is judged to be abnormal.

〔Example〕

The present invention will be described in detail below with reference to one drawing.

FIG. 2 is a block diagram showing an information processing system that performs a DMA data transfer normality check method as an embodiment of the present invention. In the figure, l is the main body side information processing device, 2 is the file memory controller, 3 is the floppy disk device,
4 is a hard disk device, and 5 is a bus. The file memory controller 2 is a device for controlling data transfer between the floppy disk device 3 and hard disk device 4 as auxiliary storage devices and the information processing device 1, and is connected to the information processing device 1 via a bus 5. ing.

The information processing device 1 includes a central processing device 10. main storage device 11;
Sum check register 12. It is configured to include a DMA controller 13 and the like. The file memory controller 2 includes a microprocessor 20. ROM21. No＼Nofa Memory 22. Sum check register 23. Status registers 24 and 25. Command register 26° floppy disk controller 27. It is configured to include a hard disk controller 28. Here, the command register 26 is a register for sending a command from the information processing device 1 to the file memory controller 2, and the status register 24 is a register that indicates the completion of a command and the operating state of the file memory controller 2. Reference numeral 25 is a register that displays the completion status of the file memory controller 2, that is, whether or not the processing has ended normally.

The operation of the embodiment system will be explained below. It is now assumed that the data in the floppy disk device 3 is to be transferred via DMA data to the information processing device 1 via the file memory controller 2. The information processing device 1 sends a read data command to the command register 26 of the file memory controller 2 via the bus 5 to set it. Command register 26
When a command is sent to the microprocessor 20
is interrupted and microprocessor 20 reads and executes the contents of command register 26. On this occasion,
A busy indication is set in the status register 24 to prevent other interrupts from occurring.

Next, according to the program stored in the ROM 21, the microprocessor 20 temporarily stores the transfer data held in the floppy disk device 3 in the buffer memory 22 via the floppy disk controller 27. When 256 bytes of data is stored in the buffer memory 22, it is transferred to the main storage device 11 of the information processing device 1 by DMA transfer, but before this DMA transfer, as shown in FIG.

A sum check is performed on the 256-byte data as a 16-bit x 128-word block, and the check word CW is
Create. This sum check is performed by adding each bit of one word of data in the word direction and taking the complement of the least significant digit of the addition result to create a check word CW.

The check word CW created in this way is transferred from the file memory controller 2 to the sum check register 12 of the information processing device 1 by five normal data transfers and stored therein before the DMA transfer of the data block. Next, the created check word CW is added to the end of the transfer data block, and the DMA data is transferred from the buffer memory 22 to the main storage device 11 under the control of the DMA controller 13.

In the information processing device 1, the transferred data is stored in the main storage device 1.
1, the central processing unit 10 reads the check word CW added to the end of the transfer data and compares this with the check word CW stored in the sum check register 12. If both match, DM
It can be determined that the A transfer was performed normally, and if there is no failure, it can be determined that an abnormality such as data block corruption has occurred.

Note that similar processing is performed when DMA data is transferred from the information processing device l side to the file memory controller 2, and the check word CW created in the information processing device 1 is transferred to the sum check register 2 of the file memory controller 2.
3 and is stored in the DMA by the microprocessor 20.
Verified after data transfer to check the normality of the transfer.

Various modifications are possible in carrying out the invention. For example, in the above embodiment, the check word CW was transferred to the transfer destination device before DMA data transfer, but of course, the DMA
The check word CW may be transferred after data transfer. Furthermore, although the above embodiment describes DMA data transfer between the information processing device and the storage device, the present invention is not limited thereto.

The present invention is also applicable to DMA data transfer between storage devices, DMA data transfer between an information processing device and an input/output device, and the like.

〔Effect of the invention〕

According to the present invention, it is possible to check whether data has been transferred normally by DMA data, and the reliability of transferred data is improved. In addition, since there is no need to increase the number of signal lines for vertical parity check of the data bus in the test, it is economical and the device does not become large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle according to the present invention, FIG. 2 is a block diagram of an information processing system that performs a normality check method for DMA data transfer as an embodiment of the present invention, and FIG.
FIG. 2 is a diagram showing an example of a configuration of a data block to which DMA data is transferred in the system. 1-1 Information processing device 2-File memory controller 3-Floppy disk 'AW 4-Hard disk device 5...-Bus 10-Central processing unit 11--Main storage device 12-Sum check register 13--DMA controller 20 -Microprocessor 21--ROM 22-Buffer memory 23-Sum check register 24-Status register 25--Status register 26--Command register

Claims (1)

[Claims] A DMA data transfer method for transferring data blocks between two or more devices by direct memory access, the data block to be transferred (DB
) is provided with a checking means (70) for generating test data (CD) by performing an error check, and a storage means (60) for holding the test data (CD) is provided in the destination device (6), When transferring (DB), transfer source device (
In step 7), the test data (CD) is added to the transfer data block (DB), and the data is transferred to the transfer destination device (6) by direct memory access.
) is transferred from the transfer source device (7) to the storage means (60) of the transfer destination device (6), and is stored separately from the transfer destination device (6).
), the check data (CD) stored in the storage means (60) is compared with the check data (CD) added to the transfer data block (DB) and transferred by direct memory access, and the transfer data block is processed. A normality check method for DMA data transfer configured to perform a normality check.