JPS63293952A - Forming method for semiconductor element connection terminal - Google Patents
Forming method for semiconductor element connection terminalInfo
- Publication number
- JPS63293952A JPS63293952A JP62128190A JP12819087A JPS63293952A JP S63293952 A JPS63293952 A JP S63293952A JP 62128190 A JP62128190 A JP 62128190A JP 12819087 A JP12819087 A JP 12819087A JP S63293952 A JPS63293952 A JP S63293952A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- pellet
- hydrogen plasma
- flux
- ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 229910000679 solder Inorganic materials 0.000 claims abstract description 47
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000001257 hydrogen Substances 0.000 claims abstract description 21
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 21
- 230000007246 mechanism Effects 0.000 claims abstract description 20
- 239000012298 atmosphere Substances 0.000 claims abstract description 8
- 238000001816 cooling Methods 0.000 claims abstract description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims 1
- 239000008188 pellet Substances 0.000 abstract description 23
- 230000004907 flux Effects 0.000 abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 abstract description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 238000002844 melting Methods 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000005394 sealing glass Substances 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 235000008331 Pinus X rigitaeda Nutrition 0.000 description 1
- 235000011613 Pinus brutia Nutrition 0.000 description 1
- 241000018646 Pinus brutia Species 0.000 description 1
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000003507 refrigerant Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000012945 sealing adhesive Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、フラックスを用いない半導体素子の接続端子
形成技術に関し、さらに、当該接続端子によるフリップ
チップ接合技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technique for forming connecting terminals of semiconductor elements without using flux, and further relates to a flip-chip bonding technique using the connecting terminals.
フリップチップの接続端子の一つに、半田（ｐｂ−８ｎ
）を用いて半球状のバンプ（突起電極）を形成したもの
がある。この場合の半田ポールの形成は、従来、一般に
ウニ八表面のパッジベージｌン膜に電極用窓をあけ、バ
リア金属を含む金属膜の層より電極パッドを形成し、パ
ッド上及びパッド周囲にはんだを堆積させた後フラック
スを塗布した状態で不活性雰囲気中で、バリア金属上の
半田を加熱溶融させて球欠体状の半田バンプな形成する
ことにより□行われていた。 ′丁なわち、
半田表面の酸化膜を取り去り新生表面を保護する目的で
、松ヤニ等のフラックスを塗布した状態で上記バンブの
形成を行っていた。Solder (pb-8n) to one of the connection terminals of the flip chip.
) to form hemispherical bumps (protruding electrodes). Conventionally, to form a solder pole in this case, an electrode window is generally opened in a pad base film on the surface of the sea urchin, an electrode pad is formed from a layer of a metal film containing a barrier metal, and solder is applied on and around the pad. This was done by heating and melting the solder on the barrier metal in an inert atmosphere with flux applied after deposition to form a spherical solder bump. 'Ding, that is,
In order to remove the oxide film on the solder surface and protect the new surface, the bumps were formed with a flux such as pine resin applied.
一方、フリップチップ方式により、当該半田バンブを有
するチップを基板にフェイスダウンボンディングにより
接合する場合にも、同様に基板側などにフラックスを塗
布しつつ、当該接合を行なっていた。On the other hand, when a chip having solder bumps is bonded to a substrate by face-down bonding using the flip-chip method, the bonding is similarly performed while applying flux to the substrate side.
なお、フリップチップについて述べた文献の例としては
、（株）工業調査会１９８０年１月１５日発行ｒＩＣ化
実装技術」ｐ８１があげられる。Incidentally, an example of a document describing flip-chips is "IC Mounting Technology" published by Industrial Research Association Co., Ltd., January 15, 1980, p.81.
しかるに、このようなフラックスの使用は、チップ表面
の汚染の原因となり半導体装置の信頼性を低下させるこ
とになる。すなわち、加熱されたフラックスは一部焼き
付きなどにより、残滓物として残り、これをイオン性汚
染に対して効果の大きい水などで洗浄しようとしても、
半田は水に弱いために水を使用できず、残滓物が原因で
半導体装置の信頼性を低下させることがある。However, use of such flux causes contamination of the chip surface and reduces the reliability of the semiconductor device. In other words, some of the heated flux may seize and remain as a residue, and even if you try to clean it with water, which is highly effective against ionic contamination,
Solder cannot be used with water because it is sensitive to water, and residue may reduce the reliability of semiconductor devices.
本発明の目的は、フラックスを用いないでも。The purpose of the present invention is to achieve a method without using flux.
前記接続端子を形成できる技術を提供することを目的と
する。It is an object of the present invention to provide a technique that can form the connection terminal.
本発明のほかの目的は、フラックスを用いないでも前記
のごとき接合を達成できる技術を提供することを目的と
する。Another object of the present invention is to provide a technique that allows the above-described bonding to be achieved without using flux.
本発明の前記ならびにそのほかの目的と新規な特徴は１
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明丁れば、下記のとおりである。A brief summary of typical inventions disclosed in this application is as follows.
本発明では、真空下水素プラズマにより還元状態となし
て、半田ボールの形成や当該半田ボールによる接合を行
なうようにした。In the present invention, the solder ball is formed and the bonding is performed using the solder ball by bringing it into a reduced state using hydrogen plasma under vacuum.
すなわち、真空下水素プラズマ還元により、半田表面の
酸化膜は次式で示すように還元除去されるので、フラッ
クスな使用する必要がなくなった。That is, by hydrogen plasma reduction under vacuum, the oxide film on the solder surface is reduced and removed as shown by the following formula, so there is no need to use a flux.
ＰｂＯ＋２Ｈ”−） Ｐｂ＋Ｈ，Ｏ・・・・・・・・・
・・・・・・■５ｎ０１＋４Ｈ−＋Ｓｎ＋２ＨｚＯ””
−・”・■丁なわち、酸化膜は水素プラズマにより分解
され、半田成分（Ｐｂ−８ｎ）を残して、あとは水とし
て除去されるので、半田ボールがフラックスなしで形成
でき、また、当該半田ボールによるフェイスダウンボン
ディングもフラックスなしで行なうことができる。PbO+2H"-) Pb+H,O・・・・・・・・・
・・・・・・■5n01+4H-+Sn+2HzO""
-・”・■In other words, the oxide film is decomposed by hydrogen plasma, leaving the solder component (Pb-8n) behind, and the rest is removed as water, so solder balls can be formed without flux, and the Face-down bonding with solder balls can also be performed without flux.
次に、本発明を適宜図面を参照しつつ説明する。 Next, the present invention will be explained with appropriate reference to the drawings.
第１図は本発明の一実施例を示ｊ原理図で、本発明を実
施するために新たに開発された当該装置の一例断面図を
併せて示しである。当該装置において、第１図では真空
チャンバ１の外部に配置されろ真空ポンプ、各種電源、
ガス源および制御装置はその図示が省略されている。FIG. 1 is a principle diagram showing an embodiment of the present invention, and also shows a sectional view of an example of the device newly developed to carry out the present invention. In this apparatus, a vacuum pump, various power supplies,
Gas sources and control devices are not shown.
本装置の真空チャンバ１内には水素プラズマ発生機構２
．赤外線ランプ３およびペレットを保持するヒータ４が
収納されている。Inside the vacuum chamber 1 of this device is a hydrogen plasma generation mechanism 2.
．． An infrared lamp 3 and a heater 4 for holding pellets are housed.
水素プラズマ発生ｍ構２は、真空チャンバ１０天面に吊
下されている。赤外線ランプ３は該プラズマ発生機構２
とヒータ４との間に、その支持機構が省略されているが
、支持されている。ヒータ４は真空チャンバ１の底面上
に立設されている。The hydrogen plasma generating structure 2 is suspended from the top surface of the vacuum chamber 10. The infrared lamp 3 is connected to the plasma generation mechanism 2.
Although the support mechanism is omitted, the heater 4 is supported between the heater 4 and the heater 4 . The heater 4 is erected on the bottom surface of the vacuum chamber 1.
ヒータ４の下部には、冷却機構５が取付けられて、いる
。A cooling mechanism 5 is attached to the lower part of the heater 4.
ここで、真空チャンバ１内を排気している高真空にする
ことにより、低酸素濃度雰囲気を得ることができる。次
いで、チャンバ１内を水素雰囲気として水素プラズマ発
生機構２により水素プラズマを発生させる。ヒータ４上
には、ペレット６が載置されている。ペレット６上の電
極７および蒸着などにより形成された半田膜８は、拡大
して描かれている。Here, by evacuating the vacuum chamber 1 to a high vacuum, a low oxygen concentration atmosphere can be obtained. Next, the chamber 1 is made into a hydrogen atmosphere, and the hydrogen plasma generation mechanism 2 generates hydrogen plasma. Pellets 6 are placed on the heater 4. The electrode 7 on the pellet 6 and the solder film 8 formed by vapor deposition or the like are shown enlarged.
ヒータ４および赤外線ランプ３あるいはそのいずれか１
により加熱されたペレット６上の半田膜８の表面自然酸
化膜は、水素プラズマにより還元される。表面酸化膜を
失い、かつ、その融点以上に加熱された半田ＢＸ８は、
その表面張力によりボール状となり半田ボール形成が達
成される。電極７を溶融半田から保腹するため、半田ボ
ール形成後直ちに冷却機構５により、ペレット６を冷却
する。冷却機構５は主に、冷媒の導管から成るものとし
て固定されていても、あるいは、冷却されたブロックを
ヒータ４に押しつけるものとしてもよい。Heater 4 and/or infrared lamp 3
The natural oxide film on the surface of the solder film 8 on the heated pellet 6 is reduced by the hydrogen plasma. Solder BX8, which has lost its surface oxide film and has been heated above its melting point,
The surface tension causes the solder to form a ball and form a solder ball. In order to protect the electrode 7 from molten solder, the pellet 6 is cooled by the cooling mechanism 5 immediately after the solder ball is formed. The cooling mechanism 5 may be fixed, mainly consisting of a refrigerant conduit, or it may press a cooled block against the heater 4.
以上により、フラックスを用いる事なしに、信頼度良く
半田ボールを形成することができる。上記において％真
空チャンバ１内にペレット６をセット後に、排気しこれ
によりチャンバ１内の雰囲気中の酸素濃度を低減させる
が、当該酸素濃度はチャンバ１の大きさなどにより異な
り一概にいえず、特に制限されないが１例えばチャンバ
内圧力を１０−４〜１０−”Ｔｏｒｒ程度にまで低下さ
せる。As described above, solder balls can be formed with high reliability without using flux. In the above, after the pellet 6 is set in the vacuum chamber 1, it is evacuated, thereby reducing the oxygen concentration in the atmosphere inside the chamber 1. However, the oxygen concentration varies depending on the size of the chamber 1, etc. For example, but not limited to, the pressure inside the chamber is lowered to about 10-4 to 10-'' Torr.
当該雰囲気調整後に水素プラズマを発生させ、下記の反
応を進ませる。After adjusting the atmosphere, hydrogen plasma is generated and the following reaction proceeds.
ＰｂＯ＋２Ｈ−＋Ｐｂ＋Ｈ，Ｏ・・・・・・・・・・・
・・・・■５ｎＯ１＋４Ｈ４Ｓｎ＋２Ｈ２０・・・・・
・・・・・・・・・・■（ただし、Ｈ＊は水素ラジカル
）
これにより、半田膜８の表面の自然酸化膜を除去できる
。上記反応は例えばペレット温度２００℃以上で行う。PbO+2H-+Pb+H,O・・・・・・・・・・・・
...■5nO1+4H4Sn+2H20...
. . . ■ (H* is a hydrogen radical) As a result, the natural oxide film on the surface of the solder film 8 can be removed. The above reaction is carried out, for example, at a pellet temperature of 200° C. or higher.
第４図に、当該半田ボール形成後のペレット６の要部断
面図を示す。FIG. 4 shows a sectional view of the main part of the pellet 6 after the solder ball is formed.
第４図にて、９は半田ボール、１０はデバイス。In Figure 4, 9 is a solder ball and 10 is a device.
１１は絶縁膜、１２はＡ７電極配朦、１３はデバイス表
面保鏝膜で、水素プラズマによる他は当該半田ボール９
の形成に際しては公知の方法を適用できる。11 is an insulating film, 12 is an A7 electrode arrangement, 13 is a device surface protection film, and the solder ball 9 is
A known method can be applied to the formation.
第４図にて、電極（パッド）７は、例えばその内側から
順次Ｃｒ層１４．Ｃｕ層１５およびＡｕ層１６よりなる
。In FIG. 4, the electrode (pad) 7 has, for example, a Cr layer 14 . It consists of a Cu layer 15 and an Au layer 16.
次に、本発明によるフリップチップ接続（フェイスダウ
ンボンディング）について、第２図および第３図を参照
しつつ説明する。Next, flip-chip connection (face-down bonding) according to the present invention will be explained with reference to FIGS. 2 and 3.
第２図は第１図と同様な装置をフリップチップ接続に適
用した例を示す原理図である。FIG. 2 is a principle diagram showing an example in which a device similar to that in FIG. 1 is applied to flip-chip connection.
真空チャンバ１内のヒータ４上には、電極７ａおよび半
田膜８ａを有するペレット６をフェイスダウンボンディ
ングで、電極８ｂおよび半田膜８ｂを有する配線基板１
７に仮接続したものを載置しである。A pellet 6 having an electrode 7a and a solder film 8a is placed on the heater 4 in the vacuum chamber 1 by face-down bonding, and a wiring board 1 having an electrode 8b and a solder film 8b is placed on the heater 4.
The one temporarily connected to 7 is mounted.
第１図に示すものと同様にして、真空チャンバ１内を排
気し水素プラズマを発生させ、水素プラズマによる半田
表面の酸化膜除去後加熱して、ペレット６と配線基板１
７の各々対向する電極７ａ。In the same manner as shown in FIG. 1, the inside of the vacuum chamber 1 is evacuated to generate hydrogen plasma, and after the oxide film on the solder surface is removed by the hydrogen plasma, the pellet 6 and the wiring board 1 are heated.
7, each facing electrode 7a.
７ｂ上の半田８ａおよび８ｂを溶融させ、冷却して配線
基板１７上にペレット６をマウントするとともに、半田
リフローを行なう。Solders 8a and 8b on 7b are melted and cooled to mount pellet 6 on wiring board 17, and solder reflow is performed.
第３図は、第２図の機構群に加えてペレット６を配線基
板１７にマウントするマウント機構１８を設けたもので
ある。マウント機構１８は、ペレット６をひろい上げ移
動させるアーム１８ａ、ペレット６および配線基板９の
位置を測定するカメラ１８ｂ、およびそれらのコントロ
ーラＮＯなどより成る。In FIG. 3, a mounting mechanism 18 for mounting the pellet 6 on the wiring board 17 is provided in addition to the mechanism group shown in FIG. The mounting mechanism 18 includes an arm 18a that picks up and moves the pellet 6, a camera 18b that measures the positions of the pellet 6 and the wiring board 9, and their controller NO.
このように、真空チャンバ１内にマウント機構１８を設
けることにより、第２図に示すが如くにペレット６と配
線基板１７の仮接続を行わずに、当該フリップチップ接
合を行うことができる。By providing the mounting mechanism 18 in the vacuum chamber 1 in this manner, flip-chip bonding can be performed without temporarily connecting the pellet 6 and the wiring board 17 as shown in FIG.
第５図に、本発明によるフラックス無しで配線基板１７
にペレット６をマルチにマウント、接合して成る構造な
有するマルチチップモジュールの一例断面図を示す。FIG. 5 shows a wiring board 17 without flux according to the present invention.
1 shows a cross-sectional view of an example of a multi-chip module having a structure in which multiple pellets 6 are mounted and bonded.
第５図にて、１９はコネクタ用ワイヤ、２０はリードフ
レーム、２１はフランジ、２２はキャップ、２３はペー
ス、２４は封止用接着剤、２５は封止用ガラス、２６は
接着剤％ ２７はフィンを示すＯ
半導体素子（チップ）６は、例えばシリコン単結晶基板
から成り、周知の技術によってこのチップ内には多数の
回路素子が形成され、１つの回路機能が与えられている
。回路素子の具体例は、例えばＭＯＳトランジスタから
成り、これらの回路素子によりて、例えば論理回路およ
びメモリの回路機能が形成されている。In FIG. 5, 19 is a connector wire, 20 is a lead frame, 21 is a flange, 22 is a cap, 23 is a paste, 24 is a sealing adhesive, 25 is a sealing glass, 26 is an adhesive% 27 indicates a fin. The semiconductor element (chip) 6 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip by well-known techniques to provide one circuit function. A specific example of the circuit element is, for example, a MOS transistor, and these circuit elements form, for example, a logic circuit and a memory circuit function.
配線基板、１７は、例えばＳｉＣ配線基板より成る。The wiring board 17 is made of, for example, a SiC wiring board.
コネクタ用ワイヤ１９は、例えばＡｕ線やＡＪ線より成
る。The connector wire 19 is made of, for example, an Au wire or an AJ wire.
リードフレーム２０は１例えばコバール１８合金により
構成される。The lead frame 20 is made of, for example, Kovar 18 alloy.
ベース２３は、例えばＳｉＣ基板により構成される。The base 23 is made of, for example, a SiC substrate.
本発明によれば、水素プラズマ還元により半田表面酸化
膜が除去でき、新生表面となし得るので、フラックス無
しで半田ボール９の形成や、ペレット６と配線基板１７
との半田ボールによる接合を行なうことができた。According to the present invention, the oxide film on the solder surface can be removed by hydrogen plasma reduction and a new surface can be created.
It was possible to make a connection using solder balls.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定されろ
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor.
なお、プラズマの発生方法についての各種方法について
は、 Ｂｒ１ａｎ Ｃｈａｐｍａｎ 、 ”Ｇｌｏｗ
ＤｉｓｃｈａｒｇｅＰｒｏｃｅｓｓｅｓ ’ 、 １９
８０ 、 ＪｏｈｎＷｉｌｅｙ ＆ ５ｏｎｓ 、 Ｊ
ｎｃ。For various methods of plasma generation, please refer to Br1an Chapman, “Glow
DischargeProcesses', 19
80, John Wiley & 5ons, J.
nc.
ｐ、１３９−１７２に、フリップ・チップ・ボンディン
グすなわちソルダーバンブによるポンディング技術につ
いては、Ｄ、 Ｊ、 Ｈａｍｉ Ｉｔｏｎ ＆ Ｗ、
Ｇ、 Ｈｏｗａｒｄ 。For flip chip bonding or solder bump bonding techniques, see D. J. Hami Iton & W., pp. 139-172.
G. Howard.
”Ｂａ５ｉｃ Ｊｎｔｅｇｒａｔｅｄ Ｃ１ｒｃｕｉｔ
Ｅｎｇｉｎｅｅｒｉｎｇ”。”Ba5ic Jintegrated C1rcuit
Engineering”.
１９７５、Ｍｅ Ｇｒａｗ−Ｈｉｌｌ ＊ Ｊｎｃ、
ｐ、 １０３−１０７ 。1975, Me Graw-Hill * Jnc,
p, 103-107.
Ｓ、 Ｍ、 Ｓｚｅ 、 ”ＶＬＳＩ Ｔｅｃｈｎｏｌ
ｏｇｙ’ 、 １９８３ 、ＭｃＧｒａｗ−Ｈｉｌｌ
Ｊｎｃ、 ｐ、 ５６４−５７０ に、フリップチップ
技術及びチップ−キャリア、配線基板への実装方式につ
いては、特開昭５９−８７８９３号。S., M. Sze, “VLSI Technology
ogy', 1983, McGraw-Hill
Jnc, p. 564-570, and Japanese Patent Application Laid-Open No. 59-87893 for flip-chip technology, chip-carrier, and mounting method on wiring board.
同６０−１５４６３２号、同６０−２０２９４６号。No. 60-154632, No. 60-202946.
同５４−７３５６４号、特願昭６１−２５１７２９号。No. 54-73564, Japanese Patent Application No. 61-251729.
同６０−２０８６６０号、同６１−１１９２１３号、同
６１−１７１５８８号、同６１−１９５４７９号等に記
載されているので、それらをもって本願明細書の記載に
かえる。更に５本願発明が主に適用されるメイン・フレ
ーム・コンピュータのｃｐｖｓの演算回路については、
多くの教科書に記載されているので、ここでは省略する
。Since it is described in No. 60-208660, No. 61-119213, No. 61-171588, No. 61-195479, etc., the description thereof is replaced with the description in the present specification. Furthermore, regarding the cpvs arithmetic circuit of the main frame computer to which the present invention is mainly applied,
Since it is described in many textbooks, it will be omitted here.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
本発明によれば、フラックス無しで、半田ボールの形成
やフリップチップ接合を行なうことができるので、フラ
ックスを使用する場合に必要なフラックスの洗浄を行う
必要力ｔなく又、フラックスを使用する事に起因するペ
レット表面の汚染、それに伴なう信頼性の低下がな（、
その作業上有利であり、かつ、信頼性を向上させること
ができた。According to the present invention, solder ball formation and flip-chip bonding can be performed without flux, so there is no need to clean the flux, which is necessary when using flux, and it is possible to use flux. There is no contamination of the pellet surface caused by this, and the resulting decrease in reliability.
This was advantageous in terms of work and improved reliability.
第１図は１本発明の実施例を示す原理図。
第２図は本発明の他の実施例を示す原理図、第３図は本
発明のさらに他の実施例を示す原理図。
第４図はペレットの要部断面図、
第５図はフリップチップ接合構造を有する半導体装置の
一例断面図である。
１・・・真空チャンバ、２・・・水素プラズマ発生機構
。
３・・・赤外線ランプ、４・・・ヒータ、５・・・冷却
機構、６・・・ペレット、７・・・電極、８・・・半田
膜、９・・・半田ボール、１０・・・デバイス、１１・
・・絶縁膜％ １２・・・Ａｌ電極配線、１３・・・デ
バイス表面保護膜、１４・・・Ｃｒ層、１５・・・Ｃｕ
層、１６・・・Ａｕ層、１７・・・配線基板、１８・・
・マウント機構、１９・・・コネクタ用ワイヤ、２０・
・・リードフレーム、２１・・・フランジ、２２・・・
キャップ、２３・・・ペース、２４・・・対土用接着剤
、２５・・・封止用ガラス、２６・・・接着剤。
２７・・・フィン。
代理人 弁理士 小 川 勝 男
第 ４ 図
【ぜ−（じ乏イ〔３言１
第 ５ 図
、７ｓＬｎぴ宗妥頌FIG. 1 is a principle diagram showing an embodiment of the present invention. FIG. 2 is a principle diagram showing another embodiment of the present invention, and FIG. 3 is a principle diagram showing still another embodiment of the present invention. FIG. 4 is a sectional view of the main part of the pellet, and FIG. 5 is a sectional view of an example of a semiconductor device having a flip-chip bonding structure. 1...Vacuum chamber, 2...Hydrogen plasma generation mechanism. 3... Infrared lamp, 4... Heater, 5... Cooling mechanism, 6... Pellet, 7... Electrode, 8... Solder film, 9... Solder ball, 10... device, 11.
...Insulating film% 12...Al electrode wiring, 13...Device surface protective film, 14...Cr layer, 15...Cu
layer, 16...Au layer, 17...wiring board, 18...
・Mount mechanism, 19...Connector wire, 20・
...Lead frame, 21...Flange, 22...
Cap, 23... Pace, 24... Soil adhesive, 25... Sealing glass, 26... Adhesive. 27...fin. Agent Patent Attorney Katsuo Ogawa Figure 4
Claims (1)
の半田ボールよりなる接続端子を形成するに際し、真空
下水素プラズマ還元雰囲気中で前記半田表面の酸化膜を
還元除去しつつ行うことを特徴とする半導体素子接続端
子形成方法。 ２、接続端子の形成が、その内部に水素プラズマ発生機
構と半導体素子加熱機構と冷却機構とを備設した真空槽
内にて行われる、特許請求の範囲第１項記載の方法。[Claims] 1. When heating and welding solder to the electrode portion of a semiconductor element to form a connection terminal made of a hemispherical solder ball, the oxide film on the surface of the solder is reduced in a hydrogen plasma reducing atmosphere under vacuum. A method for forming a semiconductor element connection terminal, characterized in that the process is performed while removing the terminal. 2. The method according to claim 1, wherein the connection terminal is formed in a vacuum chamber equipped with a hydrogen plasma generation mechanism, a semiconductor element heating mechanism, and a cooling mechanism.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62128190A JPS63293952A (en) | 1987-05-27 | 1987-05-27 | Forming method for semiconductor element connection terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62128190A JPS63293952A (en) | 1987-05-27 | 1987-05-27 | Forming method for semiconductor element connection terminal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63293952A true JPS63293952A (en) | 1988-11-30 |
Family
ID=14978673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62128190A Pending JPS63293952A (en) | 1987-05-27 | 1987-05-27 | Forming method for semiconductor element connection terminal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63293952A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184697A (en) * | 1989-12-13 | 1991-08-12 | Matsushita Electric Ind Co Ltd | Production of cream solder |
| US5223691A (en) * | 1991-06-03 | 1993-06-29 | Motorola, Inc. | Plasma based soldering method requiring no additional heat sources or flux |
| US5345056A (en) * | 1991-12-12 | 1994-09-06 | Motorola, Inc. | Plasma based soldering by indirect heating |
| WO2000017923A1 (en) * | 1998-09-17 | 2000-03-30 | Kabushiki Kaisha Tamura Seisakusho | Bump forming method, soldering preprocessing method, soldering method, soldering preprocessing apparatus and soldering apparatus |
| JP2001058259A (en) * | 1999-06-18 | 2001-03-06 | Shinko Seiki Co Ltd | Soldering method and soldering apparatus |
| KR100411144B1 (en) * | 2002-02-26 | 2003-12-24 | 서울대학교 공과대학 교육연구재단 | Reflow Method of fluxless solder bump using Ar-H2 Plasma |
| JP2004079771A (en) * | 2002-08-19 | 2004-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Solder bump forming method |
| JP2012009597A (en) * | 2010-06-24 | 2012-01-12 | Elpida Memory Inc | Manufacturing method for semiconductor device and manufacturing apparatus for semiconductor device |
| JP2012104817A (en) * | 2010-11-05 | 2012-05-31 | Raytheon Co | Method of reducing formation of oxide on solder |
| US8283783B2 (en) | 2007-11-20 | 2012-10-09 | Toyota Jidosha Kabushiki Kaisha | Solder material, method for manufacturing the same, joined body, method for manufacturing the same, power semiconductor module, and method for manufacturing the same |
| JP2013247361A (en) * | 2012-05-25 | 2013-12-09 | Psk Inc | Substrate joining method and substrate reflow treatment apparatus |
| JP2015179796A (en) * | 2014-03-18 | 2015-10-08 | 株式会社坂本電機製作所 | Reflow method and reflow device used for reflow method |
-
1987
- 1987-05-27 JP JP62128190A patent/JPS63293952A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184697A (en) * | 1989-12-13 | 1991-08-12 | Matsushita Electric Ind Co Ltd | Production of cream solder |
| US5223691A (en) * | 1991-06-03 | 1993-06-29 | Motorola, Inc. | Plasma based soldering method requiring no additional heat sources or flux |
| US5345056A (en) * | 1991-12-12 | 1994-09-06 | Motorola, Inc. | Plasma based soldering by indirect heating |
| WO2000017923A1 (en) * | 1998-09-17 | 2000-03-30 | Kabushiki Kaisha Tamura Seisakusho | Bump forming method, soldering preprocessing method, soldering method, soldering preprocessing apparatus and soldering apparatus |
| KR100473432B1 (en) * | 1998-09-17 | 2005-03-08 | 가부시키가이샤 다무라 세이사쿠쇼 | Bump forming method, soldering preprocessing method, soldering method, soldering preprocessing apparatus and soldering apparatus |
| JP2001058259A (en) * | 1999-06-18 | 2001-03-06 | Shinko Seiki Co Ltd | Soldering method and soldering apparatus |
| KR100411144B1 (en) * | 2002-02-26 | 2003-12-24 | 서울대학교 공과대학 교육연구재단 | Reflow Method of fluxless solder bump using Ar-H2 Plasma |
| JP2004079771A (en) * | 2002-08-19 | 2004-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Solder bump forming method |
| US8283783B2 (en) | 2007-11-20 | 2012-10-09 | Toyota Jidosha Kabushiki Kaisha | Solder material, method for manufacturing the same, joined body, method for manufacturing the same, power semiconductor module, and method for manufacturing the same |
| JP2012009597A (en) * | 2010-06-24 | 2012-01-12 | Elpida Memory Inc | Manufacturing method for semiconductor device and manufacturing apparatus for semiconductor device |
| JP2012104817A (en) * | 2010-11-05 | 2012-05-31 | Raytheon Co | Method of reducing formation of oxide on solder |
| US8844793B2 (en) | 2010-11-05 | 2014-09-30 | Raytheon Company | Reducing formation of oxide on solder |
| US9132496B2 (en) | 2010-11-05 | 2015-09-15 | Raytheon Company | Reducing formation of oxide on solder |
| DE102011116233B4 (en) | 2010-11-05 | 2022-12-08 | Raytheon Company | METHOD AND APPARATUS FOR REDUCING THE FORMATION OF OXIDES ON SOLDER |
| JP2013247361A (en) * | 2012-05-25 | 2013-12-09 | Psk Inc | Substrate joining method and substrate reflow treatment apparatus |
| JP2015179796A (en) * | 2014-03-18 | 2015-10-08 | 株式会社坂本電機製作所 | Reflow method and reflow device used for reflow method |
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