JPS63299543A - Synchronizing clock generating circuit - Google Patents

Abstract

PURPOSE:To extremely decrease malfunctions due to lock-in actions by using a synchronizing means which secures the synchronism between a synchronizing clock and the clock phase extracted and divided from other data. CONSTITUTION:A synchronizing means 11 is provided to secure the synchronism between each clock phase and the phase of a phase synchronizing clock PSC outputted from a phase locked circuit 9 in case the clocks extracted from each data and divided are not fetched by the circuit 9 yet and right after a hit is produced and recovered although said clocks are fetched by the circuit 9. Thus the time needed for the second pull-in action of synchronization is shortened and the malfunctions like reception errors, etc., are decreased since the phase synchronism is already secured in case the clock supplied to the circuit 9 has a hit and is recovered or said clock is switched to the clocks which are extracted out of other data and divided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous clock generation circuit that generates a synchronous clock when a plurality of data having a predetermined data transmission rate and synchronized with each other in a network are taken in.

[Conventional technology]

When receiving or receiving multiple pieces of data that have the same data transmission rate and are network synchronized with each other, or multiple pieces of data that have different data transmission rates and are network synchronized with each other, the synchronous clock generation circuit synchronizes with the network. It is necessary to generate a clock and process the above data using this clock.

FIG. 4 is a block diagram of this type of synchronous clock generation circuit recently proposed by the present inventors. IB is data B with a transmission rate of 6.312Mb/S
is sent from B channel, 2A is sent from A channel IA
A clock extraction circuit that extracts a clock from the data of
2B is a B clock extraction circuit that extracts the clock from B channel IB data, 3A is an A clock extraction circuit 2A
The A frequency division counter divides the 1,544 MHz clock extracted by the A frequency division counter to create 8 kHz frequency CLKA, and 3B is the 6 clock extracted by the B clock extraction circuit 2B.
, 312MHz, and a B frequency division counter that divides the lock to produce CLKB of a frequency of 8KHz. 4A and 4B are any one of CLKA and CLKB output from the A frequency division counter 3A and the B frequency division counter 3B, respectively. A gate circuit and B gate circuit for selecting two clocks, SL and S2 are A gate circuit 4A and B gate circuit 4B
5 is a voltage controlled oscillator whose oscillation frequency can be controlled by voltage; 6 is a gate opening/closing control signal that controls opening and closing of the gate;
7 is a 1/N frequency division counter that divides the clock output from the voltage controlled oscillator 5 to generate an 8KHz clock;
8 is a phase comparator that compares the phase of the 8KHz clock output from the 1/N frequency division counter 6 with either CLKA or CLKB, and 8 is a noise output from the signal corresponding to the phase difference output from the phase comparator 7. This is a loop filter that removes unnecessary signals.

Here, phase comparator 7. The loop filter 8 and the voltage controlled oscillator 5.1/N frequency dividing counter 6 collectively constitute a phase locked circuit 9.

Next, the operation will be explained.

Based on the data sent from the A channel IA and the B channel IB, the A clock extraction circuit 2A and the B clock extraction circuit 2B extract a 1.544 MHz clock and a 6,312 MHz clock, respectively, and output them to the A frequency division counter 3A. and B frequency division counter 3B are each 1.544MHz
and divides the 6,312 MHz clock to create CLA and CLB with a frequency of 8 KHz.

At this time, for example, the gate opening/closing control signal S1 that controls the opening and closing of the gate of the A gate circuit 4A outputs an open signal, and the gate opening/closing control signal S2 that controls the opening and closing of the gate of the B gate circuit 4B outputs a closing signal. Then, 8K extracted by the A clock extraction circuit 2A and divided by the A frequency division counter 3A
CLKA of Hz passes through the A gate circuit 4A and is input to the phase comparator.

On the other hand, the voltage controlled oscillator 5 outputs 12.352M
The frequency of Hz is reduced to 1/77 by the 1/N frequency dividing counter 6.
The frequency is divided into 2 and the phase comparator 7 is used as an 8KHz clock.
has been entered.

Here, the phase comparator 7 compares the phase of the 8KHz CLKA output from the A gate circuit 4A with the phase of the 8KHz clock output from the 1/N frequency division counter 6, and generates a control signal according to the phase difference. It is outputting.

Therefore, the voltage controlled oscillator 5 controls the oscillation frequency according to the control signal output from the phase comparator 7, and outputs a synchronized clock having a frequency of 12,352 MHz.

For example, if a momentary interruption occurs in the data on the A channel IA, the phase of CLKA changes after the momentary interruption, so resynchronization is performed to match the phase after the change.

Also, when synchronizing the data clock on the A channel IA with the data clock on the B channel IB, that is, the A gate circuit 4A is opened and closed.

When changing the B gate circuit 4B from closed to open, CLKA
Since there is a phase shift between CLKB and CLKB, resynchronization will be performed.

Figures 5 and 6 are diagrams showing the phase shift when data on A channel IA is momentarily interrupted, and the phase shift when synchronization is transferred from A channel IA to data on B channel IB, respectively. As shown in the figure, the maximum phase shift is A period.

As shown in Figure 5, a momentary interruption occurs in the A channel IA,
When the same channel IA is restored, there will be a phase difference F1 shift in the restored clock, and this shift will be up to 2 cycles (125M
The length is S/2).

Furthermore, as shown in Fig. 6, when the synchronization target is shifted to the data on the B channel IB after a momentary interruption, the phase difference F between the clock of the B channel IB that is output for the first time after the momentary interruption is
A deviation of 2 occurs, and this deviation has a maximum length of 〃cycle.

That is, the time of A period of 8KHz (% x 125μ = 6
2.5 Cμs)) is the maximum time difference required for the pull-in.

[Problem that the invention seeks to solve]

Since the above-mentioned synchronous clock generation circuit is configured as explained above, the pull-in time becomes extremely long, which causes problems such as data reception errors occurring during the unstable pull-in time. was.

This invention was made to solve the above problems, and aims to shorten the time required for synchronization pull-in, and as a result, reduce malfunctions such as reception errors as much as possible.

[Means for solving problems]

Therefore, in this invention, when the clocks extracted from each data and frequency-divided are not taken into the phase-locked circuit, and when the clocks are taken into the phase-locked circuit, but immediately after a momentary interruption occurs and the clock is restored, the phase of each clock is The present invention is characterized in that a synchronizing means is provided for synchronizing the phases of the phase synchronized clock psc outputted by the phase synchronized circuit and the phase synchronized clock psc.

[Effect]

The synchronizing means according to the present invention performs synchronization on the frequency-divided clock input to the phase-locked circuit immediately after the frequency-divided clock recovers from a momentary interruption, and on the frequency-divided clock that is not input to the phase-locked circuit. Match the phase with the output clock.

As a result, when the clock input to the phase-locked circuit recovers from a momentary interruption or when switching to a clock extracted from other data and frequency-divided, the phase is synchronized, so the time required to re-synchronize is shortened. .

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of a synchronous clock generation circuit showing one embodiment of the present invention. In the figure, IOA.

10B changes the frequency division ratio of the A frequency division counter 3A and the B frequency division counter 3B, and changes the phase of the 8KHz CLKA output from the A frequency division counter 3A and the 8KHz CLKB output from the B frequency division counter 3B. The A load control circuit and the B load control circuit synchronize with the phase of the A and B load control circuits, and these two load control circuits constitute the synchronizing means 11.

Note that the same components as those explained in FIG. 4 are given the same numbers and their explanations are omitted.

Next, the operation will be explained.

Now, the gate opening/closing control signal S1 that controls opening and closing of the gate of the A gate circuit 4A outputs an open signal, and the gate opening/closing control signal S1 of the A gate circuit 4A outputs an open signal, and
The gate opening/closing control signal S2 that controls the opening and closing of the gate is outputting a close signal, and the CL of 8 kHz is extracted from the data on the A channel and divided by the A frequency division counter 3A.
Assume that KA passes through the A gate circuit 4A and is input to the phase comparator 7. At this time, the B load control circuit 10B controls the phase of CLKB by applying a load to the B frequency dividing counter 3B in accordance with the phase of the 8 KHz clock output from the lZN frequency dividing counter 6.

On the other hand, the A load control circuit 10A does not perform any operation because the clock output from the A frequency division counter 3A is input to the phase comparator 7.

For example, if the target of synchronization is shifted from the data clock on A channel IA to the data clock on B channel IB, the time required for resynchronization at this time will be the maximum as shown in Figure 2. The phase difference is ±1 clock with respect to the extracted clock, so 1 clock = 1/6
, 312MHz=158nS, which is an extremely short time. Similarly, when a momentary interruption occurs on the A channel, the A frequency division counter 3A is activated at least once when the momentary interruption occurs.
The synchronous clock in the phase m-period circuit 9 is loaded to the phase m-period circuit 9. The maximum phase difference required for phase synchronization at this time is 1 clock = 1/1,544 MHz = 648 nS.

Although the above embodiment has been specifically explained by applying numerical values to frequencies, the present invention applies regardless of the frequency and even if the transmission speeds of data sent from multiple channels are different or the same. It goes without saying that the invention can be applied.

〔Effect of the invention〕

As explained above, the present invention is provided with a synchronization means for synchronizing the clock phase extracted and frequency-divided from other data with the synchronization clock generated by the synchronization clock generation circuit. The pull-in time during pull-in operation that occurs when an instantaneous power outage occurs in two frequencies or when changing one clock input to the synchronous clock generation circuit to another clock is greatly reduced.
This has the effect of significantly reducing malfunctions associated with retraction.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a synchronous clock generation circuit showing an embodiment of the present invention, FIGS. 2 and 3 are block diagrams of the synchronous clock generation circuit shown in FIG. 1, and FIGS. This is a time chart for purposes of illustration. 2A, 2B...Clock extraction circuit, 3A, 3B
...Frequency division counter, 5...Voltage controlled oscillator, 6...1/N frequency division counter, 7...
...Phase comparator, 8...Loop filter, 9.
...Phase synchronization circuit, 11...Synchronization means. Agent Daikun Masu 111 (Two Idiots) Procedural Amendment (Horiki Showa Year Month Day 1, Case Indication Patent Application No. 133635-1988-4)
'2. Name of the invention: Synchronous clock generation circuit 3. Person making the amendment: Inside Mitsubishi Electric Corporation. 5. Date of amendment order: August 25, 1985. 6. Brief description of the drawing to be amended. 7. Details of the amendment (1) In the 10th line of page 11 of the specification, the phrase "Figure 3 is" is amended to read "Figure 4 is". (2) On page 11, line 11 of the same book, the statement ``Figures 4 and 5 are in Figure 3'' has been corrected to ``Figures 5 and 6 are in Figure 4''. Written amendment to the above procedures (self-effective)

Claims (1)

[Claims] Each clock extracted from a plurality of pieces of data having a predetermined data transmission rate and network synchronized with each other is divided by a frequency dividing circuit, and the same frequency is output from each frequency dividing circuit, and any one of the clocks is frequency-divided. A synchronous clock generation circuit that selects a circuit, inputs the output clock of the frequency dividing circuit to a phase-locked circuit, and generates a phase-locked clock from this phase-locked circuit, wherein the phase-locked circuit generates a phase-synchronized clock. 1. A synchronous clock generation circuit comprising: synchronization means for synchronizing the phase of a clock output from another unselected frequency dividing circuit with a phase synchronous clock.