JPS63299298A - Multilayered printed board - Google Patents
Multilayered printed boardInfo
- Publication number
- JPS63299298A JPS63299298A JP13387987A JP13387987A JPS63299298A JP S63299298 A JPS63299298 A JP S63299298A JP 13387987 A JP13387987 A JP 13387987A JP 13387987 A JP13387987 A JP 13387987A JP S63299298 A JPS63299298 A JP S63299298A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ground
- wiring
- power
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011810 insulating material Substances 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 abstract description 6
- 230000008878 coupling Effects 0.000 abstract description 3
- 238000010168 coupling process Methods 0.000 abstract description 3
- 238000005859 coupling reaction Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract 3
- 238000000034 method Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、多層プリント基板に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a multilayer printed circuit board.
多層プリント基板は、より高い配線密度を実現するため
に、何層もの配線層を重ね合わせた基板であり、1子機
器の小型化には必要不可欠な要素である。A multilayer printed circuit board is a board in which many wiring layers are stacked to achieve higher wiring density, and is an essential element for downsizing single-child devices.
しかし、配線層を重ね合わせることにより、配線層間の
静電容量的結合が大きくなって、基板内における各種信
号の相互干渉が起こる恐れが生じてくる。However, by overlapping the wiring layers, capacitance coupling between the wiring layers increases, and there is a possibility that mutual interference of various signals within the substrate may occur.
そこで、従来の多層プリント基板は、図2に示すように
全ての配線層21間の部材を低誘電率の絶縁材料22と
して、配線層間の静電容量を小さく抑えていた。Therefore, in the conventional multilayer printed circuit board, as shown in FIG. 2, the members between all the wiring layers 21 are made of a low dielectric constant insulating material 22 to keep the capacitance between the wiring layers small.
一般に、電源電圧変動を防止するためには、電源とグラ
ンドとの間に電荷蓄積手段を付加することが多い。Generally, in order to prevent power supply voltage fluctuations, charge storage means is often added between the power supply and ground.
しかし、従来の多層プリント基板では、liE源用起用
配線層ランド用配線層を隣り合わせても、電源配測とグ
ランド配線との間の静電容量が小さく、前記電荷蓄積手
段としては不十分なため、コンデンサ(バイパスコンデ
ンサ)を実装しなくてはならない、これは、実装面積的
に不利であり高密度実装が要求される現在、非常に問題
となる点である。However, in conventional multilayer printed circuit boards, even if the LiE source wiring layer and the land wiring layer are placed next to each other, the capacitance between the power supply wiring and the ground wiring is small, and the capacitance is insufficient as the charge storage means. , it is necessary to mount a capacitor (bypass capacitor), which is disadvantageous in terms of mounting area and is a very problematic point in today's world where high-density mounting is required.
そこで本発明は、このような問題点を解決するもので、
その目的とするところは、電源配線とグランド配線の間
の静電容量が大きく、電源電圧変動を防止するためのコ
ンデンサを実装する必要がない多層プリント基板を提供
するところにある。Therefore, the present invention aims to solve these problems.
The purpose is to provide a multilayer printed circuit board that has a large capacitance between the power supply wiring and the ground wiring, and does not require mounting a capacitor to prevent fluctuations in the power supply voltage.
本発明の多層プリント基板は、少なくとも3層以上で構
成され、隣り合う一対の配線層のうち、一方を主に電源
配線用、他方を主にグランド用とし、前記配線層間の部
材のみを高誘電率の絶縁材料とした事を特徴とする。The multilayer printed circuit board of the present invention is composed of at least three layers, one of which is used mainly for power supply wiring and the other is mainly used for grounding among a pair of adjacent wiring layers, and only the members between the wiring layers have high dielectric properties. It is characterized by being made of a high-density insulating material.
第1図は、本発明の実施例における4層プリント基板で
ありて、第1層1.第4層4を主に信号線配線用、第2
層2を主に電源用、第6層3を主にグランド用としてい
る。FIG. 1 shows a four-layer printed circuit board according to an embodiment of the present invention, in which the first layer 1. The fourth layer 4 is mainly used for signal wiring, the second
Layer 2 is mainly used for power supply, and sixth layer 3 is mainly used for ground.
ここで、第1層と第2層の間、及び第3層と第4層の間
の部材は、従来のプリント基板に用いられるような低誘
電率の絶縁材料5.第2層と第3層の間の部材は高誘電
率の絶縁材料6でそれぞれ構成されている。Here, the members between the first layer and the second layer and between the third layer and the fourth layer are made of a low dielectric constant insulating material 5. The members between the second layer and the third layer are each made of an insulating material 6 with a high dielectric constant.
これにより、第1層にある信号線と第2層にある電源配
線、及び第4層にある信号線と第3層にあるグランド配
線との間の静電容量的結合は従来通りに小さく抑えたま
ま、第2層にある電源配線と第3層にあるグランド配線
との間の静電容量を大きくすることが出来る。As a result, the capacitance coupling between the signal line on the first layer and the power supply line on the second layer, and between the signal line on the fourth layer and the ground line on the third layer is kept small as before. At the same time, the capacitance between the power supply wiring in the second layer and the ground wiring in the third layer can be increased.
以上述べたように、本発明によれば電源配線とグランド
配線の静電容量が大きく、基板自身にバイパスコンデン
サの役割を持たせることが出来る、これにより、従来の
ようにバイパスコンデンサを実装する必要がないため、
より一層の高密度密度実装、基板の小形化が可能となる
という効果を有する。As described above, according to the present invention, the capacitance of the power supply wiring and the ground wiring is large, and the board itself can serve as a bypass capacitor.This makes it unnecessary to mount a bypass capacitor as in the past. Because there is no
This has the effect of enabling even higher density packaging and miniaturization of the board.
第1図は本発明の多層プリント基板の一実施例を示す主
要断面図。
第2図は従来の多層プリント基板(4層)の主要断面図
。
1・・・・・・・・・第1層
2・・・・・・・・・第2層
3・・・・・・・・・第3層
4・・・・・・・・・第4層
5・・・・・・・・・低誘電率の絶縁材料6・・・・・
・・・・高誘電率の絶縁材料以上
出願人 セイコーエプソン株式会社
代理人 弁理士最上、、”*<他1名)グ′ 〆FIG. 1 is a main sectional view showing an embodiment of the multilayer printed circuit board of the present invention. FIG. 2 is a main cross-sectional view of a conventional multilayer printed circuit board (four layers). 1......First layer 2......Second layer 3...Third layer 4......Third layer 4 layers 5...Low dielectric constant insulating material 6...
・・・High permittivity insulating materials and above Applicant Seiko Epson Co., Ltd. Representative Patent Attorney Mogami, ``*<1 other person) Gu' 〆
Claims (1)
いて、隣り合う一対の配線層のうち、一方を主に電源用
、他方を主にグランド用とし、前記配線層間の部材のみ
を高誘電率の絶縁材料とした事を特徴とする多層プリン
ト基板。In a multilayer printed circuit board consisting of at least three or more layers, one of a pair of adjacent wiring layers is mainly used for power supply and the other is mainly used for grounding, and only the members between the wiring layers are made of high dielectric constant insulating material. A multilayer printed circuit board characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13387987A JPS63299298A (en) | 1987-05-29 | 1987-05-29 | Multilayered printed board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13387987A JPS63299298A (en) | 1987-05-29 | 1987-05-29 | Multilayered printed board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63299298A true JPS63299298A (en) | 1988-12-06 |
Family
ID=15115215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13387987A Pending JPS63299298A (en) | 1987-05-29 | 1987-05-29 | Multilayered printed board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63299298A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03150895A (en) * | 1989-11-08 | 1991-06-27 | Hitachi Ltd | Multilayer circuit board and manufacture thereof |
JPH05167265A (en) * | 1991-12-11 | 1993-07-02 | Oki Electric Ind Co Ltd | High speed signal printed wiring board |
US10984857B2 (en) | 2018-08-16 | 2021-04-20 | PsiQuantum Corp. | Superconductive memory cells and devices |
-
1987
- 1987-05-29 JP JP13387987A patent/JPS63299298A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03150895A (en) * | 1989-11-08 | 1991-06-27 | Hitachi Ltd | Multilayer circuit board and manufacture thereof |
JPH05167265A (en) * | 1991-12-11 | 1993-07-02 | Oki Electric Ind Co Ltd | High speed signal printed wiring board |
US10984857B2 (en) | 2018-08-16 | 2021-04-20 | PsiQuantum Corp. | Superconductive memory cells and devices |
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