JPS63279666A - Picture area discriminating device - Google Patents

Abstract

PURPOSE:To automatically detect both a recorded dot and a non-recorded dot by a high precision by changing the kinds of a detection pattern for detecting the recorded dot and the detection pattern for detecting the non-recorded dot, and using respectively the most suitable pattern for detecting the respective dot detection. CONSTITUTION:A signal mij outputted from an XY delay circuit 150 is impressed to the gate circuits 161, 162 and 164 of a black dot detection circuit 160. Then, the detection pattern, shown in a figure (a), is used for detecting a black dot. When one of the outputs of the gate circuits 161, 162, at least, is '1' and in addition, the signal of a central picture element m44 is '1', the output (n) of the black dot detection circuit 160 comes to be '1' and the black dot is detected. Besides, the detection pattern, shown in the figure (b), is used for detecting a white dot. When one of the outputs of the gate circuits 221 and 222, at least, is '1', and in addition, the signal of the central picture element c33 is '0' the output (p) of the white dot detection circuit 220 comes to be '1', and the white dot is detected.

Description

[Detailed description of the invention]

[Field of the Invention] The present invention relates to an image area identification device that automatically identifies whether each area of an input image has been subjected to halftone processing, and is used, for example, in a digital copying machine. [Prior Art] For example, in a digital copying apparatus, a C0D (charge coupled device) image sensor or the like is used to read a document image in minute areas, that is, pixel by pixel, and analog electrical signals obtained as outputs of the image sensor are read. After performing A/D (analog/digital) conversion on the resulting digital signal and performing various processing on the resulting digital signal, the signal is supplied to a recording device to obtain a copy image. By the way, in the printing apparatus used in this type of apparatus, it is difficult to change the density level for each printing pixel, so it is common to perform binary printing of printing/non-printing. However, since a document may also include halftone images such as photographs, it is necessary to reproduce halftone images. As methods for expressing halftones using a recording device that performs binary recording, methods such as the dither method, density pattern method, and submatrix method have been proposed, and if these methods are used, it is possible to reproduce halftone images. can. However, when performing halftone processing, a relatively favorable copy image can be obtained when the original image density changes gradually, such as in a photograph, but when the original image density changes binaryly, such as with text, it is difficult to obtain a copy image. In this case, the outline of the copy image becomes blurred, making it difficult to read characters, and dirt on the background of the original appears on the copy image, resulting in a significant deterioration in copy quality. For original images such as text, without performing halftone processing,
Simple binary processing yields a good copy. Therefore, if a switch is provided to specify whether or not halftone processing is to be performed, the
A preferred copy mode can be selected. However, there are many cases in which a single document, such as a pamphlet, contains both a half-tone image such as a photograph and a binary image such as text. In such a case, if the binary mode is selected, the quality of the photo will be degraded, and if the intermediate mode is selected, the quality of the text will be degraded. By the way, there is one more thing about this type of digital copying device.
There are two disadvantages. In other words, when reading an image in small pixel units using a line sensor or the like, if there is periodicity in density changes on the document, interference between the period (pitch) and the array pitch (sampling period) of the image reading sensor causes Moiré may occur on recorded images.6 For example, when halftone dot printing is performed on a document, the density changes on the image have periodicity, so the period of this density change and the sampling period of the reading sensor Moiré occurs due to interference with the image. For example, the resolution of one image reading sensor is 16 pixels - * / m
In the case of m, dot printing with a density close to that resolution, that is, 133 lines (approximately 10.5 pixels/mm) ~ 2
When the density is in the range of 00 lines (approximately 16 pixels/mm), moiré tends to occur in the read signal. Of course, moire also occurs at other densities, but the occurrence is particularly noticeable at the above density. , the resulting signal fluctuation range is large. Halftone printing itself is a type of pseudo-halftone expression. The density change in pixel units is a binary value of 110 (recording/non-recording). In halftone printing, the average density of the entire pixel set is changed in multiple steps by changing the pitch of the halftone dots and the size of the halftone dots, thereby expressing halftone density. Therefore, if the problem of moiré is not considered, when copying a halftone dot printed original image, the halftone dot image is reproduced in the recorded image by binary processing the signal. A preferred copy can be made. However, in reality, as described above, moiré occurs on a document image printed with halftone dots at a specific density, resulting in a significant deterioration in copy quality. On the other hand, when converting an image reading signal into a binary signal through halftone processing, the processing process averages the density of multiple pixels, changes the threshold level, etc., resulting in moiré in the copied image. will not occur or the impact will be small. In this case, the density of the copied image is represented by halftone dots, but the halftone dots on the copy are not direct reproductions of the halftone dots on the original, but are generated by halftone processing unique to copying machines. It is a point. Therefore, if the original is a halftone-printed image or an image copied with halftone processing by a digital copying machine, it is a binary recording in pixel units, but it is better to select a copy mode that performs halftone processing. is preferred. [Object of the Invention] The present invention automatically determines whether each area on a document is a halftone image or a binary image in order to perform preferable processing according to the type of image. The purpose is to accurately and automatically identify whether or not the [Structure of the Invention] In order to achieve the above object, in the present invention, recorded dots and non-recorded dots are detected by comparing a two-dimensional array pattern of input image information with a predetermined pattern, and the detection result is Based on this, it is determined whether the input image information is a halftone dot pattern or not. In the halftone-processed image, recorded dots (for example, black pixels 1i4) and non-recorded dots (for example, white pixels) are alternately and repeatedly arranged at predetermined pitches and intervals. Therefore, the recording pixel existing at a certain position and the non-recording pixels existing around it are in a predetermined arrangement pattern, or the non-recording pixel existing at a certain position and the recording pixel existing around it are in a predetermined arrangement pattern. If a pattern appears repeatedly, it can be assumed that the image has been subjected to halftone dot processing. In other words, by sequentially moving the pixel of interest and comparing the image information of a two-dimensional area consisting of it and its surrounding pixels for each pixel of interest with a predetermined recorded dot detection pattern and non-recorded dot detection pattern. , it is possible to identify whether the input image is a halftone dot pattern or not. However, when an image subjected to halftone dot processing is actually read with an image scanner, the image pattern of the read signal changes greatly depending on the density of one image, which often causes errors in halftone dot identification. In dot printing, the density is expressed by the size of the area of the halftone recording dots within a predetermined small area, so when the image density changes, the shape of the halftone dots changes significantly. In particular, when the halftone dot density is around 50%, recorded dots (for example, black pixels) or non-recorded dots (for example, self-portrait a>) constituting the halftone dots may be connected to each other and become continuous. In such cases, it is often impossible to detect either black dots or white dots.If you adjust the threshold level when binarizing image information into recorded pixel level and non-recorded pixel level, the halftone density is 5
Identification errors in the case of 0% can be reduced. However, in that case, identification errors increase when the halftone density is higher or lower than 50%. Therefore, in the present invention, at least two types of threshold values are set, and a circuit for detecting recorded dots and a circuit for detecting non-recorded dots detect image information that has been binarized using different threshold values. The dot pattern is identified based on both the recorded dot detection results and the non-recorded dot detection results. In the case of a halftone image, the signals read by the image scanner are generally as shown in FIG. Looking at this, it can be seen that the height of the peaks, the depth of the valleys, and the duty of the signal change depending on the concentration. Now, let's focus on a signal with a density level of 50%. It can be seen that the height of the signal peaks and the depth of the valleys change depending on the position of the image. When a signal with a concentration of 50% is binarized using a threshold value TH,
In the first part Pa, the peak is larger than THI and the valley is THI.
Therefore, in the binarized signal, peaks appear as recorded pixels and valleys appear as non-recorded pixels.In the latter part pb, both peaks and valleys are larger than THt, so in the binarized signal, In this case, non-recorded pixels do not appear, that is, when binarized with THL. In the first part Pa, halftone dots (recorded dots) can be detected from the arrangement pattern of recorded pixels and non-recorded pixels, but in the later part Pb, halftone dots cannot be detected. Furthermore, when this signal is binarized using a threshold value TH2, in the first part Pa, both the peaks and valleys are smaller than TH2, so no recording pixels appear in the binarized signal, and in the later parts In Pb, the peaks are larger than TH2 and the valleys are smaller than TH, so the peaks appear as recorded pixels and the valleys appear as non-recorded pixels in the binarized signal. Therefore, when binarizing with TH2, one halftone point cannot be detected from the first part Pa, but
In the latter portion Pb, halftone dots (non-recorded dots) can be detected from the arrangement pattern of recorded pixels and non-recorded pixels. In other words, if the threshold value TH is used to detect halftone dots made up of recorded dots, and the threshold value TH2 is used to detect halftone dots made up of non-recorded dots, then the density is 50%. Even in a halftone image, halftone dots, either recorded dots or non-recorded dots, are detected. Concentration is 20%
When the density is low, such as TH1, the halftone dots of recorded dots are detected, and when the density is high, such as 80%, the halftone dots of non-recorded dots are detected using the threshold TH2. Detected. Furthermore, recording dots that appear when the density is low are generally circular, but they appear when the density is high. Since the non-recorded dots are background parts formed between a plurality of recorded dots, their shape is quite different from that of the recorded dots. Therefore, it is very difficult to detect recorded dots and non-recorded dots by comparing them with one reference pattern, and erroneous detection is likely to occur. Therefore, in the present invention, the detection patterns for detecting recorded dots and the detection patterns for detecting non-recorded dots are of different types. The most suitable pattern is used for each dot detection. Thereby, both recorded dots and non-recorded dots can be detected with high accuracy. Other objects and features of the present invention will become clear from the following description of an embodiment with reference to one drawing. [Embodiment] FIG. 2 shows the configuration of a mechanical section of a digital copying machine of one type that implements the present invention. Referring to FIG. 2, this copying machine is comprised of a scanner 1 placed above the apparatus and a printer 2 placed below the apparatus. 26 is a contact glass on which the original is placed. The scanner 1 scans and reads an image of a document placed on a contact glass 26 . The sub-scanning is mechanical, and a carriage provided in the scanner moves to the right and left in FIG. 2 by driving the electric motor MT. Reflected light from the original is imaged on a fixed image reading sensor 10 via various mirrors and lenses. The image reading sensor 10 is
This is a COD line sensor, and in FIG. 2, 5000 reading cells are arranged in a row in the direction perpendicular to the paper surface. In this example, when the copy magnification is 1.0, the resolution is 16 pixels per 1 mm of the original image. Main scanning is performed by the COD installed inside this image reading sensor 10.
This is done electrically by a shift register. The direction of main scanning is the direction in which the reading cells are arranged, that is, the direction perpendicular to the plane of the paper in the first direction. Signals obtained by reading the original image with the scanner 1 are sent to the printer 2 after being subjected to various processing. The printer 2 performs binary printing in accordance with the signal. The printer 2 includes a laser writing unit 25. Photosensitive drum 3. Electric charger 24. Developing device 12° transfer charger 14. Separate charger 15. It is equipped with 1 device 23, etc. Since this printer 2 has no particular differences from conventionally known general laser printers, only the operation will be briefly described. The photosensitive drum 3 rotates clockwise in FIG. Then, the surface thereof is uniformly charged to a high potential by the energization of the electrification charger 24. This charged surface is irradiated with laser light modulated by a binary signal corresponding to the image to be recorded. The laser beam repeatedly scans the photosensitive drum 3 in the main scanning direction by mechanical scanning. The electrical potential of the charged surface of the photosensitive drum 3 changes when it is irradiated with laser light. Therefore, a change in the laser beam, that is, a potential distribution depending on the image to be recorded is generated on the surface of the photosensitive drum 3. This potential distribution is an electrostatic latent image. When the portion on which the electrostatic latent image is formed passes through the developing device 12, toner is attached depending on the potential thereof, and the electrostatic latent image is developed into a toner image, that is, a visible image. This visible image overlaps the transfer paper fed from the paper feed cassette 4 or 5 to the photosensitive drum 3, and is transferred onto the transfer paper by the bias of the transfer charger 14. The transfer paper on which the image has been transferred passes through a fixing device 23 and is discharged onto a paper discharge tray 22 . FIG. 3 shows the configuration of the electric circuit of the digital copying machine shown in FIG. 2. Referring to FIG. 3, the scanner 1 includes an image reading sensor 10. Scanning control section 20. Amplifier 30. A/D (analog/digital) conversion o40, halftone processing section 50.2
Value processing unit 60. Area determination unit 70. Operation control unit 80. It is equipped with an output control section 90° motor driver MD, etc. The scanning control unit 20 performs signal exchange with the printer 2, main scanning control, sub-scanning control, and generation of various timing signals. Various timing signals are generated in synchronization with the scanning timing. Various status signals, print start signals, copy magnification signals, etc. are sent from the printer 2 to the scan control section 20. The scan control unit 20 sends a scan synchronization signal, a status signal, etc. to the printer 2. By driving the motor MT, the scanner mechanically scans and performs sub-scanning. The image reading sensor 10 includes a large number of reading cells, a CCD shift register, etc., like a general CCD line sensor. When the scan control unit 20 outputs the sub-scanning synchronization signal, the signals accumulated in a large number of reading cells of the image reading sensor 10 are transferred to each bit of the CCD shift register at once. Thereafter, the signal of the CCD shift register is shifted in synchronization with the main scanning pulse signal, and the image signal held in the register appears as a serial signal at its output terminal one pixel at a time (a in Figure 3). (Hereinafter, signals generated from image signals are shown in parentheses). The amplifier 30 amplifies the image signal (a), removes noise, etc., and the A/D converter 40 converts the analog image signal (a) into 6
Convert to bit digital signal. Although not shown in the drawings, the digital signal obtained by the A/D converter 40 is subjected to various conventional image processing such as shading correction, background removal, black and white conversion, etc. It is output as a digital image signal (b) of bits, that is, 64 gradations. This digital image signal (b) is processed by the halftone processing section 50°2.
The signal is applied to the value conversion processing section 60 and the area determination section 70. The halftone processing section 50 processes a 6-bit digital image signal (b
) into a binary signal (d) containing halftone information using the submatrix method. A circuit for performing halftone processing using the submatrix method is well known, and since no special circuit is used in this embodiment, the specific configuration and operation will be omitted. Note that, in addition to the submatrix method, halftone processing may be performed using a dither method or a J-degree pattern method. The binarization processing unit 60 performs MTF correction on the input 6-bit digital image signal (b), compares the correction result with a predetermined fixed threshold level TH3, and converts the input 6-bit digital image signal (b) into a binary signal according to the magnitude thereof. Output signal (e). Therefore, the processing performed here is simple binarization processing, and the signal (e) does not include information on the halftone density of the original image. As will be described later, the area determination section 70 is a circuit that determines whether or not the original image includes halftone information, and outputs a binary signal (f) according to the determination result to the output control section 90. The operation control section 80 provides the output control section 90 with a mode signal (g) according to the operation of the mode key of the operation board main. The output control unit 90 outputs a binary image signal ( d) Selectively output the binary image signal (, ) or a signal at a predetermined level (white level) output by the binarization processing unit 60. This signal (h) is given to the printer 2 as a recording signal. The printer 2 modulates the laser beam according to this binary signal and performs recording. FIG. 1 shows the configuration of the area determining section 70 shown in FIG. 3. 1st
Referring to the figure, the area determination section 70 includes a first determination section 71.
It consists of a second determination section 72 and an OR gate 73. 1st
A 6-bit image signal (b) is applied to the determination unit 71,
The upper two bits (b5, b6) of the image signal (b) are applied to the second determination section 72. At the output of the region determining section 70, a logical sum signal (f) of the signal <1) outputted by the first determining section 71 and the signal (r) outputted by the second determining section 72 appears. The first determination unit 71 includes the binarization circuit 110. Y delay circuit 12
0. It consists of an X delay circuit 130 and an AND circuit 140. Note that in this specification, the symbol X or X is used to indicate the main scanning direction of the scanner, and the symbol y is used to indicate the sub-scanning direction.
Or use the symbol Y. Further, "rl" of the binary image signal corresponds to the black pixel level, and "0" corresponds to the white pixel level. The details of the configuration of the first determination section 71 are shown in FIG. 4, and examples of signal waveforms and timing of each section are shown in FIGS. 5 and 6. The details of the first determination section will be explained with reference to FIG. The binarization circuit 110 includes a digital comparator 111° pull-up circuit 112 and a switch circuit 113. The digital comparator 111 compares the value of the digital image signal (b) applied to its 6-bit input terminal A with the value of the digital reference signal applied to the other 6-bit input terminal B, and performs the comparison. Output the results. That is, if A≧B, the signal (j) becomes “1” (corresponding to high level H; the same applies below); otherwise, the signal (j) becomes “0” (corresponds to low level L - the same applies below). Become. Each switch of the switch circuit 113 is set so that the value of the input terminal B of the comparator 111 becomes a predetermined threshold value THJ. Although this threshold value TH3 can be changed, it is usually set to a fairly low concentration level, as shown in FIG. In this example, the threshold value TH4 used by the binarization processing unit 60 is set to the center level (32) of the density gradation. In other words, the binarization circuit 110 determines the black level even for pixels whose density is considerably lower than the normal black pixel determination level. The Y delay circuit 120 is a circuit that processes the signal (j) output from the binarization circuit 110 and delays the timing of the signal by a predetermined pixel in the y direction, that is, in the sub-scanning direction, and delays the timing of the signal by a predetermined amount of pixels in the y direction, that is, in the sub-scanning direction. Output. In FIG. 4, a signal jn represents a signal obtained by delaying the signal j by n pixels in the y direction. The signal has the same delay amount as signal j3. By delaying the signal pixel by pixel in the y direction, signals from multiple pixels adjacent to each other in the y direction can be extracted as parallel signals. In other words, this circuit can also be regarded as a serial-parallel conversion circuit. FIG. 5 shows the operation timing of the Y delay circuit 120. The operation will be explained with reference also to FIG. The input signal (j) is latched by the latch 121 by a clock pulse t2 output at a timing for each pixel in the X direction. That is, the signal (j) applied to the input terminal D1 of the latch 121 appears at its output terminal Q1, and its state is maintained. By clock pulse t3, latch 1
The states of the output terminals Ql-Q6 of 21 are stored in each bit of a RAM (read/write memory) 123 at timing for each pixel in the X direction. The memory address to store is specified by address signal t1. The content of this address signal t1 is updated for each pixel in the X direction, and the same content (value) is set for pixels located at the same position in the X direction. That is, the signal t1
corresponds to the pixel position in the X scanning direction. In this example, since the number of pixels in the X direction is 4096, the signal t1 is a 12-bit parallel signal. The memory contents of RAM l 23 are clock pulses.

[3], each pixel in the X scanning direction is read out. The data read is the data previously stored at the current X-direction position. If we pay attention to the connections between the data lines D1 to D6 of the RAM 123 and the latch 121, we can see that R
AM123 data line bits 1, 2, 3, 4, 5
and 6 are bit 2 of the input terminal of the latch 121, respectively.
, 3, 4, 5. It is connected to G and 7 in a shifted state by one bit. Therefore, a signal (j) input at a certain timing is latched into bit 1 of the latch 121, and stored in bit 1 of the RAM 123 before the next pixel data is set in the latch 121. Then, at a timing delayed by one pixel in the X direction, bit 1 of the RAM 123 is read out and applied to the bit 2 input terminal D2 of the latch 121. This signal is latched into bit 2 of the latch 121 at the timing when a pixel signal appearing delayed by one pixel in the X direction is latched into bit 1 of the latch 121 at its X position. Thereafter, by repeating this operation, the signal is transferred to latch 1.
21 bits 3, 4, 5. G and 7, timing is X
The data is transferred sequentially every time one pixel is advanced in the direction. That is, when the signal is latched to bit 7 of latch 121, each bit 6.5, 4, 3, 2, and 1 of latch 121 has a value of 1, 2.3 in the X direction relative to the signal of bit 7, respectively.
．． There are signals delayed by 4.5 and 6 pixels. As a result, signals from seven pixels adjacent to each other in the X direction at a predetermined X position are obtained at the output terminals Ql-Q7 of the latch 121 at the same timing. Note that the latch 122 is used to adjust the timing of sending a signal to a circuit connected to the output of the Y delay circuit 120. Therefore, signals jO-j6 are substantially the same as the signals output by latch 121. In addition, in FIG. 6, symbols J1+J2+...B
l, B'2. B3... and At, A2. It should be noted that the signals indicated by A3 . . . represent changes in each pixel in the X direction, and are different from the signals output by the latch 122.・The signal outputted by the Y delay circuit 120 includes the xH delay circuit 1
30. The X delay circuit 130 is composed of one shift register, as shown in FIG. Signal (k) is applied to the serial data input terminal of the shift register. From the parallel data output terminals Q1 to Q7 of this shift register, signals (kl, 2., 3., 4.
5. 6 and 7) are output. This shift register (130) shifts data one bit at a time each time a clock pulse t4, which is output every time the scanning position in the X direction changes pixel by pixel, appears. For example, a signal applied to this shift register at a certain timing is cursed by bit 1 (kl) of the output terminal at the next pixel timing (X direction), and every time the pixel timing changes, bits 2, 3, etc.
4, 5.6 and 7 in sequence. That is, for example, when the signal of the pixel located at N in the pixel coordinates in the X direction is cursed as the signal (kl). The position of the pixel appearing in each signal (k6., 5., 4., 3., 2.kl) is the same as (kl) in the X direction, and N+l, N+2. N+3°N+4. N+5 and N+6. That is, the signals (kl~7) are signals of seven pixels located at pixel positions adjacent to each other in the X direction, and these are obtained at the same timing. Therefore,
The X delay circuit 130 is a serial delay circuit for serial pixel signals.
It can also be considered as a parallel conversion circuit. The signals (jO-36 and 1 to 7) output from the Y delay circuit 120 are applied to the AND circuit 140. The AND gate 141 outputs 1 when all the signals (jO"j6) are 1, and outputs 0 otherwise.
The signal (jlo) output from the AND gate 141 is
Seven pixels that are at the same position in the X direction and that are adjacent to each other in the X direction become 1 when all of them are at the desired level (with respect to TH). This signal is delayed by a predetermined pixel (one pixel) in the X direction by the shift register 143, and is applied to the AND gate 144 as a signal (jll). The AND gate 142 outputs 1 when all the signals (kl~7) are 1, and outputs 0 otherwise. Therefore, the signal (k 10
) becomes 1 when all seven pixels adjacent in the X direction are at the same position in the X direction and are at the black level (with respect to TH). The AND gate 144 connects the signal (Jll) and the signal (k
10), that is, the signal (1) is output. In other words, regarding the pixel of interest at that time, the first determination unit 71 determines whether there is halftone information ( l is determined to be 1). The reason why the shift register 143 is provided to shift the signal (jlL) in the X direction with respect to the signal (jlo) is to adjust the timing of the seven pixels in the X direction and the seven pixels in the X direction. That is, the signal (jO to jG) is the signal (k
), in order to obtain the signal (k4) corresponding to the center pixel in the X direction and the signal (jll) at the corresponding X position, the signal is changed by one pixel (4 pixels in this example) in the (Jio) is being shifted. In other words, since many micropatterns are generally close to circular, it is preferable to arrange the pixel of interest at the center pixel of the pixel group forming the "+" shaped pattern. Please refer to FIG. Note that in this figure, only the X direction is shown for easy understanding. Digital image signal (
Since the data b) is 6 bits, it contains 64 levels of density gradation information. In this example, each part ([l+++B+2) of the signal (b) shown in the figure indicates a signal obtained by reading a halftone image such as a photograph. (B+3) indicates a signal obtained by reading a background (i.e., white) image, (Bla) indicates a signal obtained by reading a character written with a relatively thick line (i.e., a binary density pixel), (B+
s) indicates a signal obtained by reading characters written with relatively thin lines, and (B+e, th 7) indicates a signal obtained by reading dirt on a document. In the binarization circuit 110, the low density level TH3 is set as the threshold level and the signal is binarized, so the obtained image signal (j) has a very low image density. Even in this case, all the parts where the image exists correspond to black pixels. On the other hand, in the signal (e) output from the binarization processing unit 60 with the intermediate level 32 set as the threshold value, in the halftone image, parts with low density correspond to white pixels, and parts with low density correspond to white pixels. Only dark areas correspond to black pixels. The signal (k10) becomes 1 only when the black of one image correction is cursed for 7 consecutive pixels in the
z 1+Bt 2 +Bt a ), the signal (k
10) becomes 1, but other parts (81J+BIS
g”1s +Bt 7 ), it becomes O. Normally, the halftone processed signal (d) and the binarized signal (e) are selected according to this signal (k 10). Therefore, the parts indicated by A, B, and C of the signal (h) shown in FIG. 6 correspond to the halftone-processed signal (d), and the other parts, E and F, are binarized. Here, C, D, and E are parts of the same character, but D and E (each 6 pixels in the X direction) corresponding to the outline part are
Since the number of pixels does not reach 7 pixels, which is the condition for determining halftone information, binarization processing is performed. Each part of the image signal (b) ([1161
B+7) is binarized with respect to the threshold level TH4, so that stains on the document are not output as a copy image. The second determination section 72 will be explained with reference to FIG. Simply put, the second determining section 72 is a circuit that determines the presence or absence of a halftone pattern. Moreover, this second determination section
A circuit for detecting black dots in halftone dots, a circuit for detecting white dots in halftone dots, a circuit for identifying the presence or absence of halftone dots in the first area, a circuit for identifying the presence or absence of halftone dots in the second area, and a third circuit for detecting the presence or absence of halftone dots in the second area. It consists of a circuit that identifies the presence or absence of halftone dots in an area. A black dot detection circuit 160 detects black dots in halftone dots. The black pins 1~ here are 1, for example 10% as shown in Figure 8.
As shown with hatching and 30% halftone dots,
These are regularly arranged recording dots (generally black dots). The black dot detection circuit 160 has XY3J! The signal (mij) for 29 pixels outputted by the extension circuit 150 is processed to identify the presence or absence of a black dot. The XY delay circuit 150 is a circuit that delays signals in the X and X directions and outputs signals of a plurality of pixels included in a predetermined two-dimensional area at the same timing. This circuit 150
The most significant bit (MSB) of the input image signal (b) is
) is applied. Therefore, the signal processed by the XY delay circuit 150 is a binary signal that becomes 1 if the gradation of the image signal (b) is 32 or more, and becomes 0 otherwise. That is, the circuit for detecting black dots detects black dots by referring to a signal obtained by binarizing the image signal (b) using the threshold value 32 (THE). Further, a white dot detection circuit 220 detects white dots at halftone dots. The white dot referred to here is, for example, the 8 dot shown in FIG.
As shown by the 0% halftone dot and the 8th dot, it is a gap between regularly arranged recording dots, that is, a non-recording dot (generally a white dot). The white dot detection circuit 220 processes the signal (Cij) for 13 pixels output from the xy delay circuit 2]0 to identify the presence or absence of a black dot. XY! ! The delay circuit 210 is a circuit that delays signals in the X and Y directions and outputs signals of a plurality of pixels included in a predetermined two-dimensional area at the same timing. This circuit 21
0 includes the upper 2 bits (b5
．． The AND of b6) is applied. Therefore, the signal processed by the XY delay circuit 210 has a gradation of 48 in the image signal (b).
It is a binary signal that becomes 1 if the value is above or equal to 0, and 0 otherwise. In other words, in the circuit that detects white dots, the image signal (
White dots are detected with reference to the signal obtained by binarizing b) using a threshold value 48 (TH2). The signal (n) is set to Ilo depending on the presence/absence of the black dot, and the signal (p) is set to 110 depending on the presence/absence of the white dot.
is set to The logical sum of the signals (,) and (p), ie, the signal (ql), is applied to the first area detection circuit 170. The first area detection circuit 170 processes the signal (ql) and outputs the signal (q2), the second area detection circuit 180 processes the signal (92) and outputs the signal (93), and the third area detection circuit 180 processes the signal (ql) and outputs the signal (93). Circuit 190 processes signal (q3) and outputs signal (r). The logical sum of this signal (r) and signal (1) is
The area determining section 70 outputs the signal (f). FIG. 7a shows the configuration of the xy delay circuit 150. Referring to FIG. 7a, this circuit includes Y delay circuit 151
and an X delay circuit. The configuration of Y delay circuit 151 is the same as Y delay circuit 120 shown in FIG. However, since a signal corresponding to the signal (k) is not required, only seven output terminals of the latch 122 are used. In other words, the signal (m
11 to m17) correspond to seven pixels that are the same in the X direction and adjacent to each other in the Y direction. The X delay circuit consists of six 7-bit latches 152.15'3
, 154, 155, 156 and 157. The latch 152 receives a signal (m 11-
m 1? ) and latch 153, 154.155
, 156 and 157 are latches 152 and 153, respectively.
, 154, 155 and 156 output signals (m21"
= m27), (m31"m37). (m41-m47), (m51-m57) and (m6
1-m67) is latched in synchronization with clock pulse t4. Therefore, each signal (m21.m31.m41.m51
．． m61 and m71) are the signals (m 11 ), respectively
The signal is delayed by 1.2, 3 degrees, 4.5 degrees, and 6 pixels in the X direction. That is, the XY delay circuits 150 and 150 are adjacent to each other. The signals mij of each pixel of a 7×7 pixel matrix composed of 7 pixels in the X direction and 7 pixels in the y direction are all output at the same timing. FIG. 7b shows a specific configuration of the black dot detection circuit 60. Referring to FIG. 7b, this black dot detection circuit 1
60 consists of four gate circuits 161, 162, 163 and 164. Gate circuits 161, 162 and 1
A signal mij output from the XY delay circuit 150 is applied to 64. In this embodiment, the detection pattern shown in FIG. 9a is used to detect black dots. That is, FIG. 9a shows a two-dimensional matrix area consisting of 7x7 pixels, in which the pixels (m
44) is at the black pixel level and all 12 pixels indicated by O are at white pixel level, or when the pixel marked by x is at black level and all 16 pixels indicated by Δ are at white pixel level. The condition is such that the case is identified as having a black dot (ie, 1), and the other cases are identified as having no black dot (ie, O). In order to detect the pixel marked 0 in FIG. 9a, the input terminal of the gate circuit 161 shown in FIG. 7b is connected to 12 pixels:
nt23. m24. m25. m32. m36.
m4Lm46. m52. m56. m63. m
64 and m65 signals are applied. In addition, in order to detect the pixel marked Δ in FIG. 9a, the gate circuit 'jP1162
The input terminal of 16 pixels m13. m14. m
15. m22. m26. m31゜m37. m41.
m47. rn51. m57. rn62. m66
, m73°m74 and m75 signals are applied. If at least one of the gate circuits 8161 and 162 is 1 and the signal of the center side lAm44 is 1, the output (n
) becomes 1, and a black dot is detected. Further, in this embodiment, the detection pattern shown in FIG. 9b is used to detect the self-dot. That is, FIG. 9b shows a two-dimensional matrix area consisting of 5×5 pixels, in which the pixels (c
33) is the white pixel level and all 4 pixels indicated by the parentheses 0 are at the black pixel level, or the pixel marked by x is at the white level and all 8 pixels indicated by Δ are the black pixel level. The condition is such that the case where this is the case is identified as having a white dot (ie, 1), and the other cases are identified as having no white dot (ie, 0). The XY delay circuit 210 and white dot detection circuit 220 realize this detection. The function of the XY delay circuit 210 is the same as that of the circuit 150 already described, and one circuit configuration is the same as that of circuit 1 because the size of the two-dimensional area is reduced to 5×5.
It is NIQ than 50. A specific configuration of the white dot detection circuit 220 is shown in FIG. 7c. Referring to FIG. 7c, this circuit consists of four gate circuits 221, 222, 223 and 224. The input terminal of the gate circuit 221 is connected to the pixel c23.0 marked 0 in FIG. 9b. c32. Signals c34 and c43 are applied. In addition, the 9th b
The pixel marked Δ in the figure c13°c22. c24. c31.
c35. c42. Signals c44 and c53 are applied. At least one of the outputs of the gate circuits 221 and 222 is 1
And, if the signal of the center pixel e33 is 0, the 9th b
Since the conditions shown in the figure are satisfied, the output (p) of the white dot detection circuit 220 becomes 1, and a white dot is detected. Figure 10a shows an example of the positional relationship between dots and pixels when reading a halftone image, and Figure 10b shows the signal arrangement obtained by binarizing the signals of each pixel in Figure 10a using a predetermined threshold. show. Consider the case where the presence or absence of halftone dots is identified from the signal shown in FIG. For example, when the position of the pixel of interest m44 is Jf: 4 (6, 4) in FIG. 10b, the pixel indicated by the x mark in FIG. 9a is at the black pixel level, and the pixel indicated by the 0 mark in FIG. 9a. Since all of the pixel groups and all of the pixel groups indicated by Δ are at the white pixel level, the output (n) of the black dot detection circuit 160 becomes 1 (black dot present). As already explained, in this embodiment, the threshold level THI when the black dot detection system binarizes the image signal and the threshold level TH2 when the white dot detection system binarizes the image signal are set. are different from each other. As will be explained below, this is very effective in eliminating halftone detection errors when the density in halftone printing is around 50%. In Figure 14, the concentrations are 20%, 50% and 80%, respectively.
The figure shows gradation image signals obtained by reading halftone printed images and signals obtained by converting them into binary values. Referring to FIG. 14, when an image with a density of 20% is binarized using a threshold value TH, a binary signal (ba) corresponding to the density of the image (switching between recorded pixels and non-recorded pixels) is obtained. However, it can be seen that when binarized with the threshold value TH2, the shading of the image does not appear in the binary signal (b b). Also, for an image with a density of 80%, the threshold 'rt-
It can be seen that when the image is binarized with ti, the shading of the image does not appear in the binary signal (ba), but when it is binarized with the threshold value TH2, the shading of the image appears in the binary signal. Furthermore, when focusing on an image with a density of 50%, it can be seen that the height of the peaks and the depth of the valleys of the signal change depending on the position of the image. This type of change is a state in which adjacent black dots or white dots become continuous. In other words, this occurs when a black dot and a white dot switch places, or when a dot is unclear as to whether it is black or white. Detection of halftone dots for this type of dot has conventionally been extremely difficult. When a signal with a concentration of 50% is binarized with a threshold value TH, in the first part Pa, the peak is TH and the larger valley is TH.
Since it is smaller than I, the binarized signal (ba) has
The peaks appear as recording pixels and the valleys appear as non-recording pixels. In the latter part pb, both the peaks and the valleys are larger than TH1, so no non-recording pixels appear in the binarized signal (ba). That is, when binarizing with THt, halftone dots (recorded dots) can be detected from the arrangement pattern of recorded pixels and non-recorded pixels in the first portion Pa, but no halftone dots can be detected from the later portion Pb. Furthermore, when this signal is binarized using the threshold value TH2, in the first portion Pa, both the peaks and valleys are smaller than TH2, so no recording pixels appear in the binarized signal (b b). In the latter part Pb, the peak is larger than TH2 and the valley is T
I(, is smaller than I), so in the binarized signal (bb), peaks appear as recorded pixels and valleys appear as non-recorded pixels. Therefore, when binarized with TH2, halftone dots are detected from the first part Pa. However, in the latter part Pb, halftone dots (non-recorded dots) can be detected from the arrangement pattern of recorded pixels and non-recorded pixels.In any case, if the density is low, that is, black dots If you want to detect dots, the peak and valley levels of the signal are low, so by setting the threshold level relatively low (to TH1), you can expect reliable dot detection and also reduce the concentration. If it is high, that is, if you want to detect a white dot, the peak level and valley level of the signal are high, so by setting the threshold level relatively high (to TH2), reliable dot detection can be achieved. Furthermore, by appropriately setting the threshold value TH2 for white dot detection and the threshold value TH for black dot detection, even when the halftone image density is 50%, A change appears in either of the two signals (ba, bb) depending on the density of the image. In this example, dot detection is performed by comparing the pattern of change in the binary signal with the reference pattern, so the image The fact that density changes appear in the binary signal means that dot detection is possible.
Even in the vicinity of 0%, no error occurs in halftone dot detection. Further, in this example, the detection pattern used to detect a black dot (FIG. 9a) and the detection pattern used to detect the own dot (FIG. 9b) are different from each other. This is because the shapes of black dots and white dots are essentially different. In other words, the black dots are generally circular in shape, and the white dots are not circular because they are in the gaps between multiple circular black dots.This shape also prevents printing problems such as ink bleeding. The influence of deformation of the dot shape due to the properties of
Each changes depending on the resolution characteristics of the image reading system and the influence of flare. Furthermore, even in images that are not halftone dots, there may be cases in which characters or the like form a pattern that can be confused with black dots or self-dots, and it is better not to erroneously detect these as dots, that is, halftone dots. Therefore, in this example, each detection pattern is determined by selecting the matrix size most suitable for each of black dots and white dots, and the arrangement pattern of black pixels and white pixels. The output of the gate circuit 232 includes a binary signal (q
1) appears, but in order to improve the accuracy of identifying whether the dot is a halftone dot or not, in this example, processing to be described later is further performed to identify the presence or absence of a halftone dot. FIG. 7d shows a specific configuration of the first area detection circuit 170. Simply put, this first area detection circuit 170 consists of a predetermined pixel matrix (this is called a first area) consisting of a W image 74 in the X direction (e.g. 8 pixels) and a W pixel in the y direction as shown in FIG. Assuming that, 1 in this first area
Determine whether there are more than 1 dots. signal q
2 is 1 if a dot exists. 0 if not present
become. Referring to FIG. 7d, this circuit 170 includes a read-only memory RO old, a counter CN1 . CN2° flip-flop FFL, FF2. Read/write memory RAM 1,
Gates Gl, G2. G3. G4. It consists of G5+G6t inverter tVt and IV2. The operation timing of the circuit of FIG. 7d is shown in FIG. 12a. Counter CNI counts clock pulses t4 and
Count up for each pixel in the direction. When the count value reaches 15, the carry terminal CY becomes high level H.
become. The signal obtained by inverting this signal is the preset terminal LD.
Therefore, when the next clock pulse appears, the data at the input terminals D1 to D4 are set in the counter. In FIG. 12a, the preset data is 8. Therefore, the counter CNI operates as an NJ counter that counts up every time the clock pulse t4 appears. The value of N can be arbitrarily set within the range of 1 to 1G depending on the values applied to the data input terminals D1 to D4. On the signal line Qx, a signal that goes to a low level B appears for one cycle every N clock pulses t4. On the other hand, the signal q2 output for each pixel in the X direction is as follows. It is applied to the flip-flop FFI via the OR gate G1, and latched into the FFI in synchronization with t4. When the signal line Qx is at the fossa level H, the flip-flop FFI
The signal latched in is applied from its output terminal Q to one input terminal of an OR gate G1 via an AND gate G2. Therefore, when the signal q1 becomes 1, the output terminal Q of the flip-flop FFI is set to the low level L on the signal line Qx.
Maintain the state of 1 (H) until . That is, when the counter CNI is set to an octal counter, as shown in FIG. 12a, after the signal q1 for a certain first pixel is cursed by the Q of the FFI as the signal o1, that signal 01 and the next When the logical sum with signal 91 is cursed by the Q of FFI as signal 02 and the signal line Qx becomes low level by repeating the same, all the logical sums of each signal q1 for 8 pixels consecutive in the X direction are The result of the calculation, ie, signal 07, is obtained at Q of the FFI. When signal 07 is present, the next clock pulse t4
When the signal q2 arrives, the signal is latched by the flip-flop FF2, and the latched signal is output as the signal q2. Further, the signal outputted by the FF2 is stored in the read/write memory RAM1 in synchronization with the clock pulse t5. The signal t6 specifying the address of the memory RAMI is
The value is updated every N pixels in the direction to a value corresponding to the position in the X direction. Note that the signal t6 is unrelated to the pixel position in the X direction. Therefore, data for one line in the X direction is stored in the memory RAM1. Furthermore, at the timing of clock pulse t41, the data stored in the previous line (at the position where the relative coordinate in the X direction is -1) is read out from the memory RAMI, and the data is sent to one input of the OR gate G4 via the AND gate G5. On the other hand, the counter CN2 operates as an N-ary counter that counts up every time the clock pulse t7 appears. Clock pulse t7 is a sub-scanning synchronization pulse that is output every time the pixel position in the X direction changes. Other operations are the same as for counter CNI. Therefore, the signal line Qy is normally at a high level H. The low level L occurs once every N pixels in the X direction. While the signal line Qy is at high level. When high level I4 is applied even once to the data terminal of flip-flop FF2, FFI and memory RAM 1 hold the logical sum of it and the input signal, so signal q2
becomes a high level L (In other words, when the signal line Qy becomes a low level L, F
The result of calculating the logical sum of all the signals (for example, 07) output by the FI is output as the signal P. In other words, NX
Regarding a predetermined pixel matrix consisting of an array of N (for example 8 x 8), that is, each first area, if there is even one pixel in the matrix in which No. 48 q1 is 1, the signal q
2 becomes 1, and q2 becomes 0 otherwise. This signal q2 determines the presence or absence of a dot in the first area detection circuit;
That is, it indicates the presence or absence of halftone dots. On the other hand, the data terminals D1 to D4 of the counter CNI are connected to the data terminals D5 to D8 of the read-only memory ROM1, and the data terminals DI-D4 of the counter CN2 are connected to the data terminals D5 to D8 of the read-only memory ROM1.
It is connected to data terminals D1 to D4 of OM1. A copy magnification signal is applied to the address terminal of the memory ROMI. The read-only memory ROMI previously stores information on the size of the first area associated with each copy magnification. For example, in this example, when the copy magnification is 1.0, the first
Since the area size is 8 x 8 pixels, 8 is output to the 4-bit output terminals DI to D4 of the first group of RoMl, and 8 is also output to the 4-bit output terminals D5 to D8 of the second group. do. in this case. The counters CNI and CN2 are set to 8 during presetting, and are 8.9.10, 11.12, 13°14*
It is counted as 15+ 8e 9+ 10..., so
Operates as an octal counter. If the copy magnification is different, the counting range of counters CNI and CN2 will change,
This changes the size and number of pixels of the first area. FIG. 7e shows the configurations of the second area detection circuit 180 and the third area detection circuit 190. First, the second area detection circuit 180 will be explained. Roughly speaking, in the second area detection circuit 180, the 11th
As shown in the figure, there are two first areas that are continuous with each other in the X direction, and two first areas that are continuous with each other in the X direction.
Assuming a second area consisting of four first areas, which are Determine whether If three or more dots are detected in the first area, the signal q3 is set to 1 for a predetermined first area in the second area, indicating that a halftone dot has been detected. The reason for performing such second area detection processing is to prevent the following erroneous detection. In other words, if there is a missing dot on the document side due to a printing error or a dot detection error on the copying machine side due to a reading error, etc., at the stage of signal 92, the halftone dot part is actually replaced with no halftone dot. It may be determined that Furthermore, if the image is not a halftone dot image, at the stage of the signal 92, for example, a part of a character or dirt on the background may be detected as a single dot, and it may be erroneously determined to be a halftone dot area. The operation timing of the second area detection circuit 180 is set to 12b.
As shown in the figure. This will be explained with reference to FIG. 7e and FIG. 12b. 181 is a data selector, 182 and 183 are latches,
184 is a read/write memory. Data selector 181
．． The latch 182 and read/write memory 184 are circuits that delay the signal q2 output for each first area in the X direction by a pixel corresponding to the first area.
Signals from two first areas adjacent to each other in the X direction are obtained at the same timing at the output terminals Q1 and Q2 of. The latch 183 transfers the signal output from the latch 182 to the first
This is a circuit that delays the signals output by the latch 182 to the output terminals Q1 and Q2 of the latch 183 in the X direction by the amount of pixels corresponding to the area, and the signals output from the latch 182 to the output terminals Q1 and Q2 of the latch 183, respectively, by the amount of pixels corresponding to the area in the X direction. A delayed signal appears. Therefore, the signals 92 for each of the four first areas included in the second area are obtained at the output terminals Ql and Q2 of the latch 182 and the output terminals Q1 and Q2 of the latch 183 at the same timing. That is, the first area El, E2°E3 and E4(7) signals q2 in FIG. 11 are 183-01°18, respectively.
2-Ql, 183-02 and 1B2-02. These four signals are connected to gates G11. G12. G1
3. It is processed in G14 and G15 and a signal q3 is generated. If three or more of the four signals (q2) are 1,
For example, El in FIG. E2. If three or more 92 in E3 and E4 are 1, the signal q3 output to the first area E4 becomes 1. In addition, in Fig. 12b, Pan Pb, Pc,
Pd. ... indicates a signal (q2) output for each first area, Qas'lt1m ... indicates a signal (q3) output for each first area, pa -1, pb -1
. Pc-1, ... are Pan pb, Pc, respectively
t”... is delayed by the number of pixels in one first area in the X direction. For example, qb is Pb l
*Determined by four signals: pb, pc-1, and pc. Next, the third area detection circuit 190 will be explained. Roughly speaking, in the third area detection circuit 190, the eleventh
As shown in the figure, four first areas that are continuous in the The signal r is set to 1. The third area detection process is performed to prevent moire. That is, due to the scanning method and structure, the risk of moire occurrence is overwhelmingly greater in the main scanning direction than in the sub-scanning direction. In the sub-scanning direction, there is no moire or it is not noticeable. In the main scanning direction, the reading resolution is generally 16 pixels/m
Moiré occurs when the dot pitch is about 1 to 3 mm, depending on the dot pitch and the relative angle between the document and the scanning. When the amplitude of the read signal decreases due to moire, the accuracy of dot detection decreases, and errors may occur in dot detection. Therefore, if there is no risk of moire occurring, this third area detection process is unnecessary. Note that in this embodiment, the number of pixels in the X direction in the third area is 3.
2 and the reading resolution is 16 pixels/m'm, so the pitch of the third area is 2 rn m. Referring to FIG. 7d, the third area detection circuit 190:
It consists of a shift register 191 and an OR gate 192. The shift register 191 shifts the signal q3 for each number of pixels in the X direction in the first area in synchronization with the clock pulse t41. When the signal q becomes 1 at least once in the four first areas that are continuous in the X direction, the signal r becomes 1 for all the first areas that make up the third area, including that first area. Set. That is, in FIG. 11, when the signal 9 becomes 1 in the first area El in the third area, the other first areas E2 . The signal r becomes 1 also for E5 and E6. FIG. 13 shows the configuration of the operation control section 80 and output control section 90 shown in FIG. 3. In this example, there are actually four operating modes for outputting signals, but only the normally used operating modes will be explained here. That is, when the mode key is set to 3, the automatic separation mode is selected. In this mode, when the signal ([) is 1, that is, when the input image is a halftone or halftone image, the same signal as the signal (d) that has undergone halftone processing by the submatrix method is output to the printer 2. Ru. Furthermore, when the signal (f) is 0, that is, when the input image is a binary image other than halftone dots, the threshold l[
The same signal as the signal (,) simply binarized by i T Ha is output to the printer 2 . Therefore, halftone processing is performed on the halftone-processed image, thereby preventing the occurrence of moiré. Note that as the black dot detection pattern and the white dot detection pattern, patterns other than those shown in the above embodiments may be used. For example, as the black dot detection pattern, the 15th
Figure a and 15bI! Those shown in I can be used. Furthermore, the pattern shown in FIG. 15c may be used as a black dot detection pattern, and the pattern shown in FIG. 15d may be used as a white dot detection pattern. The patterns shown in FIGS. 15c and 15d are effective for halftone dots with a coarse pitch, such as halftone dots for newspaper printing. [Effects] As described above, according to the present invention, false detections in halftone dot detection can be reduced. In particular, it has been confirmed that while conventional methods have partially caused false detections in halftone images of about 30% to 60%, this has been significantly improved by implementing the present invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the area determining section 70 shown in FIG. 3. As shown in FIG. It is. FIG. 2 is a front view showing a mechanical section of one type of copying machine embodying the present invention. FIG. 3 is a block diagram showing the electrical circuit of the copying machine of FIG. 2. FIG. 4 is an electrical circuit diagram showing the first determination section 71 of FIG. 1. 5 and 6 are timing charts showing the operation of the circuit of FIG. 4. FIG. FIGS. 7a, 7b, 7c, 7d, and 7e are electrical circuit diagrams showing the configuration of the second determination section 72 shown in FIG. 1. FIG. 8 is a plan view showing an enlarged image printed with halftone dots at four different densities. FIGS. 9a and 9b are plan views showing pixel arrangement patterns when detecting black dots and white dots, respectively. FIG. 10a is a plan view showing a part of a halftone-printed image;
FIG. 10b is a plan view showing the binary code obtained by reading the image in FIG. 10a. FIG. 11 shows the first area assumed by the first determination unit 72,
FIG. 3 is a plan view showing the configuration of a second area and a third area. FIGS. 12a and 12b are timing charts showing the operations of the first area detection circuit 170 and the second area detection circuit 180, respectively. FIG. 13 is an electrical circuit diagram showing the configuration of the operation control section 80 and the output control section 90. FIG. 14 is a timing chart showing a gradation image signal and a signal binarized using two types of thresholds. Figures 15a, 1.5b, 15c and 15d
The figure is a plan view showing a modified example of the dot detection pattern. 1: Scanner 2: Printer (recording means) 3: Photosensitive drum E0: Image reading sensor 40: A/D conversion D50: Medium 17fl tone processing section 60: Binarization processing section 7
0: Area determination unit 71: First determination unit 72: Second determination unit 80: Operation control unit, 90: Output control unit 110: Binarization circuit i 120: Yij[f circuit 130: X delay circuit 140: Logical product Circuit 150: XY delay circuit (first
(binarization means) 160: Black dot detection circuit (recorded dot detection means) 170: First area detection circuit 180: Second area detection circuit 190: Third area detection circuit

Claims (4)

[Claims] (1) A first binarization means that binarizes the input image information using a first threshold value; recorded dot detection means that compares the array pattern with a predetermined recorded dot detection pattern and outputs the result; a recording dot detection means that binarizes the input image information with a second threshold different from the first threshold; 2. Binarization means; The second binarization means includes a non-recorded dot detection pattern that differs from the recorded dot detection pattern in at least one of pattern size, pattern arrangement, and number of detection conditions; non-recording dot detection means that refers to the output binary information, compares its two-dimensional array pattern with the non-recorded dot detection pattern, and outputs the result;
and halftone pattern identification means for identifying whether input image information is a halftone dot pattern based on the output of the recorded dot detection means and the output of the non-recorded dot detection means. (2) The first binarization means and the second binarization means are
Each of them delays the input image information input in time series in the main scanning direction and the sub-scanning direction pixel by pixel, and simultaneously outputs the information of multiple pixels lined up in the main scanning direction and the sub-scanning direction as two-dimensional information. An image area identification device according to claim 1, comprising dimensional information generation means. (3) The dot pattern identification means identifies the number or presence/absence of information output by the recorded dot detection means and the non-recorded dot detection means for each predetermined two-dimensional area of input image information, An image area identification device according to claim (1). (4) Claims (1) and (2), wherein the second threshold is associated with a level in which the image density becomes greater than the first threshold. Section or section (
The image area identification device described in section 3).