JPS6326939B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to broadcast communication, and particularly to a broadcast communication terminal control device for transmitting and receiving control signals between a terminal and an exchange.

In conventional broadcast communication, control information regarding a destination terminal, such as a destination terminal selection signal, is individually set for each destination terminal. Therefore, selection signals equal in number to the number of destination terminals are successively transmitted from the originating terminal to the exchange, resulting in an increase in the time required for broadcast connection.

In addition, at the originating terminal, it is necessary to set the selection signal at least as many times as the number of destination terminals to which broadcast communication is to be performed, which increases the time and complexity of the circuit. I didn't get it. In exchanges, the reception of selection signals and translation processing increased, resulting in a decrease in processing capacity. Furthermore, there was no way to know the status of the receiving terminal.

In order to eliminate these drawbacks of the prior art, this invention realizes a broadcast communication terminal control device that can transmit and receive control information regarding multiple destination terminals between a calling terminal and an exchange using simple and unified signals. The purpose is to

According to the present invention, the transmitting circuit includes a synchronizing signal generating circuit, a function specifying information holding circuit that specifies the type of control information, and a terminal specifying circuit that corresponds one-to-one to a plurality of terminals and specifies the plurality of terminals by bit information. The information holding circuit is configured to sequentially send a synchronization signal, function designation information, and terminal designation information to the exchange one bit at a time, and in the receiving circuit, a synchronization signal detection circuit detects the synchronization signal from a control signal from the exchange. , subsequent function designation information and terminal designation information are sequentially distributed and held in the holding circuits, respectively.

Next, examples will be described in detail.

FIG. 1 shows an embodiment of the operation panel in the terminal control device of the present invention, in which a push button switch 301 for specifying a destination terminal and a display lamp 302 for indicating a destination terminal are arranged so that the number of terminals at least equal to the number of destination terminals registered in the switching equipment, In this case, 24 terminals are provided, and they are matched one-to-one with the destination terminal. The push button switch 301 is turned on when specifying the destination terminal, and the display lamp 302 is turned on when the destination terminal is specified using a signal from the exchange. A signal type display section 303 displays the type and content of the signal received from the exchange, and a numeric keypad 304 is used to designate the type of signal to the exchange and to enter a dial when connecting a general call. An indicator lamp 305 indicates that a dial-ready signal has been received from the exchange, a push-button switch 306 for instructing transmission of a broadcast communication signal, a push-button switch 307 for transmitting a calling signal, and a push-button for transmitting a call disconnection signal. Switches 308 are provided, and when each switch is turned on, a corresponding signal is transmitted.

FIG. 2 shows an embodiment of the control signals used in the present invention, and the control signals exchanged between the originating terminal and the exchange are uniformly displayed in this signal format. The signal format consists of a synchronization signal section 2, a function setting section 3, a destination terminal designation section 4, and an end signal section 5. The synchronization signal section 2 and termination signal section 5 are determined by the signaling system of the network for communication. The function setting section 3 has meanings as shown in FIG. 3 according to its contents. Destination terminal designation section 4
The function setting unit 3 indicates which terminal the function of the signal is related to by setting a 1-bit value αj in the bit position j determined in advance for the terminal.
It is indicated by (0 or 1). This bit position j is the push button switch 3 for specifying the destination terminal in FIG.
01 and the terminal terminal display lamp 302, respectively. However, when the selection signal for one-to-one communication is set in the function setting section 3, a normal character dial is set in the terminal designation section 4.

In the case of broadcast communication, the originating terminal uses the signal format shown in FIG. 2 to send a broadcast selection signal to the exchange as a control signal. When the signal system of this communication network uses a character synchronous transmission method using the SYN character, the originating terminal is _T0 , the destination terminal is _T1 ...Tn, and each bit of the terminal designation part 4 is sequentially set from the beginning to the destination terminal T. ₁ to correspond to Tn. It is assumed that this correspondence relationship has been registered in advance from the originating terminal to the exchange. Assuming that the control signal is divided into 8-bit units by "|", SYN | SYN | 00000010 |
0α ₁ α ₂ ……α ₇ ｜0α ₈ α ₉ ……α ₁₄ ｜……｜0α _o-2 α _o-1
αn0000｜+. Here, SYN=00010110 is a synchronization character indicating the synchronization signal section 2, and 00000010 is the function setting section 3, which is a selection signal in the broadcast signal from FIG. +=10101011
is an end character indicating the end signal part 5.
0αkα _k+1 . . . α _k+6 is the destination terminal bit designation pattern of the destination terminal designation section 4. The destination terminal that you want to be the broadcast destination
Bit αi of Ti is set to “1”. The reason why "0" is inserted every 8 bits in this bit designation pattern is to avoid confusion with the end character +. Furthermore, the four "0"s after the final bit αn in the bit designation pattern are dummy bits for creating 8-bit units.

FIG. 4 shows an embodiment of the broadcast communication terminal control device according to the present invention, in which the terminal control device 21 includes the operation panel 22 and the broadcast communication signal transmission circuit 2 shown in FIG.
3. Broadcast communication signal receiving circuit 24, call control circuit 2
The control device 21 and the terminal device 26 are connected to each other. The terminal control device 21 controls the communication between the terminal device 26 and other terminals, and transmits and receives signals in accordance with the connection sequence shown in FIG. 5 in broadcast communication. .

In FIG. 5, between the exchange 30, the originating terminal 31, and the terminating terminal 32, the originating terminal 31 first presses the pushbutton switch 307 to send a call signal 40, and when it receives the dial ready signal 41 from the exchange 30 that received this, it makes the call. The terminal 31 confirms this with the lamp 305 and transmits the selection signal 42 set by the operation unit 22 from the transmission circuit 23. The exchange 30 sends a paging signal 43 to each destination terminal 32 specified by the selection signal 42, and receives a response signal 4 from the destination terminal 32.
4, it sends a response status notification signal 45 to the originating terminal 31. In the originating terminal 31, the receiving circuit 24 receives the response status notification signal 45, and the transmitting circuit 23 sends a path connection instruction signal 46 to the exchange 30. The exchange 30 sets up a path, sends a communication enable signal 47 to the originating terminal 31, receives this, and sends communication data from the terminal device 26. When the destination terminal 32 receives this, a data reception status notification signal 49 is sent to the exchange 32.
The exchange 30 further sends this to the originating terminal 31. When the data transmission is finished, the originating terminal 31 transmits a disconnection signal 50, and when the destination terminal 32 receives this, it transmits a disconnection confirmation signal 51 to the exchange 30. The exchange 30 receives this and sends a disconnection confirmation display signal 52 to the originating terminal 31, which is received by the receiving circuit 24.

The receiving circuit 24 receives a response status notification signal 45 and a data reception status notification signal 4 transmitted from the exchange 30.
9. Receive the disconnection confirmation signal 52 and display the received function setting section 3 on the signal type display section 303 of the operation section 22;
The terminal designation section 4 is displayed on the display lamp 302. In broadcast communication, the call control circuit 25 transmits and receives control signals other than broadcast communication signals using the signal format shown in FIG. 2 according to the connection sequence shown in FIG. The terminal device 26 and the exchange 30 are connected, and signals are transmitted and received in one-to-one communication.

Next, a circuit for transmitting and receiving a signal using a flag signal as the synchronization signal 2 will be explained. 6 and 7 are specific circuit configuration examples of the transmitting circuit 23 and the receiving circuit 24 shown in FIG. 4, respectively, and in FIG.
The selector 402 selects one of the holding register 400 that holds the code of the switch 400 and the holding register 401 that holds the ON/OFF status of the pushbutton switch 301, and the contents of the selected register are input to the shift register 403, and the 8-bit The bit string is output one bit at a time. Five consecutive “1”s in the bit string from shift register 403
When detected by the "0" insertion circuit 404, "0" is inserted and sent to the exchange via the OR circuit 405 and the AND circuit 406. 3-bit octal counter 4
07 and 408 are connected in cascade, and the selector 409 selects the counter 408 or "0" and selects the counter 408 or "0".
02 as a control signal. The number specified by the number of transmission bits designation section 411 is added with "16" in the addition circuit 412, and then "8" is added in the addition circuit 413.
is added. The matcher circuit 414 is the adder circuit 4
The added value of 13 is compared with the count contents of the counters 407 and 408, and the flip-flop 415 is reset when a match is output. The matcher circuit 416 outputs the added value of the adder circuit 412 and the counters 407, 40.
8 is compared, and if the two match, the flip-flop 417 is reset. Flip-flops 415 and 417 are set by a signal indicating that push button switch 306 for instructing broadcast transmission has been pressed. AND circuit 419 is opened by the set output of flip-flop 415, and terminal 4 is opened.
The second clock of 21 passes through an AND circuit 419 and is supplied to a shift register 403 and a counter 407. A broadcast communication signal transmission enable signal is applied to AND circuit 406 through terminal 422. Delay flip-flops 423, 4 operated by the first clock
24, a delay flip-flop 425 is provided which operates on the second clock. Further, a flag pattern setting section 426 for the synchronization signal section 2 is provided, and the flag pattern can also be selected by the selector 402. The signal that turns on the push button switch 6 indicating broadcast communication and the overflow output of the counter 407 are passed through an OR circuit 427 and then through a delay flip-flop 423 to a shift register 403.
and sets the output of selector 402 to shift register 403. flipflop 41
The outputs of 5 are delay flip-flops 424, 425.
The reason why the signal is supplied to the OR circuit 405 through the terminal 422 is to continue sending a high level so that the connection with the exchange will not be disconnected when the terminal 422 is at a high level.

In FIG. 7, the function setting section 3 of the broadcast communication signal received from the exchange is held in a holding register 500, and the terminal specifying section 4 is held in a holding register 501. Either of these holding registers 500, 501 is selected by distribution circuit 502, and the contents of shift register 503 are output to the selected holding register. Bit information input one bit at a time from the synchronization detection circuit 504 to the shift register 503 is assembled into an 8-bit string by the shift register 503. A synchronization detection circuit 504 detects a flag synchronization signal from a control signal from an exchange through a gate 505, and deletes "0" following five consecutive "1" bits upon data reception after detecting flag synchronization. Flag synchronization detection output is prohibited gate 506
through gate 508 and flip-flop 507 through gate 508.
Reset. The set output of flip-flop 507 opens gate 509, and gate 5
A second clock is supplied from a terminal 511 to a shift register 503 and a 3-bit counter 512 through 09. A 3-bit counter 513 is connected in cascade to a 3-bit counter 512, and the count contents of the counter 513 are decoded by a decoder 514. One of registers 500 and 501 is selected by the output of decoder 514. The contents of counter 513 are given to distribution circuit 502 as a control signal. A delay flip-flop 515 is provided which operates from the first clock. Gate 505 is opened by a broadcast communication signal reception enable signal from terminal 516.

In the transmitting circuit shown in FIG. 6, signals input through the numeric keypad 304 and push button switch 301 are held in holding registers 400 and 401, and when the push button switch 306 for transmitting broadcast communication signals is turned on, the flip-flop is activated to start transmission. 415 is set, the second clock is input to the shift register 403 and counter 407 through the AND circuit 419, and transmission is started. At this time, the counter 407,4
08 has become “0”, so selector 40
2 selects the flag pattern of the setting circuit 426. Therefore, the flag pattern is first input to the shift register 403, and the flag pattern is input to the shift register 403, and the flag pattern is input to the shift register 403, and then the flag pattern is
The bits are transmitted via circuits 405 and 406 to the exchange. When 8 bits are sent, the counter 40
7 overflows, and this overflow signal increments the counter 408 by "+1", so the content becomes "1", and the holding register 400 becomes the selector 4.
02, and the function setting section 3 is input to the shift register. Similarly, holding registers 401 are sequentially selected and their contents are sequentially transmitted. The number of transmission bits is specified in the transmission bit number designation section 411, which means the number of registered destination terminals, and can be changed by changing the jumper wiring or by using a switch. “16” for this specified number of transmitted bits.
and “24” added value and counter 407, 40
The count value of 8 is constantly compared in matcher circuits 416 and 414, and when they match, a match signal is output. The flip-flop 417 is reset by the match with the value added "16", the selector 409 selects "0", the selector 402 selects the flag pattern again, and when the 8 bits of the flag pattern are transmitted, the matcher circuit 414 This match signal causes the flip-flop 41 to start transmitting.
5 is reset and the transmission ends. “0” again
Except for flag transmission, when the insertion control circuit 404 detects 5 consecutive "1" bits, it inserts one "0" bit and controls the AND circuit 419 to inhibit clock input to the shift register 403 by one bit. . In addition, for transmission, terminal 42
2 is inputted with “1” by the call control circuit 25.

Upon reception, "1" is input to terminal 516 by call control circuit 25, as shown in FIG. A control signal is input from the exchange to the synchronization detection circuit 504 through the gate 505. When the synchronization detection circuit 504 detects a flag pattern, it sets a control flip-flop 507 for starting reception and outputs the signal from the exchange to the shift register 503. Shift register 503 shifts the input signal bit by bit according to the clock to assemble an 8-bit string. When 8 bits are received, the counter 512 overflows, and this overflow signal causes the counter 512 to overflow.
The contents of the shift register 503 are stored in the holding register 50
It is output as either 0 or 501. Holding registers 500 and 501 are selected by controlling distribution circuit 502 by the output of counter 513. That is, the first 8 bits are set in holding register 500. The counter 513 is incremented by "1" in response to the overflow signal of the counter 512. Therefore, each time 8 bits are received, the holding registers 500 and 501 are sequentially selected and the received signal is set. When the synchronization detection circuit 504 detects the flag pattern again, the control flip-flop 507 for starting reception is reset, and reception is stopped. In addition, the synchronization detection circuit 504 detects 5 consecutive "1" bits during signal reception.
When this is detected, the gate 509 is then controlled to inhibit clock input to the shift register 503 by one bit in order to delete "0".

In this embodiment, the display lamp 302 of the operation panel 22 is explained as being one for each destination terminal, but it is also possible to provide a plurality of display lamps and display the display lamp by selecting it using the function setting section 3 received from the exchange. . Furthermore, part or all of the transmitting circuit 23, receiving circuit 24, and call control circuit 25 can be realized by program control using a microprocessor or the like.

Next, an explanation will be given of an exchange that accommodates the terminals that transmit and receive the control signals described above. When the control signal in the format shown in Figure 2 sent from the originating terminal is received by the exchange, the exchange determines the destination terminal address corresponding to "1" in the bit designation pattern of the destination terminal designation section 4 of the control signal. Obtained by conversion table. In other words, as shown in Figure 8, the exchange has the following information for each originating terminal j:
Each bit position α ₁ ...αn of the destination terminal designation section 4 is provided with bits β ₁ ...βn in which the destination terminal address DA ₁ ...DAn is stored. A terminal address translation table is provided. The destination terminal address DA ₁ .

FIG. 9 shows an embodiment of an exchange for a broadcast communication signaling device, in which incoming lines 6a . This multiplexed signal on the incoming highway 7 is switched by a switching network, for example a one-stage time switch 8, so that one time slot in the incoming highway 7 is switched to one or more time slots in the outgoing highway 9, and the multiplexed signal is transferred to the outgoing highway. 9
The multiplexed signal is supplied to a demultiplexing circuit 11 through an insertion circuit 10. The multiplexing/demultiplexing circuit 11 multiplexes and demultiplexes the time-division multiplexed signal and separates it into outgoing lines 11a...11m to which each destination terminal is connected.

The inbound highway signal is branched to the signal device 20.
A line number LMN (for example, a line memory number) indicating the channel of the input signal from the switching network 8 is supplied to the signal receiving circuit 12, and the signal is controlled for each channel. The signals are separated and stored in the general signal receiving buffer 15. This buffer 15 is read out by the central processing unit 18, and various processes are performed according to the control signal. Central processing unit 1
8 also prepares various control signals, and the signal transmission circuit 1
3, the signal transmitting circuit 13 inserts a control signal in correspondence with the signal indicating the channel from the switching network 8, and the inserting circuit 10 inserts the control signal into the corresponding output highway. These operations are similar to the operations of conventional broadcast communication devices of this type in exchanges.

A bit position destination terminal address conversion table 17 is provided within the signaling device 20. As described with reference to FIG. 8, this conversion table 17 is provided for each originating terminal j, and contains bits β ₁ ...βn indicating the presence or absence of a connection request for each terminating terminal and the address of each terminating terminal.
DA ₁ ...DAn is stored. In order to store the bit patterns α ₁ ...αn in the control signal from the originating terminal in each bit β ₁ ...βn of this conversion table 17, the signal receiving circuit 12 uses the line number of the originating terminal.
LMN and bit patterns are stored in a bit pattern receiving buffer 14.

First, a specific example of the signal receiving circuit 12 is used in a synchronous transmission method using the SYN character.
Shown in Figure 0. The signal receiving circuit 12 has the same basic configuration as a known synchronizing signal receiving circuit. Intermediate calculation results and control information for the line are stored in the reception line memory 206
The line number LMN from the switching network 8 (FIG. 9) is specified and held. The synchronization character SYN in the control signal from the input highway 7 (FIG. 9) is detected by the synchronization character position detection circuit 207, and the synchronization state determination circuit 20
8. Parallel shifter 211 and the like are provided in the same manner as in the prior art. In order to identify the broadcast signal and generate the sequence number SQN of the bit pattern related to the one-shot terminal, a pattern detection circuit 201 connected to the parallel shifter 211, selectors 203 and 204 of part of the shift number counting circuit 202, and an addition circuit are connected to the parallel shifter 211. 205
is newly added.

When the control signal is input to the exchange, the signal receiving circuit 12 detects the position of the synchronous character SYN in the synchronous character position detection circuit 207 according to a well-known procedure, and 8-bit assembly is sequentially performed in accordance with this position detection information. Since the 8 bits assembled immediately after the SYN character are a function setting code as shown in FIG. 2, the function is detected by the pattern detection circuit 201. The pattern detection circuit 201 is the third
Each code in the figure is an input address, and when that address is accessed, a specific output bit is set to “1”.
This can be easily realized by using a so-called memory conversion circuit that outputs . The detection information of the pattern detection circuit 201 is passed through the shift number counting circuit 202 which determines whether a signal is being received or not, and its output signal F is set to "1". This signal causes selector 2
04, the 1 side is selected and the AND gate 213 outputs "1", and information MD=1 indicating that it is broadcast selection information is set in the line memory 206. Further, the broadcast selection signal reception information F=1 is notified to the central processing unit 18 via the buffer 15.
The 8-bit unit information assembled thereafter is a destination terminal designation bit, and MD=1 is held until the end code + is detected. The 8-bit information includes a line memory 206, a +1 addition circuit 205,
The sequence number is set to 1 by the operation of the selector 203.
Add this and the line number of the originating terminal T ₀ in order.
LMN=l is loaded into the bit pattern receiving buffer 14. At this time, the bit pattern BITPTN for each 8 bits is also written into the bit pattern receiving buffer 14 via the parallel shifter 211 and selector 210. When the end code + is similarly detected by the pattern detection circuit 201, the shift number counting circuit 2
Output signal G=1 is output via 02, “0” is selected by selector 204, and broadcast selection information MD=
It becomes 0. As a result, the addition of the sequence number SQN is stopped (cleared to 0), and the loading of the bit pattern into the buffer 14 is also stopped. Further, the end code+detection information G=1 is notified to the central processing unit 18 via the buffer 15.

The data loaded into the buffer 14 is sequentially set in the destination terminal designation section β ₁ . . . βn of the conversion table 17. Bit position - destination terminal address conversion table 1
7 and its surroundings are configured as shown in FIG. 11, for example. The destination terminal designation bit βi is stored in memory circuit 1.
01, and the destination terminal address DAi is stored in the storage circuit 102. The address for the storage circuit 102 is applied from the central processing unit 18 to the register 108 through line 121, the write data is applied to the register 106 through line 122, and the read data from the storage circuit 102 is applied to the register 108 through line 121.
From 07 to central processing unit 18 through line 123
sent to. Reading and writing control for the memory circuits 101 and 102 is carried out by the central processing unit 18 via line 124.
It is done through. A portion of the address on line 121 is supplied to decoders 109 and 110, respectively, and their decoded outputs are used to store circuits 102 and 1.
Chip selection for 01 is performed. However, when writing to the memory circuit 102, the output of the decoder 110 is prohibited, and only reading is performed in the memory circuits 101 and 102 at the same time.

The sequence number SQN from the bit pattern reception buffer 14 is decoded by the decoder 103,
Chip selection of the memory circuit 101 is performed using the output. Bit pattern BITPTN from buffer 14
is input to the storage circuit 101 through the register 105. The line number LMN from the buffer 14 is converted into an address in the storage circuit 101 in the table 104. For example, if the line number of the originating terminal _T0 is l, l is converted to 0. The output of this table 104 provides an address for each originating terminal to the storage circuit 101. Conversion table data for table 104 is provided from central processing unit 18 via line 125.

Each word of the memory circuit 101 is converted into a conversion table 17.
It corresponds to the table number of the memory circuit 101.
The number of terminals corresponds to the number of registered terminals. Therefore, as the memory circuit 101, for example, a 1-bit×N word memory chip having a number of words N greater than the number of accommodated calling terminals may be used. Further, the number may be M (a multiple of 7 in this embodiment) which is greater than the number of destination terminals that are allowed to be registered in the broadcast connection. The word and bit directions of the memory circuit 102 correspond to the word and bit directions of the conversion table 17, respectively, and if the destination terminal address bit length is K bits, a memory of K bits×M words may be used.
This can be constructed from a combination of 1 bit x M word memory chips.

The memory circuit 101 operates with the same chip select signal in units of seven chips as one group, and this unit is the bit pattern loading unit 0αkα _k+1 of the buffer 14.
...corresponds to α _k+6 . Also, the address to the memory circuit 101 is the table number j of the conversion table 17.
It corresponds to If the sequence number SQN of data from buffer 14 is “1”, memory circuit 1
A chip select signal for the first group of 01 is output from the decoder 103. At the same time, the line number LMN=l of the originating terminal T ₀ converts the conversion table 1 into
04 to table number “0” of conversion table 17
is output and becomes the address input of the memory circuit 101. As a result of the above _, the bit pattern 0α ₁ α ₂ . This means that α ₁ α _{2 .} . . α ₇ are set in the destination terminal designation bits β ₁ β ₂ .

After that, data 0α ₈ α ₉ ...α ₁₄ ,
0α ₁₅ α _{16 . . . α 21 , .} Therefore, in the conversion table 17, bit patterns α ₁ ...αn are set to bits β ₁ ...βn.

After detecting the end code +, the central processing unit 18 sequentially reads the conversion table 17 starting from address 0 and calculates βi=
By detecting i equal to 1, it can be known that a broadcast connection request has been made to terminal Ti, and
The terminal address of Ti can also be easily obtained as DAi read at the same time.

Similarly, for control signals from terminals other than broadcast selection signals, such as path connection instruction signals (see FIG. 3), their functions are detected by the signal receiving circuit 12 and notified to the central processing unit 18, as well as to the conversion table. Bits 17 are set in accordance with the destination terminal, making it easy to specify which destination terminal a broadcast path connection (passage connection) is to be made.

Regarding transmission of the control signal, the control signal is formed by the central processing unit 18, set in the signal transmission circuit 13 similar to the conventional one, and sent to the originating terminal.
The amount of signals set in the signal transmitting circuit 13 can be extremely small compared to the case where signals are sent to each destination terminal individually.

Above, we have explained the character synchronous transmission method using the SYN character for switching equipment.
Of course, the present invention can also be similarly applied to a frame transmission system that uses flags to achieve frame synchronization. In this case, the format of the control signal is F00000010α ₁ α ₂
...It becomes αnF. Here, F=01111110 is a flag, 00000010 is a function setting code, α ₁ α ₂ ...αn
is the destination terminal designation bit. α ₁ α ₂ ...For αn, in order to avoid confusion with flag F, a "0" is inserted after five consecutive "1"s, so-called "0"
The insertion operation is performed by the signal transmitting circuit, and the inserted "0" is deleted by the signal receiving circuit. It is necessary to perform a so-called "0" deletion operation. If a known frame signal receiving circuit that detects flags and deletes "0" and a known frame signal transmitting circuit that inserts "0" are provided in place of the signal receiving circuit 12 and signal transmitting circuit 13 in FIG. 8, the conversion table can be created. 17 can be configured in exactly the same way as a broadcast communication signal device in the case of a frame transmission system. In this case, as in the embodiment of the character synchronous transmission method, the memory circuit 1
There is no need to group 01 in units of seven, and any number of groups can be easily realized.

As explained above, by transmitting and receiving signals for broadcast communication between the exchange and the originating terminal using the operation panel shown in FIG. 1 and the control signals in the format shown in FIG. The terminal control device has the ease of operation of the operation panel as shown in FIG. 1, that is, any destination terminal can be specified with a simple operation using a one-touch button, and is configured with a simple transmitting circuit and a receiving circuit, thereby realizing an inexpensive terminal control device. Furthermore, since the destination terminal can be specified with a 1-bit signal per destination terminal, the signal length is shortened, the processing at the exchange is reduced, and there is an advantage that the status of the destination terminal and the signal from the destination terminal can be notified from the exchange.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the operation panel in the terminal control device according to the present invention, FIG. 2 is a diagram showing the format of the broadcast communication signal used in the present invention, and FIG. 3 is the code of the function setting section of FIG. 2. 4 is a diagram showing an example of the configuration of a terminal control device according to the present invention, FIG. 5 is a diagram showing an example of a connection sequence for broadcast communication, and FIG. 6 is a diagram showing an example of the connection sequence of broadcast communication. FIG. 7 is a diagram showing an embodiment of the transmitting circuit, FIG. 7 is a diagram showing an embodiment of the receiving circuit in FIG. 4, and FIG. 8 is a diagram showing the bit position -
FIG. 9 is a block diagram showing the configuration of an exchange for the broadcast communication terminal control device of the present invention, and FIG. 10 is a diagram showing the logical configuration of the destination terminal address conversion table. FIG. FIG. 11 is a diagram illustrating the configuration of the buffer and the configuration of the bit position to destination terminal address conversion table and its surroundings. 301: Push button switch for specifying destination terminal, 302:
Display lamp for displaying destination terminal, 303: Signal type display section, 304: Numeric keypad, 305: Dial enable signal display lamp, 306: Push button switch for instructing broadcast communication signal transmission, 307: Push button switch for calling, 30
8: Push button switch for disconnecting calls, 2: Synchronization signal section,
3: Function setting section, 4: Destination terminal specification section, 5: End signal section, 21: Terminal control device, 22: Operation panel, 2
3: Transmitting circuit, 24: Receiving circuit, 25: Call control circuit, 26: Terminal device, 30: Exchange, 31: Originating terminal, 32: Terminating terminal, 40: Calling signal, 41: Dial ready signal, 42: Selection signal, 43: calling signal, 44: response signal, 45: response status notification signal,
46: Path connection instruction signal, 47: Communication available signal, 4
8: communication data, 49: data reception status notification signal, 50: disconnection signal, 51: disconnection confirmation signal, 5
2: Disconnection confirmation display signal, 400, 500: Function setting section holding register, 401, 501: Terminal specification section holding register, 402: Selector, 403, 50
3: Shift register, 407: "0" insertion control circuit, 407, 408, 512, 513: Counter, 409: 2-1 selector, 411: Transmission bit number designation section, 412: "16" addition circuit, 413:
"8" adder circuit, 414, 416: matcher circuit,
502: Distribution circuit, 504: Synchronization detection circuit, 51
4: Decoder, 422: Broadcast communication signal transmission enable signal terminal, 516: Broadcast communication signal reception enable signal terminal.

Claims (1)

[Claims] 1 A circuit that generates a synchronization signal, a circuit that holds function specification information that specifies the type of control information, and a circuit that holds terminal specification information that corresponds one-to-one to multiple terminals and specifies the multiple terminals using bit information. a transmission circuit consisting of a circuit for transmitting the synchronization signal, the function designation information and the terminal designation information one bit at a time, a circuit for detecting the synchronization signal transmitted from the exchange, and a circuit for detecting the synchronization signal based on the detection of the synchronization signal. , a receiving circuit consisting of a circuit that sequentially receives the subsequent function designation information and terminal designation information, and a circuit that distributes and holds the received function designation information and terminal designation information; It is equipped with a display setting circuit that sets and displays these, a function setting section that indicates the type of control information, and a terminal specifying section that specifies the destination terminal as one-bit compatible, and transmits broadcast communication signals between the terminal and the exchange. A broadcast communication terminal control device characterized by transmitting and receiving data.