JPS6326626B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DC converter, that is, a DC-DC converter that can prevent saturation of a transformer.

To explain a conventional transistor converter with reference to FIG. 1, a primary winding 3 of an output transformer 2 is connected to a DC power supply 1, a transistor 4 is connected in series to this primary winding 3 as a switching element, A rectifier circuit 7 consisting of a rectifier diode 6 is connected to the secondary winding 5 of the transformer 2, and a load 12 is connected to the output stage of the rectifier circuit 7 via a smoothing circuit 11 consisting of a diode 8, a reactor 9, and a capacitor 10. is connected. 13 is a control circuit for the transistor 4 for controlling the DC output voltage to be constant. This circuit 13 includes an error amplifier circuit 15 for obtaining an error output voltage between the output voltage and the reference voltage of the reference voltage source 14, a voltage corresponding to the load current I _L detected by the current detector 16, and a reference voltage. and an error amplification circuit 18 that compares the overcurrent level provided by the power supply 17 with a corresponding reference voltage. The output of one error amplification circuit 15 and the output of the other error amplification circuit 18 are added via diodes 19 and 20 and become an input to a first voltage comparator 21. This input is compared in a comparator 21 with a sawtooth wave generated from a sawtooth wave generation circuit 22. Note that the sawtooth wave generation circuit 22 generates a sawtooth wave having the same cycle as the on/off cycle of the transistor 4. The second voltage comparator 24 compares the sawtooth wave generated from the sawtooth wave generation circuit 22 with a reference voltage for determining the maximum duty factor supplied from the reference voltage source 23, and determines the maximum allowable duty factor, that is, the maximum allowable pulse width. Then, the output of the first voltage comparator 21 passes through the AND gate 25 for a period of time permitted by the output of the second voltage comparator 24. AND gate 25
A transistor drive circuit 26 is provided at the output of the AND gate 25, and a base drive signal corresponding to the output of the AND gate 25 is applied to the transistor 4. A resistor 28 connected in parallel to the transformer primary winding 3 via a rectifier diode 27 is used to reset the transformer 3, and a capacitor 29 connected in parallel to this resistor 28 is used to remove spike voltages.

When the transistor 4 of the converter configured in this way is turned on during the period _t1 to _t2 in FIG. 2, the voltage of the power supply 1 is applied to the primary winding 3, and the corresponding voltage is applied to the secondary winding. 5 and is supplied to the load 12 via the rectifier circuit 7 and the smoothing circuit 11. Second
In the figure, when the base drive signal of transistor 4 disappears and transistor 4 turns off at time t ₂ , the energy stored in transformer 2 during the on period of transistor 4 is transferred to primary winding 3 and rectifier diode 2.
7 and a resistor 28, and the second
The increase in collector-emitter voltage V _BE of transistor 4 shown in Figure A is limited, and the transformer 2
is magnetically reset. The generation period of the reset voltage V _R during the off period of the transistor 4 is from t ₂ to
_t3 , and after the transformer 2 is reset by voltage application during this period, the voltage V _S of the power supply 1 is applied to the transistor 4.

By the way, when the fluctuation of the load current I _L is small, the transformer 2 is reset every cycle, so saturation of the transformer 2 does not occur, but the load current
When I _L suddenly changes from a small state to a large state,
It becomes impossible to obtain sufficient reset voltage,
The transformer 2 becomes saturated and the collector current I _C of the transistor 4 increases, causing destruction or deterioration of the transistor 4. That is, the load current I _L shown in FIG. 2D
During the period t ₄ to _{t 9} when _t
VR will also be lower. Therefore, the charging voltage of the capacitor 29 naturally becomes low. Next, after _t9 , when the on-time of the transistor 4 becomes longer as shown in _t9 to _t10 due to the increase in the load current _IL , a high voltage is required to reset the transformer 2.
A relatively large amount of energy is stored in the transformer 2 during the time period t ₉ to t ₁₀ , but since the spike voltage removal capacitor 29 is provided, the energy stored in the transformer 2 when it is on is used as a reset voltage as it is. Instead, it is used to charge the capacitor 29, and the reset voltage gradually increases. Therefore, the voltage that resets the transformer 2 during the off period from t ₁₀ to _{t 11} becomes lower than the full-load reset voltage level V _A corresponding to the collector current I _C at this time,
It becomes impossible to reset transformer 2. Therefore, as is clear from the B-H curve shown in Figure 2C,
In the interval from t ₉ to _{t 12} , it is impossible for the B-H curve to return to its original state, and in the next cycle after t ₁₁ , the operation starts from a state where it is not reset, transformer 2 becomes saturated, and as shown in Fig. 2B. The collector current I _C of transistor 4 becomes excessive. For this reason, in the past, a transistor 4 with a large power capacity was used to prevent destruction or deterioration of the transistor 4, or the magnetic flux density of the transformer 2 was designed to be low. Therefore, the device has become large and expensive.

In order to solve the drawbacks of the method shown in FIG. 1, the inventor of the present application proposed the method shown in FIG. This third
The circuit shown in the figure is the circuit shown in FIG. 1 with a capacitor charging power supply circuit 30 added thereto. That is, separate power supply 3
1 and a rectifying diode 32 for blocking reverse current are connected in parallel to a capacitor 29. The power supply 31 is configured to be a separate power supply from the DC power supply 1 of the main circuit, and supplies the capacitor 29 with a voltage V _RM approximately equal to the reset voltage level V _A required when the full load current I _LM flows.

In the device provided with the charging power supply circuit 30 as described above, the load current I _L decreases in the period _from t ₅ to _{t 9} as shown in FIG. When _L becomes the full load current I _LM , the collector current I _C becomes small during the on period from t ₆ to t ₇ , and from t ₇ to _{t 8}
Naturally, the flyback voltage during the off-period is also low. Therefore, the diode 27 is turned off, and the sum of the voltage V _S of the DC power supply 1 and the voltage of the transformer 2 is applied to the transistor 4. Even if the flyback voltage during the period _t7 to _t8 is low, since the capacitor 29 is charged with the voltage _VRM by the separate power supply 31, the charging voltage does not drop as in the conventional circuit shown in FIG. If the collector current I _C increases during the on period from t ₉ to t ₁₀ , the corresponding flyback voltage increases from t ₁₀ to t 10 .
Occurs at _t11 , diode 27 turns on and becomes the reset voltage. At this time, since the capacitor 29 has been charged to the voltage _VRM in advance, a situation in which the flyback voltage is absorbed by the capacitor 29 and becomes impossible to reset does not occur. Therefore, saturation of the transformer 2 is prevented and excessive collector current is limited. Note that the reset voltage is clamped to the voltage _VRM of the separate power supply 31, and _VCE is also clamped.

By the way, in the circuits of FIGS. 1 and 3,
Resetting is not possible unless the energy stored in the transformer 2 while the transistor 4 is on is released during the off period. The energy stored during the on-period of transistor 4 varies depending on the input voltage V _S , collector current I _C , and pulse width, that is, on-time T _ON ; in the circuit shown in Figure 1, when the input voltage V _S is high, The reset voltage also increases. However, during the off-time of transistor 4, the input voltage V _S
A voltage V _S +V _R , which is the sum of the voltage V S and the reset voltage V _R , is applied between the collector and emitter, and when the input voltage is high, a considerably large voltage is applied to the transistor 4. Therefore, it is required to use a transistor 4 with high breakdown voltage. On the other hand, in the circuit shown in FIG. 3, the reset voltage is set by the voltage V _RM of the separate power supply 31.
Since V _R is clamped, the voltage applied to the transistor 4 is limited, and the withstand voltage of the transistor 4 can be lowered. However, in the case of a load short circuit or a sudden load increase, the transformer 2 may become saturated. That is, in conventional circuits, the duty factor is set to a relatively large fixed value, such as 50%, so that a predetermined output voltage can be obtained even when the input voltage is low. In this way, when a load short circuit occurs in a state where the duty factor is large and the input voltage V _S is high, the output voltage first decreases, so the pulse width is widened to reach the maximum pulse width (maximum duty factor). Although an error amplification circuit 18 for overcurrent detection is provided, there is generally a delay in response, so the pulse width cannot be narrowed immediately. When the maximum pulse width is reached and the input voltage V _S is high, the energy stored in the transformer 2 also becomes large, and a large reset voltage is required. but,
If the reset voltage is limited in relation to the withstand voltage of the transistor 4, a sufficient reset voltage cannot be obtained and the transformer 2 may become saturated.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a DC converter in which a transformer does not become saturated even if the load suddenly increases under high input voltage conditions.

To achieve the above object, the present invention includes a transformer having a primary winding and a secondary winding, a switching element connected in series to the primary winding, and a switching element connected in series to the primary winding.
a DC power supply connected to a series circuit of the secondary winding and the switching element, a rectifier circuit connected to the secondary winding, and a resistor connected in parallel to the primary winding via a rectifier diode; The maximum allowable duty factor is changed at least in the vicinity of the maximum value of the input voltage of the primary winding so as to be substantially inversely proportional to the input voltage, and the switching element receives an on/off control signal having a duty factor within the range of the maximum allowable duty factor. The present invention relates to a DC converter comprising a switching element control circuit that supplies a switching element to a DC converter.

According to the present invention, the maximum allowable duty factor, ie, the maximum allowable pulse width, is changed in inverse proportion to the input voltage, so that the maximum allowable duty factor, ie, the maximum allowable pulse width, is kept narrow when the input voltage is high. Therefore, even if a load short circuit occurs when the input voltage is high and the output voltage drops and the pulse width is widened to the maximum allowable pulse width, the maximum allowable pulse width will be narrowed in response to the high input voltage. This not only limits the energy stored during the on-time T _ON of the switching element, but also lengthens the off-time T _OFF of the switching element, lengthening the reset time during which the reset voltage is applied. Therefore, even if the reset voltage is limited due to the withstand voltage of the switching element,
The long reset time allows the transformer to reset and prevents transformer saturation.

Embodiments of the present invention will be described below with reference to FIGS. 5 to 8. However, in Fig. 5, the numbers 1 to 32
Components indicated by are substantially the same as those indicated by the same reference numerals in FIGS. 1 and 3, so their explanation will be omitted.

In the DC converter shown in Figure 5, the input voltage V _S
In order to change the reference voltage of the comparator 24 according to the input voltage, an input voltage detection circuit 33 is _provided. and _R2 at a voltage dividing point 34. Note that the input voltage detection circuit 33 is connected to the transformer 2.
A tertiary winding 35 and a rectifier diode 36 provided in
, a smoothing capacitor 37, and a resistor 38.

The input voltage detection circuit 33 obtains the input voltage V _S , that is, the DC voltage corresponding to the voltage supplied to the transformer 2 from the power supply 1, and the potential at the voltage dividing point 34 in the reference voltage source 23 responds to the input voltage. and change.
In the comparator 24 for determining the maximum allowable pulse width, the sixth pulse width obtained from the sawtooth wave generation circuit 22 is
The sawtooth wave 39 and the maximum pulse width determining reference voltage supplied from the reference voltage source 23 shown in FIGS.
V _MAX is compared to generate the maximum allowable pulse width control signal shown at C in FIGS. 6 and 7. FIG. 6 shows the state when the input voltage V _S is low, and FIG. 7 shows the state when the input voltage V _S is high. Therefore,
As is clear from the comparison between Figure 6C and Figure 7C,
The maximum allowable pulse width T _MAX becomes narrower as the input voltage V _S becomes higher.

The output voltage control comparator 21 compares the sawtooth wave 39 with the error output voltage V _E as shown in A in FIGS. 6 and 7, and calculates the pulse width T _C as shown in B in FIGS. generates control pulses.
In the states shown in FIGS. 6 and 7, since T _C is narrower than T _MAX , the pulse B is directly sent to the output of the AND gate 25 as shown in D in FIGS. 6 and 7, and the transistor 4 It operates on and off in response to the pulse D in FIG. 6 or FIG. 7. V _CE of transistor 4 changes as shown by E in Figure 6 or 7, and even if the reset voltage V _RM is constant, if the input voltage _VS is high, V _CE becomes high during the off period. .

FIG. 8 shows a state in which the current I _L of the load 12 suddenly increases while the input voltage V _S is high as shown in FIG. If the load is light until time t ₃ and a load short circuit occurs at time _{t 3} , the output voltage will decrease and the output voltage will increase, resulting in the tolerance shown in FIG. 8C determined by the second comparator 24. Maximum pulse width
The width of the output pulse of the first comparator 21 increases until T _MAX , and the collector current I _C flows during the period t ₄ to t ₅ as shown in FIG. 8B. At this time, since the allowable maximum pulse width T _MAX is narrowed by the high input voltage as explained in FIG. 7, the energy stored in the transformer 2 during the on-time T _ON of the transistor 4 decreases. Furthermore, as the on time T _ON becomes shorter, the off time T _OFF becomes longer, so that the transformer 2 can be reset reliably. Since the circuit shown in FIG. 5 is provided with an overcurrent limiting circuit, a control output is generated from the overcurrent detection error amplification circuit 18 after a predetermined response delay, and this control output is transmitted to the voltage detection error amplification circuit 15. , the diode 20 turns on and the output pulse width of the comparator 21 becomes narrower, as shown in FIG.
As shown in the period t ₈ to _{t 9} , the on time of the transistor 4 becomes narrow. If the maximum allowable pulse width is fixed as shown in Figure 6C, which is set so that a predetermined output voltage can be obtained with a low input voltage, a load short circuit will occur at a high input voltage. When the output voltage decreases, the on-time T _ON increases to the maximum allowable pulse width T _MAX as shown in FIG. 6C, making it impossible to reset the transformer 2.

When the input voltage V _S becomes lower than a certain value, the Zener diode 40 turns off and the reference voltage source 2
The reference voltage sent from 3 no longer follows the input voltage V _S , and becomes a fixed reference voltage obtained by dividing the voltage +V between resistors R ₁ and R ₂ . Therefore the input voltage
When V _S is low, the maximum allowable pulse width T _MAX does not become too large and cannot be reset.

As is clear from the above, according to this example,
Since saturation of the transformer 2 can be prevented and the reset voltage can be lowered, it is possible to downsize the transformer 2 and lower the withstand voltage of the transistor 4. Therefore, it is possible to downsize the device and reduce costs.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto and can be further modified. For example, in the embodiment, the separate power supply 31 is configured separately from the DC power supply 1 in order to prevent fluctuations in the reset voltage, but a common power supply system may be used. Further, in order to keep the reset voltage constant, the charging power supply circuit 30 may include a voltage regulating circuit.
Further, a control circuit 1 that drives and controls the transistor 4
3 is a separately excited system, but the voltage of the transformer 2 may be fed back to the base of the transistor 4 to drive the transistor 4 using a self-exciting system. Also, input voltage is changed to transformer 2
It may also be detected independently without using. Separate power supply 31
The voltage may be set slightly higher than the reset voltage required at full load.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional transistor converter, Fig. 2 is a waveform diagram showing the states of each part of Fig. 1, Fig. 3 is a circuit diagram showing a conventional improved converter, and Fig. 4 is a circuit diagram showing the state of each part of Fig. FIG. 5 is a circuit diagram showing the DC converter according to the embodiment of the present invention. FIG. 6 is a waveform diagram showing the states of each part in the figure. FIG. 6 shows the states of points A to E in FIG. 5 when the input voltage is low. Figure 7 is a waveform diagram showing the states of points A to E in Figure 5 when the input voltage is high, and Figure 8 is the waveform diagram showing the state of points A to E in Figure 5 when _the input voltage is high _. , is a waveform diagram showing the maximum allowable pulse width. In the symbols used in the drawings, 1 is a DC power supply, 2 is a transformer, 3 is a primary winding, 4 is a transistor, 5 is a secondary winding, 7 is a rectifier circuit, 12 is a load, and 13 is a control circuit, 21 is a comparator, 2
2 is a sawtooth wave generation circuit, 24 is a voltage comparator, and 33 is an input voltage detection circuit.

Claims (1)

[Claims] 1. A transformer having a primary winding and a secondary winding;
a switching element connected in series to the primary winding; a DC power supply connected to a series circuit of the primary winding and the switching element; a rectifier circuit connected to the secondary winding; a resistor connected in parallel to the primary winding via a rectifier diode, and a maximum allowable duty factor that varies approximately in inverse proportion to the input voltage at least near the maximum value of the input voltage of the primary winding; A DC converter comprising: a switching element control circuit that supplies an on/off control signal having a duty factor within a range of a maximum allowable duty factor to the switching element;