JPS63246055A - Packet transmitter-receiver - Google Patents

Abstract

PURPOSE:To attain communication with high speed high throughput by separating a means applying complicated processing between packet transmission/ reception controllers and a means applying comparatively simple processing. CONSTITUTION:A transmission packet is sent to a line 131 from a transmission buffer 101 via a header addition circuit 111 and a line control section 12 and a reception packet is stored in a reception buffer memory 102 from a line 132 via the control section 12 and a header read circuit 112. In this case, mode setting or timeout recovery processing causes complicated processing with many control states. On the other hand, the addition of sequence number and reception error detection of a sequence number are processed comparatively easily. Then the former processing is realized by a memory 16 and an operation mode setting/error recovery processor 15, and the latter processing is executed by only a transmission/reception state circuit 14. Thus, while no error takes place, the processing is executed by the hardware only.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a packet communication system, and particularly to a high-speed and high-throughput packet transmitting/receiving device.

(Prior Art) In general, in the transmission and reception of packets, flow control to prevent overflow of a reception buffer and retransmission control to recover from errors such as dot errors during transmission and packet loss are required. In the prior art, these controls are often realized by a window control method used in high-level transmission procedure control (HDLC) and the like. This method limits the number of consecutive packets that can be transmitted, and also implements reception confirmation and retransmission procedures.

In the conventional system, these processes are performed using the third configuration. A sequence number is added to the transmission packet in the transmission buffer memory 331 by the Beda addition circuit 341 by the transmission control processor 35, and the packet is sent to the transmission line 311. A flag, a frame check sequence, etc. are added by the line control unit 32. On the other hand, the packet received from the reception line 312 is checked for flags and frame check errors by the line control unit 32, and then the sequence number and other information is read by the pedal reading circuit 342, and the Beda is analyzed by the transmission control processor 35. , are stored in the reception buffer 332.

Here, the transmission control processor 35 includes a header addition circuit 341
By notifying the header of the sequence number and detecting the received sequence number from the header reading circuit 342, the number of packets that can be continuously transmitted and the packets to be retransmitted are determined. That is, this is the core part of this system, which uses the above sequence number to control the number of transmittable packets, confirm reception of received packets, and perform retransmission procedures in the event of a reception error.

This control not only changes the internal control state each time each packet is sent or received, but also requires time management etc. in the retransmission procedure until confirmation of delivery of each sent packet (reception confirmation of received packet on the other side) is obtained. Requires extremely complex processing.

Furthermore, if delivery confirmation is not obtained within a certain period of time, it is necessary to perform a process of adjusting the receiving state of the other party's device and restarting the process. Furthermore, it is generally necessary to set an operating mode for performing these series of processes. In these cases, it is necessary to exchange commands and responses with the other party's transmitting/receiving device. Since the transmission control processing described above has a very large number of states, it has no choice but to rely on program processing in which a program is stored in the memory 36 and processed by the processor 35 based on the program, as shown in FIG.

In this case, even if the speed of the transmission line 312.311 is increased to several tens of Mbit/sec, the above software processing execution time is slow, so a throughput of only IMbit/sec can be obtained at most, making it impossible to realize high throughput packet communication. arise. One way to solve this problem is to execute the process using firmware, but since it basically has to rely on program control, the throughput can only be improved by a few Mbit/sha.

(Problems to be Solved by the Invention) As described above, in the conventional technology, it is necessary to perform very complicated processing for packet transmission and reception control, and it is necessary to rely on program processing. Therefore, there is a problem that high speed and high throughput cannot be obtained.

The present invention attempts to solve the above problems.

(Means for Solving the Problems) That is, the present invention is a packet transmitting/receiving device that performs packet transmission control, and includes a first control means for managing the transmission/reception status of each packet, error recovery processing for each packet, and setting of an operation mode. and a second control means that performs packet error recovery processing and operation mode setting, and when packet error recovery processing and operation mode setting are not performed, the first control means manages packet transmission and reception status and performs packet error recovery processing or operation mode setting. The first control means and the second control means are used only when making settings.
The first control means controls the transmission and reception of each packet in conjunction with the control means, and controls the transmission and reception of each packet.
Consisting of the following (a) to (fl), (a) a means for adding a sequence number to a transmitted packet, <b) a means for detecting a sequence error in a received packet, and (C) a means for adding a sequence number to a normally received packet. (d) means for requesting the other party's transmitting device to retransmit the packet whose reception has failed; and (e) until receiving notification of normal reception from the other party's receiving device for each transmitted packet. means for retaining the transmitted packet; The second control means that performs the recovery process and sets the operation mode includes the following (a) to (O), that is, (a) means for detecting the state of transmission and reception of packets from the first control means; means for transmitting a packet corresponding to the retransmission request from the destination receiving device to the destination receiving device via the first control means when receiving a notification of the packet retransmission request from the device; ) when it is detected from the timer means of the first control means that the normal reception notification or the retransmission request notification from the other party receiving device has not been received within a certain time; and (d) means for setting an operation mode with the other party's packet transmitting/receiving apparatus via the first control means. This is a characteristic packet transmitting/receiving device.

(Function) The present invention provides a means for performing complicated processing such as setting an operation mode between packet transmission and reception control devices, error recovery processing such as packet sequence error and timeout, and a method for performing complicated processing when no error occurs in normal data packet transfer. By separating the means for performing relatively simple processing, the former can be achieved through program control, and the latter can be easily implemented in hardware, making it possible to realize high-speed, high-throughput data transmission control with a small amount of hardware. can. In other words, the speed of data transmission control is usually executed only by hardware (wiring logic) as long as no errors occur, so if the element speed is increased, a throughput of several tens of Mbit/sec can be obtained.

(Embodiment) A packet transmitting/receiving device according to the present invention will be explained using FIG. 1. In FIG. 1, the transmission packet is sent to the transmission buffer 10.
1, the header addition circuit 111, and the line control unit 12 to be sent to the line 131. On the other hand, the received packet is sent from the line 132 via the line control unit 12 to the header reading circuit 112.
The data is then stored in the receive buffer memory. Here, the line control section 12 adds and checks a frame check sequence, adds a flag, and detects the frame check sequence. The packet transmission/reception state management circuit 14 corresponds to the first control means in claim 1. That is,
It manages packet sequence numbers during normal data transmission and reception.

On the other hand, a processor 15 for operating mode setting and error recovery control
and the memory 16 corresponds to the second control means,
Transmission control is performed in conjunction with the packet transmission/reception state management circuit only when performing the above-mentioned complicated processing. However, memory 16
stores the state transition control program for this purpose. Here, the packet processing sequence shown in FIG. 2 will be used to explain the specific processing. Here A
The case where data is transferred from to B is illustrated.

First, prior to data transmission, the operation mode and parameters are negotiated between A and B. Corresponds to the command/response in the figure. Data transmission then begins. A sequence number is added to each data (denoted by DT) (DT(1), DT(2), etc.).

The sequence number is incremented one after another. Here, RR(3) indicates that up to data DT(3) has been received. A moves from DT(0) to DT( until RR(3) is obtained.
3) is retained and prepared for retransmission. After confirming RR(3), A sends out DT(4) to DT(7). Here D
Consider the case where T(6) causes an error. B is DT (
7), a sequence error can be determined and a retransmission request REJ(5) is sent back to A. This RE
"5" in J(5) means that the receipt was normally received up to DT(5). Therefore, A starts retransmission from DT(6). At this time, the transmission sequence number needs to be updated from 7 to 6. That is, variables such as the read address of the transmission buffer and the sequence number are updated according to the contents of the REJ packet. After this, DT(6) to DT(
1) is transmitted, and further DT(2) is transmitted. Next, consider a case where RR(2) makes an error when returning arrival confirmation RR(2) for DT(2) from B to A. At this time, A measures the time from the transmission of each packet until the response is obtained. Here, the time expires due to an error in RR(2). In this case, A inquires of B as to how far the RR has been received (P=1). In response, B notifies A that it has received up to RR (2, F=1) and DT (2), and then normal transmission is resumed.

Among the series of processes described above, the processes that involve many control states and can be complicated are the mode setting of A and B, the retransmission process of A, and the timeout recovery process of A and B.

Adding a one-sided sequence number, detecting a sequence number reception error, and confirming arrival are relatively easy as long as you pay attention to the sequence number to be transmitted.

Here, the above processing is realized by the memory 16 in FIG. 1 and the operating mode setting/error recovery control processor 15.

On the other hand, the latter process is performed only by the packet transmission/reception state management circuit.

The most distinctive difference in the processing content between the two is that the latter increments the sequence number by one or returns the received sequence number as a response, whereas the former increments the sequence number and returns it as a response. The point is that a relatively random processing sequence is required, such as jumping or command response, in which various types of processing can be considered depending on the situation. Therefore, if these two are separated, and the latter is implemented in hardware and the former is implemented in software, processing can be executed only by hardware as long as no errors occur, and speeding up can be achieved.

Further, a detailed view of FIG. 1 is shown in FIG. 4. In this figure, the receiving buffer 40 is connected to the transmitting buffer 401 i, t 101.
2 to 102 and line control unit 42 to 12 to lines 431 and 43
2 corresponds to 111 and 112, respectively, and performs the same function as explained in FIG. 441 to 444 are shown in Figure 1
This corresponds to 14 packet transmission/reception state management circuits and header reading/addition circuits 112 and 111 of No. 4. Here, the transmission control circuit 442 determines a sequence number to be added to a transmission packet, and the reception control circuit 441 detects a reception sequence number error. Furthermore, the reception control circuit 441 sends a request for retransmission of a received error packet and confirms the arrival of a normally received packet by sending the reception status to the control line 44.
5 (IX2X3) to the transmission control circuit 442, and the transmission control circuit 442 transmits an RR packet or a REJ packet.

Further, the ACK waiting packet management circuit 444 stores the address of the packet held in the transmission buffer memory until it receives a normal reception notification for each transmitted packet, and the ACK waiting packet management circuit 444 stores the address of the packet held in the transmission buffer memory until it receives a normal reception notification for each transmitted packet.
1, the reception control circuit 4 receives the transmission packet sequence number and holds the storage address of the packet.
The processor 45 detects P(R> of the packet that has been notified of normal reception from the control line 4411 from the control line 4411 and resets the above-mentioned storage address. If retransmission is to be performed, the processor 45 sends the packet again via the control line 454. The address of the packet in the transmission buffer memory is known and the packet is retransmitted.

On the other hand, the timer 443 measures the time until a response is received from the receiving device for each transmitted packet, and is set via the control line 4421 in the same manner as above.
Re5et is performed at 1. A timer is set for each transmitted packet. When a timeout occurs, the sequence number of the packet that caused the timeout is notified to the processor 45 via the control line 453.

Packet transmission control when the above packet retransmission requests and timeouts do not occur, including adding sequence numbers to transmitted packets, and confirming the normal arrival of each packet (AC
K reception) and window flow control functions using sequence numbers are performed only by control circuits 441 and 442. In addition, 443.4 is used to manage ACK waiting packets and timer management to detect errors in response packets.
It is realized by 44 circuits.

All of these are simple controls that can be realized using only the hardware described below, enabling high-speed data transfer.

On the other hand, the operation of the processor 45 is as follows. When the reception control circuit receives a retransmission request packet from the other receiving terminal, it notifies the processor 45 through the control line 452. The processor 45 accesses the reception control circuit and the transmission control circuit via control lines 452 and 451 to determine the transmission/reception status, that is, the sequence number of the last transmitted packet and the sequence number of the last packet that was successfully received and received confirmation of arrival. Know. Then, by detecting for which sequence number the packet for which the retransmission request has been made by the above operation, the transmission control circuit is set to perform transmission from that packet. In this case, the ACK waiting packet management circuit is accessed to know the storage address of the packet in the transmission buffer memory. In this way, retransmission of the packet occurs.

In contrast, if a timeout occurs, the processor 45 learns the packet number for which no response is returned from the control line 453, and based on this, the processor 45 exchanges a command response packet for inquiring the status with the other transmitting/receiving device. This is done via control circuits 441, 442. In this case, the operation of the control circuits 441 and 442 is completely controlled by the processor. The same applies to the exchange of commands and responses for setting the operating mode.

All the operations of the processor 45 described above are processed by program control of the memory 46, so that even if the processing becomes complex, it can be handled.

Further, details of the circuits 441 and 442 will be explained. FIG. 5 is a detailed diagram of the transmission control circuit 442. At step 442, the header addition circuit 50 automatically adds a transmission sequence number p(s) and a reception sequence number P(R) to the transmission data 4011. P(S) is given by a counter 51 and is incremented every time one packet is transmitted. Further, at this time, 445(2) provides the normally received sequence number (reception P(R)) from the reception control circuit to the transmission permission/impossibility determination circuit 52. This judgment circuit 52 has a window size of 5.
Based on the values W and P(S) of 21, transmission control is performed so that the number of unconfirmed ACKs does not exceed W. On the other hand, if there is no transmission packet, an RR/RNR packet is generated from the circuit 54 and P(SR) indicating normal reception is notified to the other party. Also, if a sequence error is detected in the reception control circuit 441, 445
In (3), this fact is notified to the circuit 53 and a REJ packet is transmitted. (In other words, the retransmission request is automatically operated by hardware. However, the retransmission processing for it is processed by the processor.) Furthermore, the processor 45 can monitor or send the transmission sequence number via the control line 451 and the interface 4511. An interface 4512 can be used to instruct command/response transmission. REJ, RR/RNR, data packets, or command/response packets based on processor instructions are sent to 421 via selector 56 . Timer 443, A
The control circuit for the CK waiting packet is set via 4421 for each transmission sequence number P(S). FIG. 6 shows the reception control circuit 442. Received data 42 in circuit 60
2 headers are read. The received p(s) transmission sequence number is judged to have a sequence error by the sequence checker 61, and P(8) without an error is latched in the register 62 and stored. If there is no sequence error, this received P(S) is notified to the transmission control circuit 442 via the signal line 445(1), and is notified to the partner device as P(R), thereby realizing a normal reception notification. If there is an error, the transmission control circuit 442 is notified via 445(3) and an REJ frame is automatically transmitted.

On the other hand, the register 63 holds the P(R) reception sequence number of the received packet, which indicates how many of the packets that have already been sent have been successfully received by the destination device, and can be sent via window via 445(2). Used for impossibility judgment. Further, through the control line 4411, the timer 4
43 and Re56 of the ACK waiting packet management circuit 444
t is performed for each reception P(R). When a command response is received, its contents are held in the register 64 and notified to the processor 45 via the interface 452(1) and the control line 452. The processor 45 also receives P(S) via the interface 452(2),(3)
, P(R) can be monitored.

As described above, the transmission/reception control circuits 441 and 442 have a simple configuration, and can be fully realized with hardware.The timer 443 for each packet can also be configured with a memory and a counter.
The waiting packet management circuit can also be configured with only memory.

(Effects) As mentioned above, normal packet transmission/reception operations do not require the operation of the processor 45 unless an error occurs, and can be realized by processing only with hardware. By increasing the element speed, the line speed can be increased to 100 Mbit/s or more. This enables high-speed packet transmission and reception operations.

Further, in the case of error recovery, control is performed by a processor, but this reduces the error rate within the network, so that the deterioration in efficiency can be virtually ignored, making it possible to perform extremely high-speed, high-throughput communication as a whole.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a packet transmitting/receiving device according to the present invention, FIG. 2 is a diagram of a packet transmitting/receiving sequence to illustrate the principle of the present invention, FIG. 3 is a diagram showing a conventional packet transmitting/receiving device, and FIG. This figure describes FIG. 1 in more detail, FIG. 5 is a detailed diagram of the transmission control circuit of FIG. 4, and FIG. 6 is a detailed diagram of the reception control circuit of FIG. 4. In the figure, 12...Line control unit, 14...Packet transmission/reception state management circuit, 15...Operation mode setting/error recovery control processor, 16...Memory, 101.102...Buffer, 1
11...Header addition circuit, 112...Header reading circuit, 8 B Tei 5 times 4zu 1z

Claims (1)

[Claims] (1) A packet transmitting/receiving device that performs packet transmission control, consisting of a first control means that manages the transmission and reception status of each packet, and a second control means that performs error recovery processing of each packet and setting the operation mode, When the packet error recovery process and the operation mode setting are not performed, the first control means manages the packet transmission and reception status,
a first control in which the first control means and the second control means cooperate to control packet transmission and manage the transmission/reception status of each packet only when performing packet error recovery processing or setting an operation mode; The means include (a) a means for adding a sequence number to a transmitted packet; (b) a means for detecting a sequence error in a received packet; and (c) a means for notifying the other transmitter of the sequence number of a normally received packet. (d) means for requesting the other party's transmitting device to retransmit the packet whose reception has failed; and (e) means for holding each transmitted packet until notification of normal reception is received from the other party's receiving device for each transmitted packet. and (f) a timer means for detecting whether the normal reception notification or the retransmission request notification is returned from the destination receiving device for each transmitted packet within a certain time, and detects errors in each of the packets. The second control means for performing recovery processing and setting the operation mode includes: (a) means for detecting the transmission/reception status of packets from the first control means; and (b) means for receiving a request for retransmission of the packets from the partner receiving device. (c) means for transmitting a packet corresponding to the retransmission request from the other receiving device to the other receiving device via the first control means when the notification is received; When it is detected from the timer means that the normal reception notification or the retransmission request notification has not been received from the destination receiving device within a certain time, the first control means sends a message to the destination packet transmitting/receiving device. (d) means for setting an operation mode with the other party's packet transmitting/receiving device via the first control means.