JPS6322344B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a multi-processor system having a plurality of microprocessors, etc., in which shared resources (for example, shared memory, etc.) are accessed between the plurality of microprocessors. This invention relates to a shared resource access method for multiprocessor systems that improves coordination when processing.

[Technical background of the invention and its problems]

In recent years, as the cost of microprocessors has fallen, multiprocessing, in which a single system is equipped with a plurality of microprocessors and these microprocessors are used in coordination, has rapidly developed. The reason for this is that load distribution and function distribution can be achieved for system tasks. Furthermore, if it is distributed to independent microprocessors that operate in parallel, overall performance can be greatly improved. Additionally, multiprocessing allows for modular design, making system maintenance and expansion relatively easy.

By the way, in a conventional multi-processor system of this type, a plurality of masters 3, 3 are connected to a multi-bus 1 via local buses 2, 2, respectively, as shown in FIG. An output controller I/O 4 and a system memory 5 are connected. Each master 3 has a microprocessor 3a, a local input/output controller 3b, a local memory 3c, and a buffer 3d. The address is sent to the output controller 4, and the input/output controller 4 reads necessary data from the system memory 5 and sends it back to the user I/O or to the master 3. In the figure, 4a and 5a are address buses;
b and 5b are data buses, and 4c and 5c are response lines. Therefore, in such a system, when changing the input/output controller 4, for example, when replacing a floppy disk with a hard disk, the effect of the change remains on the input/output controller 4, and the microprocessor 3a
and application software can be used as is.

However, such a system does not manage access to the shared memory area of the system memory 5, which is a shared resource, and while one microprocessor 3a is rewriting the other microprocessor 3a, the system memory 5 is If you are currently writing, the wrong data will be read.
In order to prevent such a situation, a flag is set from the microprocessor 3a to the multi-bus 1 to indicate whether the shared memory area can be used or not (in use). This flag is called a semaphore. For example, if the semaphore value is "1" it cannot be used, and if it is "0" it can be used, then if the semaphore value indicates that it can be used between the microprocessors 3a and 3a that share the multibus 1, then , any one of the microprocessors 3a may set a semaphore when using the shared memory area, and clear it after use.

The problem here is that when one microprocessor 3a determines that it is "usable" and attempts to set a semaphore, another processor 3a checks for a semaphore that has not yet been set. However, it may be determined that it is usable. This problem can be solved by locking the bus while checking and setting the semaphore to prevent other microprocessors 3a from accessing the semaphore.

In recent 16-bit microprocessors, bus locks can be easily configured to make it easier to configure microprocessor systems.

Below, regarding the bus lock, Intel's iAP ×
Examples of 86/10 and iAPX88/10 (8086, 8088) are shown.
Traditional multiprocessing systems have been hampered by coordination problems, but these two microprocessors have the functionality built-in from the beginning. set to maximum mode
A bus lock signal (hereinafter referred to as a lock signal) is output from the iAPX86/10 and iAPX88/10.
Lock uses a 1-byte Lock prefix command.
When EU (Execution Unit) executes, BIU (Bus
Interface Unit), which remains active while an instruction with this prefix is being executed. However, the Lock prefix has nothing to do with interrupts. During this time, even if another process issues a request to use the bus, the microprocessor only records it and waits until the execution of the locked instruction is completed. The Lock signal is active only during one instruction. Even if two instructions with the Lock prefix are placed side by side, there will be a period of time in between when the instructions are not locked. Note that when a repeated string instruction is locked, Lock remains active during one block processing.

iAP×86/10 set to minimum mode,
iAP×88/10 does not have a Lock signal. but,
Using the Lock prefix, the CPU's HLDA for HOLD requests from the DMA controller to the CPU is
response can be delayed until the locked instruction has finished executing.

The Lock signal is merely informational.
It is the responsibility of other microprocessors on the shared bus to ensure that they do not access the bus while Lock is active. On systems that use an 8289 ``bus arbiter'' to control access to a shared bus, a Lock can be input to the 8289 to prevent it from releasing the bus while it is active. Lock
may be used in multiprocessing systems to coordinate access to shared memory areas such as buffers and pointers. If access to the shared memory area is not managed, an incorrect value may be read while another microprocessor is rewriting it.

On the other hand, 8-bit microprocessors (Intel 8085A,
(Zilog Z80, etc.) does not have a bus lock function and uses software to generate the bus lock signal. Intel's 8085A prevents other microprocessors from accessing the shared memory area by putting the serial data output into the override input of the bus beater. The 8085A instructions use the microprocessor's basic clock while checking the contents of the semaphore and setting the semaphore if it is unavailable.
Lock the bus for 58 clocks. The maximum speed of 8085A is 0.2 μs per clock, and at this time, 58
Access to the shared memory area from other microprocessors becomes impossible for ×0.2=11.6 μs. This time becomes a fatal obstacle when performing high-speed transmission (for example, when performing bit serial transmission, at 1 Mbaud, it is necessary to be able to access the shared memory area in an 8 μs cycle). For this reason,
In a system that uses a multiprocessor configuration to distribute system functions and perform high-speed transmission, this long bus lock time becomes a hindrance, making it impossible to increase the transmission speed.

[Purpose of the invention]

The present invention aims to minimize bus lock time and coordinate access to shared resources in a multi-processor system that does not have hardware for multiple microprocessors to coordinate access to shared resources. An object of the present invention is to provide a shared resource access method for a multi-processor system that uses multi-bus control signals.

[Summary of the invention]

In a multi-processor system composed of a plurality of microprocessors, when the microprocessors do not have a bus lock function, the present invention provides common access from each microprocessor in order to maintain coordination of access to shared resources. It is also equipped with a semaphore circuit that reads and writes the output of the built-in flip-flop by using the difference in timing between the bus controller signal of the local bus of the multiprocessor system and the system bus controller signal. This is a shared resource access method for multiprocessor systems.

[Embodiments of the invention]

Next, an embodiment of the present invention will be described with reference to FIGS. 2 to 6. In addition, FIG. 2 is a configuration diagram of the system memory connected to the multibus, FIG. 3 is a diagram showing a specific example of the semaphore circuit in FIG. 2, FIG. 4 is an address map diagram, and FIGS. The figure is a timing diagram of semaphore read and write. In FIG. 2, reference numeral 11 denotes a multi-bus to which a plurality of microprocessors (not shown) are connected, and has an address bus 11A and a data bus 11B. 12 is a decoder that decodes the system address input from address bus 11A; 13a and 13b are decoders 1;
14 is a semaphore circuit which includes a semaphore select signal SS, a system memory read control signal MRDC, and a system memory write control signal MWTC. is now being entered.

FIG. 3 shows a specific example of the semaphore circuit 14, and although the type of microprocessor to be used is not particularly limited, an example of the configuration of a multiprocessor system using Intel's 8085A will be described. The multiprocessor accesses the shared memories 13a and 13 via the address bus 11A of the multibus 11.
When b is accessed, the decoder 12 decodes the system address and generates a memory chip select signal MC for the shared memories 13a and 13b according to the contents of the system address. As shown in the address map of FIG. 4, this semaphore circuit 14 has a semaphore-occupied portion SD allocated to a part of the system address space ST, so the decoder 12 sends a semaphore select signal therefor. SS is starting to occur.
14a and 14b are NAND gates with a "low level L" active input, which take the negative AND of each of the semaphore select signals SS, the system memory read control signal MRDC, and the system memory write control signal MWTC, and generate the semaphore read signal. S1 and a semaphore write signal S2. Semaphore read signal S1 is D type FF (for example, 74LS74) 1
Clock terminal CP of 4c and 3-state buffer 14d
(For example, 74LS125) is input to the gate terminal.
On the other hand, semaphore write signal S2 is D type FF
It is input to the reset terminal R of 14c. D type
The set terminal S and data input terminal D of FF14c are each connected to +5V, and the set function is inactive, and D is output at the rising edge of the clock.
The Q terminal of type FF14c is set to H level. Also, the semaphore write signal S2
is active (logic level L), and this Q terminal changes from H to L. The Q terminal of a D type FF14c is connected to the input side of the three-state buffer 14d,
The output side is connected to the system data bus.
When the semaphore read signal S1 is active L,
The 3-state buffer 14d output is open and D
The state of the Q terminal of type FF14c is read to the system data bus. Although FIG. 3 shows one semaphore circuit 14, the number can be increased to any number.

Next, the operation of the semaphore circuit configured as shown in FIG. 3 will be explained. In the case of semaphore read, as shown in FIG.
MEMR is output. When the memory is placed in the system address space ST, the bus arbiter generates the system bus control signal MRDC. At this time, if another microprocessor is using the multibus 11, it will be in a busy state and in a waiting state, so the time until the system bus control signal MRDC is output is not constant.
When a read is performed on a semaphore, deuda 1
2 is ANDed to generate a semaphore read signal S1. System bus control signal MRDC is local bus control signal
Since MEMR becomes inactive after becoming inactive, the timing at which the signal S1 becomes inactive is also delayed from the timing at which the signal MEMR becomes inactive. Therefore, when the microprocessor reads the semaphore, the D type FF 14c is read by the signal MEMR while the gate of the 3-state buffer 14d is open by the signal S1.
Read the status of the Q output. Immediately after the microprocessor finishes reading, the Q output of the D type FF14c goes to H level at the rising edge of the signal MRDC. Originally, when the Q output is at H level, it remains as it is. In addition, Q-1 is the Q output of the D type FF14c when it has been in the reset state, Q
-2 is D type when it has been in the set state from before.
This is the Q output of FF14c.

In the case of semaphore or write, as is clear from Figure 6, the same procedure as in the case of semaphore or read is applied.
A signal S2 is generated from the NAND gate 14b.
This signal S2 resets the output of the D type FF 14c and resets the state of the semaphore to "0". This means that in 8086 cases MOV〓
This corresponds to executing SEMAPHORE,0.

〔Effect of the invention〕

As detailed above, according to the present invention, by using the semaphore circuit shown in FIG. 3, it is possible to read and write data during one cycle read access of the multibus. For example, in the case of Intel Corporation 8085A, Of the portion equivalent to 58 clocks of , 45 clocks excluding 13 clocks of LDA SEMA ADDRESS, or 1 clock
If it is set to 0.2 μs, the time can be reduced by 9 μs, and the semaphore check can be performed in the same time as accessing a normal shared resource. Therefore, even in a system that uses a multi-processor configuration to perform load distribution and transfer high-speed data, a multi-processor system that allows access to shared resources while maintaining access coordination between each microprocessor is possible. can provide a shared resource access method.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a multi-processor system, FIGS. 2 to 6 are shown to explain an embodiment of the method of the present invention, and FIG. 2 is an example configuration diagram of a system memory. FIG. 3 is a block diagram of the semaphore circuit, FIG. 4 is an address map diagram, and FIGS. 5 and 6 are time charts for semaphore read and semaphore write. 11...Multibus, 12...Decoder, 13
a, 13b...Shared memory, 14...Semaphore circuit, 14a, 14b...NAND gate, 14
c...D type FF, 14d...3 state buffer.

Claims (1)

[Claims] 1. In a multi-processor system composed of a plurality of microprocessors, in order to prevent simultaneous access to shared resources, when one microprocessor accesses a shared resource, it has a priority control circuit that prohibits access from the other microprocessor. If the processor does not have a bus lock function, it must be commonly accessible from each microprocessor and multi-processor in order to maintain coordination of access to shared resources.
It is equipped with a semaphore circuit that reads and writes the output of the built-in flip-flop by utilizing the difference in timing between the bus controller signal of the local bus of the processor system and the system bus controller signal, minimizing access time. A shared resource access method for a multi-processor system characterized by: