JPS6321827A - Semiconductor manufacturing equipment - Google Patents
Semiconductor manufacturing equipmentInfo
- Publication number
- JPS6321827A JPS6321827A JP16768386A JP16768386A JPS6321827A JP S6321827 A JPS6321827 A JP S6321827A JP 16768386 A JP16768386 A JP 16768386A JP 16768386 A JP16768386 A JP 16768386A JP S6321827 A JPS6321827 A JP S6321827A
- Authority
- JP
- Japan
- Prior art keywords
- film
- chamber
- annealing
- section
- lamp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000137 annealing Methods 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000004544 sputter deposition Methods 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 6
- 239000010936 titanium Substances 0.000 abstract description 6
- 229910052719 titanium Inorganic materials 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 239000007789 gas Substances 0.000 abstract description 3
- 239000011261 inert gas Substances 0.000 abstract description 3
- 239000010453 quartz Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005422 blasting Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体製造装置、特にウェハ表面上に膜を
形成するものに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor manufacturing apparatus, particularly an apparatus for forming a film on a wafer surface.
第２図は従来のランプアニール装置の一例を示す断面図
である６図において、１はウェハ、２はウェハ１を保持
するサセプタ、３は石英チャンバ、４は該チャンバ３の
フタ、５はチャンバ３のガス導入部、６は加熱用のラン
プである
従来のランプアニール装置では、ウェハ１を大気中でサ
セプタ２に乗せた後、石英チャンバ３内に挿入する。そ
の後、フタ４を閉めて密閉し、ガス導入部５より窒素ガ
スを導入し石英チャンバ３内の雰囲気を置換するかある
いは真空にした後、ランプ６を点灯してアニールを行な
う。FIG. 2 is a sectional view showing an example of a conventional lamp annealing apparatus. In FIG. 6, 1 is a wafer, 2 is a susceptor that holds the wafer 1, 3 is a quartz chamber, 4 is a lid of the chamber 3, and 5 is a chamber. In the conventional lamp annealing apparatus, which includes a gas introduction section 3 and a heating lamp 6, the wafer 1 is placed on a susceptor 2 in the atmosphere and then inserted into a quartz chamber 3. Thereafter, the lid 4 is closed and hermetically sealed, nitrogen gas is introduced from the gas inlet 5 to replace the atmosphere in the quartz chamber 3, or the atmosphere inside the quartz chamber 3 is evacuated, and then the lamp 6 is turned on to perform annealing.
また、上記装置には枚葉処理装置であるため石英チャン
バ３の熱容量が小さく、昇降温速度が速いという特徴が
あり、このためチタ二／等の酸化しやすい金属の熱処理
を行なう場合、これまでよく用いられてきた拡散炉に比
べ低温で炉内にウェハを挿入でき、また石英チャンバ３
内をより完全に不活性ガス雰囲気に置換するか真空にす
ることができこれにより、金属表面に酸化物が形成され
るのを抑制することが可能であった。In addition, since the above-mentioned apparatus is a single-wafer processing apparatus, the heat capacity of the quartz chamber 3 is small, and the temperature rise and fall rate is fast. The wafer can be inserted into the furnace at a lower temperature than the commonly used diffusion furnace, and the quartz chamber 3
It was possible to more completely replace the interior with an inert gas atmosphere or create a vacuum, thereby making it possible to suppress the formation of oxides on the metal surface.
しかしながら、従来の装置では膜形成された試料をアニ
ール部へ移す際、試料が大気にさらされるため、チタン
等の酸化しやすい金属膜ではその芒表面層に酸化膜が形
成されてしまうという問題点があった。However, in conventional equipment, when the sample with a film formed is transferred to the annealing section, the sample is exposed to the atmosphere, which causes the problem that an oxide film is formed on the surface layer of metal films that easily oxidize, such as titanium. was there.
この発明は上記のような問題点を解消するためになされ
たもので、酸化しやすい金属膜が形成された試料でも、
その金属膜表面に酸化膜が形成されることなくランプア
ニールすることができる半導体製造装置を得ることを目
的とする。This invention was made to solve the above problems, and even samples with a metal film that is easily oxidized,
An object of the present invention is to obtain a semiconductor manufacturing apparatus that can perform lamp annealing without forming an oxide film on the surface of the metal film.
この発明に係る半導体製造装置は、同一装置内にランプ
アニール部と成膜部を設け、さらに試料を不活性雰囲気
中または真空中で搬送するための搬送部を上記成膜部と
ランプアニール部間に設けたものである。A semiconductor manufacturing apparatus according to the present invention includes a lamp annealing section and a film forming section in the same apparatus, and further includes a transport section for transporting a sample in an inert atmosphere or in a vacuum between the film forming section and the lamp annealing section. It was established in
この発明においては、試料を不活性雰囲気中または真空
中で搬送するための搬送部を成膜部とアニール部間に設
けたから、成膜部で金属膜を形成膜された試料を、不活
性雰囲気中または真空中の搬送部を通してランプアニー
ル部へ搬送することができ、これにより金属表面に酸化
膜が形成されることなくランプアニールすることが可能
となる。In this invention, since the transport section for transporting the sample in an inert atmosphere or vacuum is provided between the film forming section and the annealing section, the sample on which the metal film has been formed in the film forming section is transferred to the inert atmosphere. The metal can be transported to the lamp annealing part through a transport part inside or in a vacuum, thereby making it possible to perform lamp annealing without forming an oxide film on the metal surface.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は、本発明の一実施例による半導体製造装置の概
略構成を示し、図において、７は試料を外気から隔離す
るためのロードロック室、８は試料を真空中あるいは不
活性ガス中で成膜室あるいはランプアニール室へ搬送す
るための搬送系、９は試料表面に膜を形成するための成
膜室、１０は膜が形成された試料をアニールするための
ランプアニール室であり、酸アニール室の周壁はその一
部または全部が石英ガラスにより構成されている。FIG. 1 shows a schematic configuration of a semiconductor manufacturing apparatus according to an embodiment of the present invention. In the figure, 7 is a load lock chamber for isolating the sample from the outside air, and 8 is a load lock chamber for separating the sample from the outside air. A transport system for transporting to a film forming chamber or a lamp annealing chamber; 9 a film forming chamber for forming a film on the sample surface; 10 a lamp annealing chamber for annealing the sample on which a film has been formed; Part or all of the peripheral wall of the annealing chamber is made of quartz glass.
また、アニール室１０の周辺部には加熱用ランプ（図示
せず）が設けられている。ここで上記成膜室９．アニー
ル室１０．搬送系８は、任意の雰囲気を所定の気圧に充
填できるものである。Further, a heating lamp (not shown) is provided around the periphery of the annealing chamber 10. Here, the film forming chamber 9. Annealing chamber 10. The transport system 8 can be filled with any atmosphere to a predetermined atmospheric pressure.
次に作用効果について説明する。Next, the effects will be explained.
ロードロツタ室７に搬入され、外気と分離されたシリコ
ン半導体基板（試料）・を搬送系８を通して成膜室９に
搬送する。ここで上記基板上に例えばチタン膜をスパッ
タリング法により形成した後、再び搬送系８を通してラ
ンプアニール室ｌＯにシリコン半導体基板を搬送する。A silicon semiconductor substrate (sample), which has been carried into the load rotor chamber 7 and separated from the outside air, is conveyed to the film forming chamber 9 through the conveyance system 8. After forming, for example, a titanium film on the substrate by sputtering, the silicon semiconductor substrate is again transported to the lamp annealing chamber IO through the transport system 8.
このとき、搬送系は真空もしくは不活性ガス雰囲気状態
であるために、酸化しやすいチタン膜表面に酸化膜が形
成されることなくランプアニール室にシリコン半導化け
なって、チタン膜表面に酸化膜のない膜を形成すること
ができる。At this time, since the transport system is in a vacuum or inert gas atmosphere, an oxide film is not formed on the surface of the titanium film, which is easily oxidized, and the silicon semiconductor is not formed in the lamp annealing chamber. It is possible to form a film without
なお、上記実施例ではスパッタリング法を用いてチタン
膜を形成した場合について述べたが、これはイオンブレ
ーティング法、蒸着法、ＣＶＤ法等のいずれの方法を用
いてもよい。In the above embodiments, the titanium film was formed using a sputtering method, but any method such as an ion blasting method, a vapor deposition method, or a CVD method may be used.
以上のように、この発明によれば同一装置内にランプア
ニール部と成膜部を設け、さらに試料を不活性雰囲気中
または真空中で搬送するための搬送系を成膜部とアニー
ル部間に設けたので、酸化しやすい金属膜が形成された
試料でもその金属膜表面に酸化膜が形成されることなく
ランプアニールすることができる半導体製造装置を得る
ことができる。As described above, according to the present invention, a lamp annealing section and a film forming section are provided in the same apparatus, and a transport system for transporting the sample in an inert atmosphere or in a vacuum is provided between the film forming section and the annealing section. By providing this, it is possible to obtain a semiconductor manufacturing apparatus in which even a sample on which a metal film that is easily oxidized can be subjected to lamp annealing without forming an oxide film on the surface of the metal film.
第１図はこの発明の一実施例による半導体製造装置を示
す概略図、第２図は従来のランプアニール装置を示す断
面図である。
図において、７はロードロック室、８は搬送系、９は成
膜室、１０はランプアニール室である。
なお図中同一符号は同−又は相当部分を示す。
第１ 図
７：ＯＪ”Ｄ／夕ｆ
第２図
１：りｌ／／
２“グｔフタ
３：１ｊｉｆ−／−ン／／”
４：ノタ
５ニア°λメλ〃
６：ランフ。FIG. 1 is a schematic view showing a semiconductor manufacturing apparatus according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional lamp annealing apparatus. In the figure, 7 is a load lock chamber, 8 is a transport system, 9 is a film forming chamber, and 10 is a lamp annealing chamber. Note that the same reference numerals in the figures indicate the same or equivalent parts. 1st Fig. 7: OJ"D/evening f Fig. 2 1: ri// 2"gut lid 3: 1jif-/-n//" 4: Nota 5 near ° λ me λ 6: Lumph.
Claims (3)
ルする半導体製造装置において、任意の雰囲気をその気
圧が所定値になるよう充填できる成膜部及びアニール部
と、 上記成膜部とアニール部との間に設けられ、半導体基板
を真空中あるいは不活性雰囲気中で上記成膜部からアニ
ール部へ搬送するための搬送部とを備えたことを特徴と
する半導体製造装置。(1) In a semiconductor manufacturing device that forms a film on a semiconductor substrate and then anneals the whole, there is a film forming part and an annealing part that can be filled with an arbitrary atmosphere so that the atmospheric pressure becomes a predetermined value, and the film forming part and the annealing part. 1. A semiconductor manufacturing apparatus comprising: a transport section provided between the film forming section and the annealing section for transporting the semiconductor substrate from the film forming section to the annealing section in vacuum or in an inert atmosphere.
ンブレーティング、ＣＶＤのいずれかの方法であること
を特徴とする特許請求の範囲第１項記載の半導体製造装
置。(2) The semiconductor manufacturing apparatus according to claim 1, wherein the method for forming the film is one of sputtering, vapor deposition, ion blating, and CVD.
部が石英ガラスにより構成されていることを特徴とする
特許請求の範囲第１項または第２項記載の半導体製造装
置。(3) The semiconductor manufacturing apparatus according to claim 1 or 2, wherein the lamp annealing section has a peripheral wall partially or entirely made of quartz glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16768386A JPS6321827A (en) | 1986-07-15 | 1986-07-15 | Semiconductor manufacturing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16768386A JPS6321827A (en) | 1986-07-15 | 1986-07-15 | Semiconductor manufacturing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6321827A true JPS6321827A (en) | 1988-01-29 |
Family
ID=15854290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16768386A Pending JPS6321827A (en) | 1986-07-15 | 1986-07-15 | Semiconductor manufacturing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6321827A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04226025A (en) * | 1990-04-16 | 1992-08-14 | Applied Materials Inc | Method forming titanium silicide con- ducting layer on silicon wafer |
| JPH04226023A (en) * | 1990-04-16 | 1992-08-14 | Applied Materials Inc | Low nitrogen pressure manufacturing method for forming titanium silicide on semiconductor wafers |
| JPH04226024A (en) * | 1990-04-16 | 1992-08-14 | Applied Materials Inc | Method for the formation of titanium sili- cide on semiconductor wafer |
| JPH05102075A (en) * | 1991-03-29 | 1993-04-23 | Applied Materials Inc | Method for forming tungsten contact having low resistance and low defect density for silicon semiconductor wafer |
| JPH07111252A (en) * | 1990-04-20 | 1995-04-25 | Applied Materials Inc | Method for formation of titanium nitride on semiconductor wafer by reaction of nitrogen-contained gas with titanium in integrated treatment system |
| JP2002512450A (en) * | 1998-04-16 | 2002-04-23 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method for manufacturing NAND flash memory device capable of easily obtaining poly 1 contact by removing poly cap |
| CN101988193A (en) * | 2009-08-05 | 2011-03-23 | 鸿富锦精密工业（深圳）有限公司 | Wet film-coating system |
| JP2013140990A (en) * | 1998-03-03 | 2013-07-18 | Akt Kk | Method of coating and annealing large area glass substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57117278A (en) * | 1981-01-14 | 1982-07-21 | Sony Corp | Manufacture of semiconductor device |
| JPS59124712A (en) * | 1982-12-29 | 1984-07-18 | Fujitsu Ltd | semiconductor manufacturing equipment |
-
1986
- 1986-07-15 JP JP16768386A patent/JPS6321827A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57117278A (en) * | 1981-01-14 | 1982-07-21 | Sony Corp | Manufacture of semiconductor device |
| JPS59124712A (en) * | 1982-12-29 | 1984-07-18 | Fujitsu Ltd | semiconductor manufacturing equipment |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04226025A (en) * | 1990-04-16 | 1992-08-14 | Applied Materials Inc | Method forming titanium silicide con- ducting layer on silicon wafer |
| JPH04226023A (en) * | 1990-04-16 | 1992-08-14 | Applied Materials Inc | Low nitrogen pressure manufacturing method for forming titanium silicide on semiconductor wafers |
| JPH04226024A (en) * | 1990-04-16 | 1992-08-14 | Applied Materials Inc | Method for the formation of titanium sili- cide on semiconductor wafer |
| JPH07111252A (en) * | 1990-04-20 | 1995-04-25 | Applied Materials Inc | Method for formation of titanium nitride on semiconductor wafer by reaction of nitrogen-contained gas with titanium in integrated treatment system |
| JPH05102075A (en) * | 1991-03-29 | 1993-04-23 | Applied Materials Inc | Method for forming tungsten contact having low resistance and low defect density for silicon semiconductor wafer |
| JP2013140990A (en) * | 1998-03-03 | 2013-07-18 | Akt Kk | Method of coating and annealing large area glass substrate |
| JP2002512450A (en) * | 1998-04-16 | 2002-04-23 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method for manufacturing NAND flash memory device capable of easily obtaining poly 1 contact by removing poly cap |
| CN101988193A (en) * | 2009-08-05 | 2011-03-23 | 鸿富锦精密工业（深圳）有限公司 | Wet film-coating system |
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