JPS63201783A - Picture processing device - Google Patents

Abstract

PURPOSE:To increase the picture processing speed by simultaneously processing picture data, which is stored in a picture memory, by a processor unit consisting of processor elements whose number is smaller than that of memory elements and reading and writing data in accordance with addresses which are controlled by an address control means correspondingly to the size of a unit processing area. CONSTITUTION:The picture memory is provided which consists of plural memory elements which are accessed by addressing independently of another memory. The processor unit which consists of processor elements whose number is smaller than the number of memory elements and simultaneously processes plural picture elements of the picture memory, and the address control means which controls addresses correspondingly to the size of the unit processing area in the picture memory are provided. Thus, a picture processing device is obtained where the picture processing is quickly performed independently of the size of the processing area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and particularly to an image processing device that performs high-speed processing and parallel processing of image data using an image memory control technique.

[Prior Art] Generally, when processing images at high speed, software is used as the computer processing method.
As the amount of image data increases, speeding up becomes necessary. There are two methods for speeding up processing: one is a method using serial processing hardware called the pipe line method, and the other is a parallel processing method using multiple processors. . The former has a limit because the processing clock frequency increases as image data is processed at high speed. On the other hand, in the latter case, speedup can be increased to any degree by increasing the number of processors placed in parallel. In extreme terms, it is one of the technologies that is currently attracting attention because it is possible to obtain maximum speed by placing as many processors as there are pixels.

By the way, at this time, communication processing between each pixel becomes important, and it is necessary to proceed with processing while performing mutual communication. In such a parallel processing method, it is impossible to have as many processors as each pixel when handling high-resolution data. For example, when handling an image read on A4 paper with 16 pixels/1III (pel), the number of pixels is approximately 16M pixels (pi
xels), and it is impossible to have this many processors at the same time.

[Problems to be Solved by the Invention] The present invention provides an image processing device that performs image processing at high speed regardless of the size of a processing area.

[Means for Solving the Problem] As a means for solving this problem, the image processing device of the present invention has a plurality of memories that can be accessed by specifying addresses independently of other memories. an image memory consisting of elements; a processor unit consisting of a plurality of processor elements smaller than the memory elements and processing multiple pixels in the image memory at the same time; and a processor unit corresponding to the size of a unit processing area in the image memory. and address control means for controlling the address.

Also, an image memory consisting of a plurality of memory elements that can be accessed by specifying addresses independently of other memories, and a plurality of processors smaller than the memory elements.
a processor unit that simultaneously processes a plurality of pixels in the image memory; an address control means that controls an address in accordance with the size of a unit processing area in the image memory; and a chip of the memory element. and enable control means for controlling enable.

[Operation] In such a configuration, the image data stored in the image memory is simultaneously processed by a processor unit consisting of fewer processor elements than the number of memory elements, and is controlled by the address control means in accordance with the size of the unit processing area. read/write using the specified address.

Further, the size of the processing area of the image memory can be freely changed by the enable control means.

-Margin below- [Example] An embodiment of the present invention will be described below.

The configuration of the image processing apparatus of this embodiment includes an image memory 1 for one page, a processor unit 2, and a peripheral section 3 such as input/output devices. FIG. 1 shows the basic configuration of only the basic part, in which an image memory 1 is connected to a processor unit 2. Nxm image data at an arbitrary position on the image memory 1 is transferred to a processor unit 2 constituted by an array of nxm processor elements 2a,
After being processed at high speed, it is returned to the image memory 1 again. n
Each process within the array of processor elements 2a of Xm is performed simultaneously, which is a so-called parallel processing architecture. Further, other configurations are shown in FIGS. 9(a) and 9(b). In FIG. 9(a), according to the control of the control circuit 94, image data from the input side image memory is transferred to a processor unit 92 consisting of a plurality of processor elements.
A plurality of pixels are subjected to predetermined processing in parallel and stored in the output side image memory 93. On the other hand, in FIG. 9(b), an image memory 91 or 93, a processor unit 92, a human power device 96, and an output device are connected by a common bus.

The image memory 1 will be described in detail below.

Now, for simplicity, set the image size to 1024 x 102.
We will proceed with an image memory having 4 pixels, each with 8 bits/pixel data. To change the image size, it is only necessary to extend the architecture of this embodiment. In addition, the processor unit 2 has a total of 16 processor elements 2 of 4×4.
It shall consist of a.

FIG. 2 is a diagram showing the configuration of the image memory 1.

Assuming that the image structure is made up of 1024 x 1024 pixels as shown in the figure, dividing this into 4 x 4 units results in a total of 256 x 256 pixels, 64 K (=65
536 ) blocks. Now, this is the third
As shown in the figure, it is reorganized in units of 4 x 4 pixels, and 4 x 4 pixels = 64 pixels.
(each pixel has 8 bits of data). Therefore, the memory address space is 4x4x64
Three-dimensional addressing is possible.

Assuming that one memory chip supports one 64 pixel in a 4.times.4 pixel, a memory chip is required in which each address is 8 bits deep in the 64 address space. This requires a memory chip with a capacity of 512 bits (=64 Kbytes), but in this embodiment, a combination of two dynamic RAMs (D-RAMs) of 256 bits is used. That is, 64 out of 256 bits D-RAM x 4
Two bit configurations are used as 64K x 8 bits. These two memory chips will be referred to as memory element 1a from now on.

The image memory 1 is composed of 16 memory elements 1a corresponding to a 4×4 matrix. Fourth
The figure shows the configuration of such a 4×4 memory element 1a. Each memory element 1a is designated with a row address and a column address, and one pixel of 4×4 pixels is designated as 6
Image data in the address space of 4 is input/output. The row address generator 4 and column address generator 5 give addresses to each 4×4 memory element 1a. Note that memory element 1a is D-R.
If AM is used to time-share and provide row addresses and column addresses, only one address generator is required. At this time, time-division switching control of row addresses and column addresses is required.

By giving each address from such an address generator, a memory element 1 of 4×4 pixels is created.
It becomes possible to read/write a. That is, by specifying the address - times, image data for 4×4 pixels can be driven simultaneously. Therefore, as a data line,
It is assumed that an 8-bit data line comes out directly from each memory element 1a.

Now, suppose that data with a row address of A (0≦A≦255) and a column address of B (0≦B≦255) is read from the image memory 1, then the image data (A , B), 8-bit long image data of 4×4 pixels is read out.

Furthermore, simultaneous access of a plurality of pixels will be generalized and explained.

FIG. 10 shows one page of the image as it is, and this image data is shown in the figure as follows:
Divide into blocks of 11 pixels, kxf1 as shown in Figure 11.
memory elements 1a. Also, kxJ
A block of J pixels is (0, O), (0, 1), (
0,2).

The memory is numbered (0, 3)... and consists of x 1 memory elements 1a as shown in FIG.
Corresponds to unit 1. Figure 13 shows memory unit 1
It is a two-dimensional representation of Also, since the memory size to be accessed is in block size units of kxJJ pixels, even if a block R of kxfi pixels at an arbitrary position is accessed, kx! All one memory element 1a is accessed, and each one address is accessed after one memory element 1a.

In this way, the image data of a plurality of kX1 adjacent pixels at arbitrary positions in the image are accessed at once, read, and then processed by the processor unit 2. The image data processed by processor unit 2 is again 'x, Q
'You can access and write to any position with a pixel block size.Here, k' = and u' =
This will be explained in the future as part 1.

To provide a supplementary explanation of the above-mentioned memory access for only 'xJJ' pixels, when the processing in the processor unit 2 is spatial filter processing, etc., the block size accessed by the writing side is larger than the block size kxJL accessed by the reading side. may become smaller. Generally, the write side block size is 'x, 11'.
is often processed as 1×1. Also, when the processing in the processor unit 2 is image reduction processing, the block size accessed on the write side is smaller than the block size kxl accessed on the read side.

Generally, the block size on the light side 'xJl' is the minimum integer that satisfies the statement '≧α and the statement '≧β' when the vertical and horizontal reduction ratios are α and β. . If the reading and writing memories are the same or have the same kxl memory configuration, and the above two examples are performed, the configuration size of memory unit 1 on the writing side is kx
You must write to 'xJJ' to a size smaller than the intersection. In this case, memory element 1
Instead of accessing all kXJL elements of a, the memory element 1a that does not correspond to writing must be masked to prevent it from being accessed. However, kx! The image memory 1, which is composed of one memory element 1a, can access and read a maximum of kxJL adjacent image data at one time.
The adjacent 'Xi' image data of a smaller size can also be accessed freely by performing the masking described above. Masking and accessing only 'XJJ' pieces at the same time is easily possible by manipulating the chip enable of the memory element 1a.

Next, examples of memory access of a predetermined pixel at an arbitrary position will be explained in the case where the memory unit configuration is 4 x 4 and k x JJ, and the chip enable control for masking will also be explained. explain.

First, an example will be shown in which the block sizes kx and Q are 4×4.

FIG. 5 shows an enlarged view of a portion of FIG. 2.

A process will be described in which image data of an arbitrary 4×4 block S in the image memory 1 is read out, processed by the processor unit 2, and then transferred to an arbitrary 4×4 block T.

The 4x4 squares in Figures 5 and 6 are 4x4 16
This is the first point that separates the memory elements 1a. If these 16 memory elements 1a contain Aa, Ab,
..., Ba, Bb, ---Ca, -Dc, Dd. First, when reading a 4×4 block S, among the 16 memory elements 1a, the memory
Element Dd has (row address, column address)
(N, M) is given as Memory element D
(N, N+1) for memory elements Ad, Bd, and Cd, and (N+1.M) for the remaining memory elements Ad, Bd, and Cd.
The element is given (N+1.N+1). This is the row address generator 4 mentioned above. Generated by column address generator 5. Furthermore, once the position of the end point U of the 4×4 block S is determined, divide its horizontal and vertical position addresses by 4 and find the remainder n.

It is clear that the row address and column address allocated to memory element AaNDd are uniquely determined by m. Suppose the position address of U (Y, X)
Then, Y=4N+n (n=0.1,2.3)X=4M+m
(m=o, 1, 2.3) For example, M in address generator 4.5.

It is also possible to consider a configuration in which information on N and information on m and n are input into a look-up table or the like, and an address given to mesori element A a ND d is output. At this time, the outputs are M, N, N+1. It is clear from the above explanation that it is any one of N+1.

Also, by using this property, as shown in Fig. 7, n or m is entered manually in the lookup table, and 0.
1 and control whether or not to increment the address N or M given to the memory element AaNDd.

The row address generator 4 uses n and N, and the column address generator 5 uses m and M.

In this way, addresses are given to the 4×4 16 memory elements by the address generators 4 and 5 as described above, and 16 pieces of data can be obtained at the same time.

These 16 pieces of data are transferred to the 4×4 block T shown in FIG. 5 again in the processor unit 2, with some processing or no processing at all. However, 16 memory elements A a -D
Each image data read from d is not necessarily transferred to the same memory element A a -D d. The 4×4 memory block S in Figure 5 is 4×4
, the data read from memory element Aa of 4×4 memory block S must be transferred to memory element Dc.

Then, the 4×4 memory blocks S, T are at their end points u, v
have arbitrary positions (y, x), (y', I will explain whether it is okay if it is written in .

As shown in Figure 5, Y = 4N+n (n=o, 1, 2.3)X = 4
M+m (m=o, 1,2.3)Y' =4P+p (
p=o, 1, 2.3) X' = 4Q+q (q=0.1
, 2.3), p-n=4y'+y (-y'=-1, -0y=0.
1, 2.3) ...■ q-m=4x' +x (x' =-1, 0x=0.
1, 2.3) ...■ Find x and y.

First, the row array A consisting of (Aa, Ab, Ac, Ad) is rotated X times in the right direction. This is named row array A'. Similarly, row arrays B, C, and D rotated X times in the right direction are named row arrays B', C', and D'.

Next, the array (ABCD)' consisting of row arrays A', B', C', and D' is rotated downward seven times.

In the case of FIG. 5, n, m, p according to FIG.

It is clear that q is 3, 3, 2, 1, so 0.0 formula% formula% obtain. Therefore, from the above explanation, we obtain the following matrix.

Rotating to the right twice, row array A' = (Ac, Ad, Aa, Ab) B' =
(Bc, Bd, Ba, Bb)C' = (
Cc, Cd, Ca, Cb) D' = (Da, Dd
, Da, Db) When rotated downward three times, (Be, Bd, Ba, Bb) (Cc, Cd, Ca, Cb) (Da, Dd, Da, Db) (Ac, Ad, Aa, Ab) − ■If we compare this matrix ■ with the basic array ■ below, we get A-a, Ab, Ac, Ad- Ba, Bb, Be, Bd Ca, Cb, Cc, Cd Da, Db, Dc, Dd. −Basic array■Basic array■
is simply a two-dimensional array of read data from memory elements Aa to Dd arranged from left to right and top to bottom, and matrix ■ is a two-dimensional array of read data from memory elements Aa to Dd.
This corresponds to a two-dimensional array in which the data to be written to d is arranged in order. That is, as an example, memory element Aa
Looking at the array ■, the data read from 4th line 3
written in column. If you refer to this basic array ■, 4
Since Dc is in the third column of the row, it is understood that the read data of the memory element Aa should be written to the memory element Dc.

For supplementary explanation, memory niremen)-Aa on Figure 5
It is easy to notice that it is sufficient if the read data is written to the position Dc, but the displacement from the position Aa to the position Dc is equal to the displacement from the position address U to the position ■. Also, since the configuration of the memory element 1a is 4×4, the horizontal direction
The remainder when both vertical positions are divided by 4 can be considered to be the displacements x and y of the memory element. For example, if the displacements of U and V are multiples of 4, the displacements x and y will be 0, and data read from a certain memory element will be written to the same memory element after processing. .

The hardware implementation of the above processing will be briefly explained.

FIG. 8 shows that data simultaneously read out from a memory element 1o consisting of 16 4×4 memory elements 1a is processed by the processor unit 2, and the data is stored in X-displacement raw data 81 by 4 elements each. Perform rotation for X number of times. After that, rotation is performed by the number of y based on the y displacement raw data 82,
Aa~Ad, Ba~Bd, ca~Cd, Da respectively
The configuration is such that data is written to memory element 1a of NDd.

Note that the y-displacement raw data 82 has 4 input elements each, so the y-displacement raw data 82 is exactly the same as the X-displacement rotation.
Needless to say, it can be composed of It goes without saying that the raw data may have a depth of the same number of bits as the depth of the memory data, or that the same number of 1-bit depths as the depth of the memory data may be used. Furthermore, it can be easily inferred that a shift register, barrel shifter, etc. can be used for raw data.

Further - if you think about it in defeat, you can change the memory block to kx
If the size is JJ, the memory emunit is 10.
The configuration of is also kxJJ. In this case, when a memory block S of kxJJ at an arbitrary position is processed by the processor unit 2 and then transferred to a memory block T of kxU at an arbitrary position, Y=kN+n (n=o, 1.- ”, k-1
)X=JIM+m (m=o, 1....,
l-1) (N, M, P, Q are 0, 1, 2.3...
)Y'=kp+p (p=o, 1....
, to -1) x'=danQ+q (q=0. 1. ・
..., q-1) However, if the position address of the end point of S is (Y
, X), the position address of the end point of T is (y', x')...
・(10) Find n, m, p, q, P−n”K:Y′+y (y′−1,0,31−0,1,2,3,...,−
1) , q-m=sentence x"+x (x'--1, O9x -0,1,2,3,-,u-1
)...(11) Processing may be performed using x and y such as, for example, X displacement raw data 81 and y displacement raw data 82 as shown in FIG. In this case, the X displacement raw data 81 has l manpower and can be shifted up to o-4-t. The y displacement raw data 82 has k manual forces and can be shifted from 0 to -1. Moreover, since each of the inputs of the y-displacement raw data 82 has one element, the raw data of one element of human input constitutes communication.

As shown in FIG. 10, memory element access control for simultaneous access of blocks of the above-mentioned 'x statements' will be explained.

The position address of the end point i of the block k"Xl' is (f
, g). Y when reading the memory accessed according to the above equation (10).

When assigning flg to X and writing to the memory to be accessed, assign flg to Y'' and X'.

By substituting the result into Equation (11) to obtain y and x, the embodiments shown in FIGS. 7 and 8 can be applied directly to kxJJ.

Also, at this time, only the memory element k'x, l' among the memory elements kx, +1 is chip-enabled. The chip that enables this is
Once the location address of (f, g) of end point i of l' is determined, n, m, or p, q can be uniquely determined from equation (10), and there are 'xJl' memory elements to be accessed. Uniquely determined.

By the way, as explained so far, in the grid configuration consisting of kxU memory elements, blocks 'x, Q' are simultaneously accessed on the read access side, and blocks k'xJJ' are simultaneously accessed on the write side. (However, 0≦k"≦, O≦dan"5 sentences), but this is also the same as the previous explanation.Example of chip enable control given to the memory element in this case is shown in FIG.

When the position addresses of the end points of the block of k'xJ1', k"x sentence" are (y, x), (y', x'), the formula (1
0), n, m, p, and q are found. This n, m and p
, q are input to the data input of the selector. Furthermore, a read/write signal R/W for memory access is manually inputted as a selector selection control signal, and n and m are selectively output when reading, and p and q are selectively output when writing.

Similarly, the block sizes, k'llj' and k''.

The angle is also input to the selector, and the R/W signal is input manually as a selection control signal. When reading, k'' and u= are selected and output, and when writing, k''.

By the way, the memory elements to be accessed are n, m, and ' on the read side.

It is clear that once k', k', p, and q on the light side are determined, they are uniquely determined, so these data output from the selector are input to the lookup table and are stored in the memory of kxJl, respectively. Outputs a signal that controls the memory to be accessed among the elements.

By the way, the images before and after being processed by processor unit 2 are separate memories, and their memory configurations are kX! 1, KXL, as shown in Figure 15, 2
It can be easily inferred that it is sufficient to use one lookup table. In this case, lookup table 151 and lookup table 152 are tables with different contents.

Further, there is no problem at all even if k= and u=L. With the configuration as described above, it is possible to partially mask the memory elements to be accessed without having to access all of the kxJl mesori elements. The configuration of the memory element of kXl may be set to the maximum required size of kXl.

Next, a description will be given of how the memory elements are accessed to process all the image data corresponding to the entire previous screen, that is, the scanning method of accessing all the memory data.

For example, the position artres of the end point U of the adjacent block kx, Q to be accessed, that is, the number when counting from 0 in the vertical direction from the end is Y, and the number when counting from 0 in the horizontal direction from the end The method of accessing the memory when Y and X are determined when the number is X has already been explained. That is this X.

An example of how to scan Y and process all images will be described.

(First example) This method scans the image data position addresses Y and X for accessing the memory element kxJl by increasing or decreasing them by an integer multiple of the intersection. For example, first set Y and X to 0. , X is sequentially increased by sentences. After increasing X to the end point in the horizontal direction, next set X back to 0,
Increase Y by , and then increase X by . This is repeated sequentially to scan the entire screen or a part of the screen. This will be tentatively named the first sequential scanning method.

(Second example) Also, instead of increasing and decreasing X and Y sequentially as described above, blocks of consecutive kX sentences are accessed here and there on the entire image screen, and when accessing, X, When the displacement is an integral multiple of Y crab 9 sentences, this is tentatively named the first random scan method.

(Third example) In order to access the memory element kxJl, the image data position addresses Y and X are scanned by incrementing and decrementing them by integers.
, and sequentially increase X by 1. After increasing X to the end point in the horizontal direction, set X back to O and set Y to 1.
Then increase X by 1. This is repeated sequentially to scan the entire screen or a part of the screen. This is tentatively named the second sequential scanning method. In this case, the same memory data is accessed many times.

(Fourth example) Also, instead of increasing and decreasing X and Y sequentially as described above, access blocks of 'xfL here and there on the entire image screen and execute this for all X and Y. . Or execute for all X and Y of a continuous part of the entire screen. When it is random, we tentatively name it the second random scan method.

(Fifth example) In a memory configuration having kx, l memory elements, when the memory block to be accessed is 'x-viewed', the position address Y, X
The block-wise scan method is different from the first sequential scan method, in which the entire screen is scanned by sequentially increasing and decreasing u' by an integer multiple of u'.
It is called the sequential scan method.

(6th example) Also, instead of increasing and decreasing X and Y sequentially as in (5th example), access successive 'XJl' blocks here and there on the entire image screen, and then
, XIJ (when the displacement is an integral multiple of k'xJl', this is tentatively named a blockwise random scan method.

(7th example) Regardless of the memory configuration of memory element kXl,
Something to scan sequentially, e.g. any number d
A method in which scanning is performed by changing X and Y every ', f' is simply called a sequential scan method.

(8th example) When scanning randomly in (7th example) or (4th example)
Even in this case, if memory access is not performed for all combinations of X and Y, it will simply be called a random scan method.

As mentioned above, there are many scanning methods that can be considered, but in addition to these, there is also a read-side memory access, and there are two types of memory access: read-side memory access scan methods and write-side memory access scan methods. It doesn't necessarily match.

Furthermore, in this scanning method, once the read side is determined, X= and Y' accessed on the write side are determined by the processing content of the processor unit 2. Alternatively, the scanning method on the write side may be determined first. In this case, the scan on the read side is determined by the processing content.

Further, the block sizes ' and i' to be accessed on the read side and the write side may be different, and the size of the memory element configuration kxu may be different.

Expanding the contents of the lookup table as follows:
By accessing any number of memory elements simultaneously, the image memory can be accessed in any block size. At this time, the configuration of the memory elements of k)Jl may be set to a number corresponding to the maximum required size of kXu.

Formula (10) is modified to use the following formula.

Y = kN + n (m = o, 1. ..., -1
)x = ljM+m (m=o, 1. ・, u
-t) Y'=KP+p (p=o, t, ..., -
1) X'=LQ+q (ci=o, 1. ・, L-1)
At this time, equation (11) is transformed as follows.

R-n = 'y' y'=-1, o.

y = 0.1, 2, 3, 4. ..., k"-1) q-m
=dan"x'+x x'=-1, O x =0. 1. 2. 3. 4....,
Intersection # -1)...Equation (20) k# has a configuration such that the larger one of k and K is larger than the larger of vertical and L, and when performing image enlargement/reduction processing, it will be slightly Add an explanation.

The image processed in processor unit 2 is KX
When data is written to an image memory composed of L memory elements, and the image memory on the read side is composed of kxf1 memory elements, and the block size actually accessed on the write side and read side is are respectively ″×dand, k′xdan′ (1≦k ”
As mentioned above, in the case of ≦, 1≦dan"≦L, 1≦'≦, 1≦cross'≦, the chip enable control of the memory element as shown in FIG. 15 can be performed. .

When enlarging/reducing processing is performed, k'', tachi'hani'.

Although it varies depending on the view, the maximum vertical and horizontal magnification is α,
When β is assumed, it can be easily inferred from the above explanation that it is sufficient to set KXL memory elements so that K≧α and L≧β statement ' and L≧β statement' are satisfied.

At the same time, k″1 sentence “Hani”≧αN′.

As long as it is the minimum integer that satisfies the condition ``≧β statement'', it is sufficient to set `` and `` to the minimum integer that satisfies the above conditions, depending on the vertical and horizontal expansion rates α and β, using, for example, a lookup table. Also, as shown in Fig. 15, ', l' and k''
, x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x may be might be set. ”. That is, by adding a means for manipulating the chip enable of the memory element, the area size of the block accessed by reading and writing can be varied.

[Second embodiment] kx4 for accessing kx, Q data at the same time
A second example of allocating image data to one memory element will be described.

FIG. 16 is a diagram showing a state in which the information on one screen of an image has been rewritten into data, which is divided horizontally into equal parts and vertically into equal parts. At this time, for explanation, the area divided into kx sentences is (0,0), (0,1), ... (0
,or),···.

(If k, u>, each area is allocated to each memory element 1b as shown in FIG. 17.

The allocation method is to allocate the dashed diagonal part shown in FIG. 16 to address O of each memory element 1b, then allocate the adjacent image data to address 1 of each memory element 1b, and do the same in the same way. When all the lines in the area have been allocated, the second line is allocated from left to right in the same way, and all the image data is allocated. Then, when the addresses given by the row address generator 4 and column address generator 5 shown in FIG. 4 are all the same for all kxu memory elements 1b,
As shown in the shaded area shown in FIG. 16, discrete image data can be accessed at once.

By adopting such a configuration, it is possible to specify a certain address, read the memory element 1b, and after processing in the processor unit 2, change the address when writing to kXJJ memory elements 1b. There is a possibility that data can be written without any problems.

For example, as shown in FIG. 16, when the area is composed of KXL image data, a portion of one screen of the image may be moved by an integral multiple of L in the horizontal direction and an integral multiple of K in the vertical direction. When performing processing such as transfer, the read address and write address may be the same. For this purpose, a row address generator 4. The load on address control such as the column address generator 5 is extremely reduced.

Processing of movement and transfer is performed in the processor unit 2. As shown by dashed diagonal lines in FIG. 16, the processor unit 2 is input with kx1 image data, that is, image data covering the entire screen, and each piece of data is input in the horizontal and vertical directions. Since the displacement is an integer multiple of , it is sufficient to exchange or move kx1 pieces of data within the processor unit 2 and process all addresses of the memory element. As a result,
It takes a lot of processing to cover the entire screen.

In the case of this second embodiment as well, as shown in the conceptual diagram of transferring the image in area A to area B shown in FIG.
In kxJJ memory elements 1b, a certain 1
When an address is given, the data at the corresponding position is read out one by one from each area divided into ki, and the processor unit 2 rearranges all the kx statement communication data and writes it to the same address where it was read. and kx
One of the j areas has completed the transfer process. When the processor unit 2 executes this for all addresses of the memory element 1b, processing of all images is completed.

However, processor unit 2 must return one kx to memory element 1b. However, in reality, if the processor unit 2 accepts as many areas as there are areas in area A and outputs as many areas as there are areas in area B, the burden on the processor unit 2 will be lightened. However, the number of areas in area A and area B is not necessarily equal.
For example, area A consists of a 3×3 area, which is reduced to 2/3 by processor unit 2,
It is also possible that the data is transferred to area B, which is composed of a 2×2 area.

In this way, if you do not necessarily need the read/write data for all memory elements 1b, that is, to mask the memory that you do not want to write to, use the same configuration as shown in Figure 15 to set chip enable for all memory elements 1b. All you have to do is control. In this case, the data at the input ends of the two lookup tables may be information regarding the vertical and horizontal sizes of area A and area B and the position of the areas.

Next, a description will be given of how to access the memory elements and process all the image data corresponding to the entire screen in the case of the second embodiment, that is, how to scan the access of all the memory data.

For example, the end point U of the adjacent kxR block to be accessed
If Y and X are determined, the position address of , that is, the number when counting from the end in the vertical direction starting from O, is Y, and the number when counting from the end in the horizontal direction, starting from 0, is X. We have already explained how to access the memory. Now, an example of how to scan these X and Y in order to process all images will be explained.

When one screen is divided into dan×sentence areas, each area corresponds to each memory element, so image 1
To scan the screen, all you have to do is give the same address to each memory element and increment the address sequentially starting from address 0. Since the memory element address has a column address and a row address, both the column and row are first set to 0, and the column is incremented from O to the final address. After that, the row address is incremented, and then the column is incremented again from O to the final address. This is repeated to access all memory elements.

Separately, there are memory accesses on the read side and memory accesses on the write side after processing in the processor unit, and there are two types of memory access: the scan method for read-side memory accesses and the scan method for write-side memory accesses. It doesn't necessarily match. Also, the block size to be accessed on the read side and the write side is
' may be different, memory element configuration kXA
The size may be different.

As explained above, according to this embodiment, the block size to be accessed from the read-side memory and the write-side memory can be changed according to the scaling factor during image scaling processing, etc. You can make settings.

Furthermore, if the memory element access method of this embodiment is applied, when the processing performed by the processor unit can perform multiple types of processing, the image accessed by the read side and the write side can be changed depending on the processing content to be executed. Since the area size can be changed, it has become possible to handle a variety of processing by the processor.

[Effects of the Invention] The present invention provides an image processing device that performs image processing at high speed regardless of the size of a processing area.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the configuration of the image processing device of this embodiment, Fig. 2 is a diagram showing how one screen of images corresponds to the address of a memory element, and Fig. 3 is a diagram showing a memory consisting of 4 x 4 memory elements. Figure 4 is a diagram showing the entire memory and the address generator given to it. Figure 5 is a diagram showing a part of the image. Figure 6 is a diagram showing the memory allocation for a part of the image. Figure 7 is a diagram of the memory address. A diagram showing the control circuit, FIG. 8 is a block diagram of pixel data control, FIGS. 9(a) and (b) are diagrams showing the configuration of another image processing device of this embodiment, and FIG. 10 is a single image screen. Figure 11 is a diagram showing kx,Q memory elements, Figures 12 and 13 are diagrams showing one memory element, Figures 14 and 15 are memory element access Fig. 16 is a diagram showing one image screen, Fig. 17 is a diagram showing kxJ1 memory elements, and Fig. 18 is a conceptual diagram of transferring an image in area A to area B. be. In the figure, 1...image memory, Ia, Ib...memory
Element, 2... Processor unit, 2a...
・Processor element, 3... Peripheral part, 4...
Row address generator, '5... Column address generator, 91... Input end image memory, 92
...Processor unit, 93...Output side image memory, 94...Control circuit, 95...Input device, 9
6... Output device, 151, 152... Lookup table. Patent applicant: Canon Co., Ltd. [2, 4. -5
--i Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6/IJ %J Figure 9 Figure 10 Figure 17-7661

Claims (9)

[Claims] (1) An image memory consisting of a plurality of memory elements that can be accessed by specifying addresses independently of other memories, and a plurality of processors smaller than the memory elements.
The image forming apparatus is characterized by comprising: a processor unit which is made up of elements and which simultaneously processes a plurality of pixels in the image memory; and an address control means which controls an address in accordance with the size of a unit processing area in the image memory. Image processing device. (2) A patent characterized in that the image memory is such that pixel data in adjacent predetermined areas are allocated to the same location, and pixel data corresponding to the same position on the predetermined area is allocated to the same memory element. An image processing device according to claim 1. (3) In the image memory, pixel data in adjacent predetermined areas are allocated to the same memory element, and pixel data corresponding to the same position on the predetermined area are allocated to the same location. An image processing device according to claim 1. (4) The image processing apparatus according to claim 1, wherein the processor unit moves an image. (5) The image processing apparatus according to claim 1, wherein the processor unit converts an image. (6) An image memory consisting of a plurality of memory elements that can be accessed by specifying addresses independently of other memories, and a plurality of processors whose number is smaller than the number of memory elements.
a processor unit that simultaneously processes a plurality of pixels in the image memory; an address control means that controls an address in accordance with the size of a unit processing area in the image memory; and a chip of the memory element. An image processing apparatus comprising: enable control means for controlling enable. (7) A patent characterized in that the image memory is such that pixel data in adjacent predetermined areas are allocated to the same location, and pixel data corresponding to the same position on the predetermined area is allocated to the same memory element. An image processing apparatus according to claim 6. (8) A patent characterized in that the image memory is such that pixel data in adjacent predetermined areas are allocated to the same memory element, and pixel data corresponding to the same position on the predetermined area is allocated to the same location. An image processing apparatus according to claim 6. (9) The image processing apparatus according to claim 6, wherein the processor unit scales the image.