JPS63204587A - Bubble memory cassette device - Google Patents

Abstract

PURPOSE:To efficiently assign page address spaces in spite of a change in the storage capacity of a bubble memory cassette by providing a master holder with a holder selecting function and assigning page address spaces starting from the same page address to respective holders. CONSTITUTION:Respective holders 17-20 are selected by a holder specifying means 26 in the master holder 17 and holder selecting means 27-30. Consequently, the page address spaces starting from the same page address can be assigned to respective holders 17-20 on the basis of a page address specifying signal 36, the page address space of each holder can be expanded and the load of a control circuit 25 can be reduced. Even if the storage capacity of the bubble memory cassette to be loaded to each holder is changed, the space corresponding to the storage capacity can be secured always from the same page address, so that a bubble memory cassette device having master interchangeability can be designed.

Description

Detailed Description of the Invention [Summary] The present invention provides a mask/slave type bubble memory capsent device having a means for specifying one of the holders in the master holder, and assigning the master to the corresponding holder. By having a means for selecting a page address designation signal and a control signal from a control circuit in the holder, the page address space allocated to each holder from the control circuit is a page address space starting from the same page address, thereby This bubble memory cassette device is capable of flexibly responding to changes in the storage capacity of bubble memory cassettes attached to each holder.

[Industrial application field]

The present invention relates to a mask/slave type bubble memory cassette device, and more particularly to a bubble memory cassette device that can efficiently allocate page address space even when the storage capacity of the bubble memory cassette attached to each holder changes. .

[Conventional technology]

A bubble memory storage device is an auxiliary storage device using a magnetic bubble storage method, and has advantages over conventional floppy disk devices such as no mechanical operating parts, high speed, and relatively large capacity. Especially recently, by making bubble memory into a cassette and making it freely removable,
Storage devices with excellent operability have been developed. Furthermore, there are bubble memory cassette devices that include a plurality of cassette holders in order to freely select and access a plurality of bubble memory cassettes.

FIG. 5 is a block diagram of a conventional mask-slave type bubble memory capsent device. Each holder has a control circuit 9
and a master holder 1 having a drive circuit 5 and a drive circuit 6 to
The bubble memory cassette installed in each holder is independently driven. The drive circuits 5 to 8 of each holder are
Controlled by a control signal lO from a control circuit 9 in the master holder, and accessing the bubble memory cartridges attached to each drive circuit 5 to 8 by each page address designation signal 11 to 14 from the same circuit, Input/output data 15 is exchanged with the control circuit 9. Further, the control circuit 9 exchanges data, addresses, and various control signals with the host via the interface bus 16.

In the conventional example described above, the bubble memory cassette attached to each of the holders 1 to 4 stores information in a page-by-page block configuration in which one page is made up of a plurality of bits (for example, 256 bytes). Now each bubble memory cassette is about 1
Assume that it has a storage capacity of M bytes and can be accessed in page units of 1 page = 256 bytes each. Therefore, each bubble memory cassette has a page address of 4000 pages in hexadecimal, that is, 40008 pages (H represents a hexadecimal number; the same applies hereinafter).

If the control circuit 9 is capable of accessing page addresses for 4 Mbytes, then in order to enable parallel access to each holder 1 to 4 from the host, the page address for each holder 1 to 4 must be As shown in FIG. 6, a unique page address space of 1 Mbyte is allocated to each page. In other words, the maximum number of pages that can be accessed by one control circuit 9 is divided and allocated to a plurality of holders.

[Problem that the invention seeks to solve]

However, in the conventional example described above, if the storage capacity of the bubble memory cassette increases with the advancement of memory elements, it is conceivable that the page address space for all holders will exceed the maximum number of pages of the control circuit 9. In such a case, the control circuit 9 itself must be redesigned, and the page address space shown in FIG. 6 must be redivided according to the storage capacity of each bubble memory cassette. had. In order to solve this problem of upward compatibility, each folder 1~
If a large page address space is set aside for 4, when a bubble memory cassette with a small storage capacity is used, there will be a problem that unused page addresses will be generated and the page address space cannot be used efficiently. was.

In order to solve the above problems, the present invention provides a master holder with a function of selecting one of a plurality of holders, thereby allocating a page address space starting from the same page address to each holder. It is an object of the present invention to provide a bubble memory socket device that can efficiently allocate a page address space in response to changes in the storage capacity of bubble memory sockets attached to each holder.

[Means for solving problems]

In order to solve the above problems, the present invention has a basic configuration shown in FIG. 1. Each holder includes a master holder 17 consisting of a control means 25, a holder designation means 26, a holder selection means 27, and a drive means 21, and a pair of holder selection means and drive means 28, 22, 29, and 23, 30, respectively. 24 and slave holders 18, 19, and 20.

A control means 25 in the master holder supplies a control signal 35 and a page address designation signal 36 to each drive means 21 to 24 via holder selection means 27 to 30 in each holder, and also exchanges input/output data 37. I do. The holder designation means 26 in the master holder supplies holder designation signals 31 to 34 to the holder selection means 27 to 30 in each holder, respectively.

A data bus 38 and an address bus 39 are connected from the host to the control means 25 and holder designation means 26 in the master holder.

[For production]

In the bubble memory cassette device having the configuration shown in FIG. 1, a designated holder number is given from the host to the holder designating means 26 in the master holder 17 via the data bus 38 and address bus 39. The holder designation means 26 activates one of the holder designation signals 31 to 34 corresponding to the holder number.

As a result, one of the holder selection means 27 to 30 in each of the holders 17 to 20 is turned on. As a result, the control signal 35 and page address designation signal 36 from the control means 25 are inputted only to the drive means corresponding to the above-mentioned holder number among the drive means 21 to 24, and are activated to activate the attached bubble. The memory cassette is accessed and input/output data 37 is exchanged.

According to the above method, each holder 17 to 20 is selected by the holder designation means 26 and the holder selection means 27 to 30, so that the page address designation signal 3 is sent to each holder 17 to 20.
6 makes it possible to allocate a page address space starting from the same page address, eliminating the need to divide the page address space for each holder as in the conventional example, and allowing a wide page address space per holder to be controlled. The load on the circuit 25 can be reduced. Even if the storage capacity of the bubble memory cassette installed in each holder changes, it is only necessary to always secure the space equivalent to the storage capacity from the same page address, making it possible to use a bubble memory cassette device with upward compatibility. can be designed.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail.

(Configurations of Holder Designation Means and Holder Selection Means (FIGS. 2 and 3)) First, the overall configuration of the bubble memory capsent device in this embodiment is the same as that in FIG. 1. Next, Figure 2 shows the first
It is a block diagram of the holder designation means 26 of a figure. A data bus 38 (see FIG. 1) from the host is input to a latch circuit 40, and its output is input to a decoder circuit 41. The decoder circuit 41 outputs holder designation signals 31 to 34 (see FIG. 1). Further, the output of the launch circuit 40 is input to the gate circuit 42, and the output thereof is output to the host via the data bus 38. On the other hand, the address bus 39 (see FIG. 1) from the host is input to a decoder circuit 43, and its output is input to the first input of AND circuits 44 and 45. A write signal 46 (not shown in FIG. 1) is input from the host to a second input of the AND circuit 44, and the output of the AND circuit 44 controls the launch circuit 40. Further, the second input of the AND circuit 45 receives a read signal 47 from the host.
(not shown in FIG. 1) is input, and the output of the circuit 45 controls the gate circuit 42. Note that all of the above circuits operate in negative logic.

The gate circuit 42 is composed of 3-state buffers 48-1 to 48-n as shown in FIG.
9-1 to 49-n correspond to each bit output of the latch circuit 40 in FIG. 2, and outputs 50-1 to 50-n in FIG.
This corresponds to each bit of the data bus 38 in the figure. Also, the third
The control signal line 51 in the figure corresponds to the output of the AND circuit 45 in FIG.

Next, the holder selection means 27 to 30 in FIG. 1 are constituted by 3-state buffers 48-1 to 4-n shown in FIG. 3, similar to the gate circuit 42 in FIG.
9-1 to 49-n correspond to each bit of the control signal 35 and page address designation signal 36 in FIG. 1, and outputs 50-1 to 50-n in FIG. ~2
Corresponds to the output to 4. In addition, the control signal line 51 in FIG.
correspond to each holder designation signal 31 to 34 in FIG. Note that the number n of input and output points may be different from that of the gate circuit 42 (FIG. 2).

(Operation of the embodiment of the present invention (FIGS. 1 to 4)) Next, the operation of the above embodiment will be explained.

First, the host program writes the number of the folder to be accessed into the data register area in the host. Next, when the host specifies the address of the data register area, the holder number is output to the data bus 38. On the other hand, the address of the data register area outputted to the address bus 39 is inputted to the decoder circuit 43 shown in FIG. The decoder circuit 43 activates its output only when the address is input. And write signal 4 from host
By inputting 6, the output of the AND circuit 44 becomes active, and the holder number is latched in the launch circuit 40.

Next, the output of the latch circuit 40 is input to the decoder circuit 41, and the signal corresponding to the holder number among the holder designation signals 31 to 34 becomes active. For example, if the slave holder 18 is designated in FIG. 1, the holder designation signal 3
2 becomes active. Since the corresponding holder selection means 28 has the configuration shown in FIG. 3, when the control signal line 51 becomes active in FIG. 3, the three-state buffers 48-1 to 48-n are turned on, and the input 49-1~
The same state as 49-n is transmitted to outputs 50-1 to 50-n. As a result, the control signal 35 and page address designation signal 36 from the control means 25 in the master holder are input to the drive means 22 of the slave holder 18 shown in FIG. Since the holder designation signal is not active in the holder selection means of the other holders, the three-state buffer of FIG. 3 separates the inputs 49-1 to 49-n and the outputs 50-1 to 50-n. According to the holder number input from the host through the above operation, the control signal 35 from the control means 25 in the master holder and the page address designation signal 36 are input only to the driving means of the corresponding holder.

Further, when the host wants to know the holder number currently being accessed, the read signal 47 shown in FIG. 2 is activated. As a result, the output of the AND circuit 45 becomes active, and the gate circuit 42 is turned on. As a result, the holder number latched in the latch circuit 40 is output to the host via the data bus 38.

In the above operation, each holder 17 to 20 is specified from the data register of the host via the holder specifying means 26 in the master holder 17 (Fig. 1), so the page address space is divided between each holder. This is no longer necessary, and the page address designation signal 36 designated by the control means 25 can be assigned to each holder from the same page address 00008 as shown in FIG.

Currently, the storage capacity of the bubble memory cartridges attached to each holder 17 to 20 is approximately 1 MB each, and 1 page = 256.
If the page address space that can be accessed by the control means 25 is 4M bytes, each holder has a margin of 3M bytes, as shown in FIG. Therefore, the bubble memory cassette can expand its storage capacity to 4 Mbytes, and can use the page address space much more efficiently than the conventional example shown in FIG.

When the above expansion is performed, it is only necessary to change the usage range setting on the host side, and high upward compatibility can be maintained.

〔Effect of the invention〕

According to the present invention, by providing the master holder with a holder selection function, it is possible to allocate a page address space starting from the same page address to each holder, and the number of pages per holder is reduced compared to the conventional example. This allows for a wider page address space. Even if the storage capacity of the bubble memory cassette installed in each holder changes, it is only necessary to always secure the necessary page address space from the same page address, so there is no need to change the address format, and high-level Compatibility can be maintained.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the bubble memory capsent device according to the present invention, FIG. 2 is a configuration diagram of the holder specifying means 26, and FIG. 3 is a circuit diagram of the gate circuit 42 and the holder selection means 27 to 30. , FIG. 4 is an explanatory diagram of page addresses and space allocation according to the present invention, FIG. 5 is a configuration diagram of a conventional bubble memory cassette device, and FIG. 6 is an explanatory diagram of the operation of the conventional example and its problems. It is. 17... Master holder, 18-20... Slave holder, 21-24... Drive means, 25... Control means, 26... Holder designation means, 27-30... Holder selection means, 31 to 34... Holter designation signal, 35... Control signal, 36... Page address designation signal. Figure 3 Conventional Initial Appointment of I1 and Closing of Sen 2 Intuition 1 Figure 6

Claims (1)

[Claims] 1) One master holder (17) having means (21) for driving the bubble cassette and means (25) for controlling said means, and controlled by the control means (25) in said master holder. Bubble cassette driving means (22, 23, 24)
one or more slave holders (18, 19, 20
), wherein the bubble memory cassette device is provided in the master holder (17) and is connected to the master holder (17) or slave holders (18, 19, 20).
) holder designating means (26) for designating one of the plurality of holders of the master holder (17) and each slave holder (18);
, 19, 20), and the holder designation means (2
6) Holder designation signal (31, 32, 33, 34) from
holder selection means (27) for selectively inputting the page address designation signal (36) and control signal (35) from the control means (25) in the master holder to each drive circuit (21, 22, 23, 24); , 28, 29, 30). 2) The bubble memory cassette is loaded into the drive means (21) in the master holder or the drive means (in each slave holder) by the page address designation signal (36) from the control means (25) in the master holder. 22
, 23, 24), wherein the page address space allocated to the bubble memory cassettes installed in the holders is a page address space starting from the same page address between each holder. Memory cassette device.