JPS63204353A - Common bus coupling system - Google Patents

Abstract

PURPOSE:To efficiently perform data transfer at the time of coupling buses with a few amount of delay, by changing the priority order of a bus occupancy request corresponding to the activity status of the bus in a coupling device, and accelerating the data transfer within the range of the bus occupancy ratio of the coupling device set in advance. CONSTITUTION:Both buses (a) and (b) are connected with bus couplers 10a and 10b provided with a counter means 15 which counts an arrival data per unit time, a threshold value holding means 16 which holds a threshold value set in advance, and a comparison means 17. And by changing the priority order of the bus occupancy request from a high order to a low order corresponding to the activity status, the data transfer can be accelerated within the range of the bus occupancy ratio of the bus couplers 10a and 10b. In such a way, it is possible to perform the data transfer efficiently at the time of coupling the buses with simple constitution and with a few amount of delay efficiently.

Description

[Detailed Description of the Invention] [Summary] This is a common bus coupling method in which multiple different types of common buses are coupled by a coupling device, and when data is sent and received between modules connected to the different types of common buses, the common bus In order to solve the problem that bus occupancy becomes longer and its sloop node decreases, the priority of bus occupancy requests is raised or lowered according to the bus usage status of the coupling device, and the bus occupancy rate of the coupling device is determined in advance. By configuring the data transfer to be accelerated within the range of , it becomes possible to efficiently perform data transfer during bus connection with a small delay with a simple configuration.

[Industrial application field]

The present invention relates to a common bus coupling method for coupling a plurality of different types of common buses using a coupling device.

When data is transferred between a plurality of different shared buses via a coupling device (hereinafter referred to as a bus coupler), it is required to transfer data more efficiently.

[Conventional technology]

FIG. 3 shows a block diagram illustrating a conventional example.

FIG. 3(A) shows an example of a common bus coupling method, and FIG. 3(B) shows another example.

In addition, in Fig. 3, different types of common buses (a) and (b) are connected via bus couplers H1) and 1 (2), respectively, and each common bus (a) and (b) has its own Bus occupancy control units 2a and 2b that perform control for using the bus
It is equipped with

3 (A) and (B) both show a central processing unit (hereinafter referred to as CPU) 3 and a mass storage device (hereinafter referred to as MS) 4
This example uses the case where data is transferred between

The bus coupler 1 (1) shown in FIG. 3(A) transfers data via the driver 11 when transferring data from the CPU 3 to the MS 4, and via the driver 12 when transferring data from the MS 4 to the CPU 3. Transfer via.

For example, when transmitting and receiving data through access from the CPU 3, the CPU 3 first requests the bus occupancy control unit 2a to occupy the bus (a), and once the request is granted, the CPU 3 requests the bus occupancy control unit 2a to occupy the bus (a).
b) The bus occupancy control unit 2b is requested to occupy the bus occupancy control unit 2b.

If this request is also approved, the MS4 address will be sent,
Continue to start data transfer. This method is a method in which bus signal lines are directly coupled via a bus coupler 1 (1) and data is directly transmitted and received (hereinafter, this is referred to as the (11 method)).

On the other hand, the method shown in FIG. 3(B) (hereinafter referred to as method (2)) is a method in which a buffer is provided in the bus coupler to temporarily store addresses and data for transmission and reception.

That is, for example, when data is transferred from the buffer 13 from the MS 4 to the CPU 3, the buffer 14 is transferred from the CPU 3 to the MS 4.
The buffers 13 and 14 are used to transfer data to the bus occupancy control units 2a and 2b on the other side, and also transfer requests for occupancy of buses (a) and (bl), addresses, and data.
It will be done through.

In addition, as shown in FIG. 3 (B), ■ and ■ are bus occupancy request/acceptance, ■ are other bus accesses (memory address set), and ■
, ■ indicate address and data transfer, respectively.

[Problem that the invention seeks to solve]

In the case of method (1) shown in Figure 3 (A), when performing data transfer, it is necessary to occupy both buses (a) and (b) at the same time, and the occupation time is long in order to synchronize bus occupation. and throughput decreases.

On the other hand, in the case of method (2) shown in Figure 3 (B), it is not necessary to occupy both buses (a) and (b) at the same time, but buses ta) and (b) on the data receiving side are delayed. For the sake of time
A large buffer 13, 14 is required, which increases cost and propagation time accordingly.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention shown in FIG. 1 includes a counting means (counter) 15 for counting arriving data per unit time, a threshold holding means (threshold value register) 16 for holding a preset threshold value, and a counting means ( Both buses (a) and (b) are coupled by bus couplers 10a and 10b, which are equipped with comparison means (comparison circuit) 17 for comparing the counted value of counter) 15 and the value of threshold value holding means (threshold value register) 16. It is composed of

[Effect]

The priority of the bus occupancy request is changed from high to low according to the bus usage status of the bus couplers 10a and 10b, and the bus occupancy rate range of the bus couplers 10a and 10b (
For example, by configuring the device to accelerate data transfer within a maximum speed of 10 MB/S, it becomes possible to efficiently perform data transfer during bus connection with a small delay with a simple configuration.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 shows a block diagram illustrating the invention in detail. Note that the same reference numerals indicate the same objects throughout the figures.

This embodiment will be explained by taking as an example a case where data transmission and reception between the CPU 3 and the MS 4 described in FIG. 3 are performed via the bus couplers 10a and 10b.

Note that when the bus coverr 10a transfers data from the CPU3 to the MS4, the bus coverr 10b transfers data from the MS4 to the CPU3.
The configuration is the same.

Further, the bus coverrs 10a and 10b have counters 15. Threshold register 16. A comparison circuit 17, a decoder 18 that converts arriving data per unit time into a predetermined signal, a bus buffer 19 that accepts data from buses (a) and (b), and a FIFO method for storing data from the bus buffer 19. When the value of the counter 15 is compared between the six-stage FIFO data buffer 20 that stores the data, the clock generator 21 that generates a predetermined clock signal, and the comparator circuit 17, an over (OVER) signal is generated if the value exceeds the threshold value. The bus occupancy request signal generator 22 generates a bus occupancy request signal.

Next, the operation of this embodiment will be explained using an example in which data is transferred from bus (a) to bus (b).

Data from the bus (a) is accepted by the pass buffer 19 in the bus coupler 10a, and is sequentially transferred to the FIFO data buffer 20 having a six-stage configuration. At this time, the counter 15 counts the number of received data arriving per unit time via the decoder 18.

This count value is received from a threshold register 16 from a resource management module (not shown) that allocates the transfer capacity of the bus ('b).
The count value is compared with a preset threshold value, and when the counted value exceeds the threshold value, the comparison circuit 17 sends an over (OVER) signal to the bus occupancy request signal generation section 22.

The bus occupancy request signal generating section 22 thereby changes the priority of the bus (b) occupancy request to a lower level and makes a request to the bus occupancy control section 2b. It is assumed that there are a plurality of priority levels for normal bus occupancy requests.

Note that the value of the counter 15 is reset at fixed intervals by the clock of the clock generator 21 generated by access from the bus (b).

For example, if the threshold value recently stored in the threshold value register 16 is “
3", when three data from bus (a) arrive within a unit time, the over (0VER) signal is not sent, and even if the bus is occupied with a high priority, the bus (a) side Transfer with less delay is possible within the allocated transfer capacity.

On the other hand, when four pieces of data arrive from bus (a) within a unit time, if they are transferred as is, they will use more than the allocated transfer capacity of the bus (bl side), so an over (0VER) signal is sent. The request for occupying the bus (bl) is changed to a lower priority and processed.

At this time, when the FIFO data buffer 20 becomes full, transfer on the bus (a) side is inhibited by a BUSY response.

Note that the threshold value is set by the resource management modules (not shown) of the buses (a) and (bus 2) communicating with each other to adjust the transfer capacity for each direction of data.

In this manner, by setting the threshold value by a resource management module (not shown) that allocates the transfer capacity of the bus, it is possible to dynamically change the threshold value without impairing the capacity of the bus system.

〔Effect of the invention〕

According to the present invention as described above, data transfer during bus connection can be efficiently performed with a small delay using a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a block diagram explaining a conventional example. In the figure, 1 (1), 1 (2), 10a and 10b are bus coverrs, 2a and 2b are bus occupancy control units, 3 is a CPU, and 4 is an MS. 11.12 is the driver, 13.14 is the buffer,
15 is a counter, 16 is a threshold register, 1
7 is a comparison circuit, 18 is a decoder, 19 is a pass buffer, 20 is a FIFO data buffer, 21 is a clock generator, and 22 is a bus occupancy request signal generator. O (Voiced 8 tufts 3 hairs Σ word relaxing block pro 150

Claims (1)

[Claims] A coupling device (10a,
10b), a counting means (15) for counting arriving data per unit time;
), a threshold value holding means (16) for holding a preset threshold value, and a count value of the counting means (15) and the threshold value holding means (1).
a comparison means (17) for comparing the count value of the counting means (15) with the value of the threshold value holding means (16);
A common bus coupling method characterized in that when the counted value exceeds the threshold, a bus occupation request for data transfer is changed from a high priority to a low priority.