JPS63188783A - Logic analyzer - Google Patents

Abstract

PURPOSE:To analyze a logic waveform flexibly by detecting a fact that a prescribed logic relation holds among input two binary signals to be analyzed for longer time than a prescribed time. CONSTITUTION:A logic relation establishment detection part 10, a time width detection part 20, and an analytic object selection part 30 are provided. Then the detection part 10 detects the setting of a prescribed logic relation among plural input binary signals I1, I2, I3...In to be analyzed and supplies its detection output to the detection part 20. The detection part 20 detects whether or not the logic relation detected by the detection part 10 continuing to prescribed time width and supplies its detection result as a trigger signal TR to the selection part 30. The selection part 30 selects a prescribed input signal to be analyzed among input binary signal groups I1-In to start analyzing the input signal or recording a waveform for subsequent analyses.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a logic analyzer used for testing digital circuits and the like.

Conventional technology Conventionally, logic analyzers used for testing digital circuits detect when a predetermined AND is established between multiple input binary signals to be analyzed, and use this detection output as a trigger for analysis. The target signal waveform is selected.

Problems to be Solved by the Invention The conventional logic analyzer described above determines whether or not to generate an analysis target selection trigger based only on the success or failure of a predetermined logical product. There is a problem with flexibility, such as triggers being applied in certain situations.

Means for Solving the Problems The logic analyzer of the present invention includes a logical relationship establishment detection unit that detects that a predetermined logical relationship is established between a plurality of large value signals to be analyzed, and By including a time width detection unit that detects that a logical relationship has continued over a predetermined time width, and an input signal selection unit that uses the detection output of this time width detection unit as a trigger to select an input signal to be analyzed, the trigger can be It is designed to give flexibility in how it is applied.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a block diagram showing the configuration of a logic analyzer according to an embodiment of the present invention.

This logic analyzer includes a logical relationship establishment detection section 10
, a time width detection section 20 , and an analysis target selection section 30 .

The logical relationship establishment detection unit 10 detects a plurality of large crab value signals 1. ．． I2,1. . . . 11, it is detected that a predetermined logical relationship is established, and the detection output is supplied to the time width detection section 20. The time width detection unit 20 detects whether the logical relationship detected by the logical relationship establishment detection unit 10 continues for a predetermined time width, and sends the detection result to the trigger signal TR.
It is supplied to the analysis target selection unit 30 as The analysis target selection unit 30 selects a predetermined input signal to be analyzed from the human value signal group ■1 to I7 based on the trigger and signal TR from the time width detection unit 20, and starts its analysis. Start recording waveforms in preparation for future analysis.

FIGS. 2 and 3 are block diagrams showing an example of the configuration of the logical relationship establishment detection section 10 and the time width detection section 20 shown in FIG. 1. These circuits have I
, ll2=“1” is established for three clock cycles, the trigger signal TR is generated.

First, as shown in FIG. 2, the logic relationship establishment detection unit 10 detects n logic circuits 11, 12.
It consists of a person and a gate A. In this detection unit 10, i,=l11fl, i2=
"o", 'sl-'s2-"1", Is3~+sn-"
0'' is set.

On the other hand, the time width detection section 20 is composed of m delay flip-flops 21 to 2m, a three-man AND gate A, and a delay flip-flop D, as shown in FIG. t,=j2=t3="0", L4~t,-"1
”, the initial value of the output of the three flip-flops 21 to 23 in the previous stage is set to “0”.
It is preset so that When the detection signal R becomes "1" for a period three times the period of the clock signal CK, the output of the three-man AND gate A becomes "1", and the trigger signal TR output from the delay flip-flop D becomes "1".
1”.

FIG. 4 is a time chart of the generation of the TR signal.

When the signal becomes 1 for a period of three or more cycles of the clock signal CK, the trigger signal TR changes from "0" to "1".

Above, we have exemplified the case where a logical product holds true between two human power figures as a predetermined logical relationship that holds true between input signals, but such a logical relationship can also be a logical product that holds true between two or more input signals. Any value including logical sum may be used.

Effects of the Invention As explained in detail above, the logic analyzer of the present invention detects that a predetermined logical relationship has been established between a plurality of input binary signals to be analyzed over a predetermined period of time, and outputs this detection output. Since the input signal to be analyzed is selected using the input signal as a trigger, it is effective in realizing highly flexible analysis of logic waveforms, such as eliminating transient states at waveform change points.

In particular, this has the effect of making it easier to apply a trigger even when the input signal is dynamically changing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a logic analyzer according to an embodiment of the present invention, FIG. 2 is a logic circuit diagram showing an example of the configuration of the logical relationship establishment detection section 10 of FIG. 1, and FIG. 1
A logic circuit diagram showing an example of the configuration of the time width detection unit 20 shown in the figure,
FIG. 4 is a timing chart for explaining the operation of the logic circuits of FIGS. 2 and 3. 10... Logical relationship establishment detection unit, 20... Time width detection unit, 30... Analysis target selection unit.

Claims (1)

[Claims] A logical relationship establishment detection unit that detects that a predetermined logical relationship is established between a plurality of input binary signals to be analyzed, and that the detected logical relationship continues for a predetermined time width. What is claimed is: 1. A logic analyzer comprising: a time width detection section that detects the time width detection section; and an input signal selection section that selects an input signal to be analyzed using the detection output of the time width detection section as a trigger.