JPS63186457A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a lamination-type semiconductor device wherein the area of an integrated circuit substrate occupied by a wiring region can be reduced, the total module can be miniaturized, and the high speed quality can be improved, by laminating a plurality of semiconductor integrated circuit substrates having a three-dimensional structure wherein wiring patterns for electric connection are formed on the surface, the rear, and the side surface. CONSTITUTION:A semiconductor integrated circuit substrate 10 has a three dimensional structure wherein wiring patterns 13 for electric connection are formed on the surface, the rear and the side surface. A plurality of the substrates are laminated, and wiring connection between each of the substrates 10 is made via the above-mentioned wiring patterns 13. For example, a computer module is constituted by stacking the integrated circuit substrates 10 of wafer scale. The central part of the substrate 10 is assigned to an active element region 11 constituted of memories and logic gates. These integrat ed circuit substrates 10 are stacked in 10-200 stages to realize a computer system. The wiring connection between the substrates 10 is made by mutually connecting the wiring layers 13 formed on the surface, the side surface, and the rear via soldering electrodes 14. Supporting bodies 15 are inserted between the substrates in order to prevent the deformation of the soldering electrodes 14.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, to a semiconductor device with a three-dimensional wiring structure in which wiring patterns for electrical connection are formed on the front surface, back surface, and side surface. The present invention relates to a stacked semiconductor device constructed by stacking a large number of integrated circuit boards, and a method for manufacturing the same.

[Conventional technology]

By stacking a large number of wafer-sized semiconductor integrated circuit boards, a compact computer system with excellent high speed can be realized. Conventional devices, as described in Japanese Patent Application Laid-open No. 51-78176 or No. 60-160645, have a structure in which wiring connections between the boards are made through through holes provided in the integrated circuit board. Also, JP-A-58-3903
As described in No. 0 or Japanese Unexamined Patent Publication No. 58-39036, the structure was such that wiring connections were made all at once on the sides of the substrates after they were laminated. However, these conventional techniques do not take into account miniaturization of a large number of wiring lines, equalization of wiring resistance, and arbitrary selection of connection contacts. Furthermore, sufficient consideration has not been given to reliability, including the mechanical strength of the wiring connection structure in stacked mounting.

Next, Japanese Patent Laid-Open No. 60-214530 and Japanese Patent Laid-open No. 58-56455 are related to a method of manufacturing an integrated circuit board used in a stacked semiconductor device. This conventional technology has two
This method involves exposing the wafer surface for the first time, then removing the substrate from the photomask, rotating it, and then bringing it close to the mask again to perform a second exposure to the side surface. , a photoresist pattern for three-dimensional (two-sided) wiring was formed. As described above, the conventional method targets the two perpendicular surfaces of the wafer, and does not give any consideration to a method of simultaneously exposing the three surfaces including the front surface, side surfaces, and back surface.

[Problem that the invention seeks to solve]

The conventional configuration in which a through hole is formed in an integrated circuit board, a wiring layer is formed on the sidewall of the integrated circuit board, and then the boards are interconnected with each other, does not take into account the increase in wiring density that accompanies the improvement in element integration density. There is a problem in that circuit boards become larger due to higher integration. That is, it is difficult to miniaturize the through holes, and as a result, the occupancy rate of the wiring area increases significantly compared to the element area, resulting in a problem of increasing the size of the substrate.

Further, in the conventional structure, when forming a wiring layer on the side wall of the through hole, the thickness of the wiring layer varies, so there was a problem in making the wiring resistance uniform. Furthermore, the conventional technology does not take into account the mechanical strength of the wiring connection structure when these circuit boards are stacked in multiple layers, and there is a problem with reducing the reliability of the wiring connection due to thermal fatigue. Ta.

Next, the above-mentioned conventional manufacturing method does not take into account the simultaneous exposure method for the three sides of the wafer from the front side to the back side, and requires a complicated process of rotating the wafer substrate. However, there was a practical problem in that it made it difficult to use the normally widely used contact exposure apparatus.

The purpose of the present invention is to solve the above-mentioned problems in the prior art, and to make it possible to reduce the wiring area occupied on an integrated circuit board.
To provide a stacked semiconductor device that allows the entire module to be miniaturized and to improve speed.
Another object of the present invention is to provide a manufacturing method that can easily form a wiring pattern on three surfaces of a substrate, ie, the front surface, back surface, and side surface, using a contact exposure method.

[Means for solving problems]

The above purpose is to stack a plurality of semiconductor integrated circuit boards having a three-dimensional wiring structure in which wiring patterns for electrical connections are formed on the front, back, and side surfaces, and to connect the wiring between each integrated circuit board using the wiring patterns. In addition, as a manufacturing method, a substrate on which a photoresist film is formed on each required part of the front surface, back surface, and side surface is supported by a holder having a light reflecting function part around the periphery, and then a mask is applied. This is achieved by a method including a step of simultaneously exposing the photoresist film by irradiating the surface of the substrate with light through the light reflecting function section and irradiating the side and back surfaces of the substrate with light reflected from the light reflecting function section. Ru.

Conventional means for forming through holes generally include mechanical grinding and chemical etching. However, these means have limitations on processing accuracy and require a high level of technology. Therefore, in the present invention,
In order to enable wiring connections between boards without creating through holes, a method was developed to extend the wiring layer, which was conventionally formed only on the top surface (active element surface) of the board, to the bottom surface via the side surface. Adopted.

[Effect]

By adopting a method that uses an integrated circuit board with a three-dimensional wiring structure instead of using a through-hole method, the patterning of the wiring resistance layer to be formed can be realized using simple photolithography technology, making it possible to obtain a highly accurate wiring pattern. Can be done. In particular, since the step of providing a conductive layer in the through hole is not necessary, the conductive layer can be easily formed and the film thickness can be uniform.

Furthermore, since the wiring pattern dimensions can be accurately controlled, a wiring layer with uniform resistance can be realized. Furthermore, since the electrode spacing can be significantly reduced compared to the through-hole method, the occupation rate of the wiring area can be kept low, making it possible to downsize the integrated circuit board. At the same time, since there are no through holes in the plane of the substrate, the wiring layout of the wiring layer can be simplified and the wiring density can be increased. When making wiring connections between multiple boards, if you form solder electrodes on the top surface of one integrated circuit board in advance and stack other boards on top of this, the top surface of the board can be Wiring connections between arbitrary electrodes can be made by changing the configuration pattern of the solder electrodes formed.

When stacking multiple boards, a considerable amount of load is applied to the solder joints due to the board's own weight, but if a support is inserted separately between the boards, this load will be reduced. By being supported by the support body, a load on the solder connection electrode portion can be avoided.

Next, according to the method for manufacturing a three-dimensional wiring structure of the present invention, the light reflecting function portion provided in the holder operates to guide a part of the vertically incident light to the wafer to the side and back surfaces of the wafer,
Thereby, a predetermined portion from the front surface of the wafer to the back surface via the side surface can be exposed simultaneously to form a wiring photoresist pattern.

〔Example〕

The present invention will be explained in detail below.

First, an embodiment of the configuration will be described using FIGS. 1 to 4. 1 and 2 are diagrams showing the principle of the present invention. 1st
As shown in the figure, a computer module is constructed by stacking wafer-scale integrated circuit boards 10. The center of the integrated circuit board 10 is an active element area 11 consisting of memory and logic gates, and such an integrated circuit board is
A computer system can be realized by stacking 0 to 200 layers. Wiring connections between the boards are performed by interconnecting wiring layers 13 formed on the top, side, and bottom surfaces of the circuit boards. FIG. 2 is a schematic diagram of a plurality of stacked integrated circuit boards 10, in which interconnections of the circuit boards are electrically connected by solder electrodes 14. Further, a support 15 is inserted between the substrates to prevent deformation of the solder electrodes.

3 and 4 show WSI (Wafer) according to the present invention.
This figure shows a stacked module (scale integration). FIG. 3 shows a wafer scale CMO8 integrated circuit board 20 with logic gate element area 21 (gate at 2043) and memory element area 22 (byte x 40 at 64).
It consists of an active element region consisting of X4) and a wiring region 23. After cutting the wafer following the CMOS process, the top surface of the wafer is
Wiring patterning on the side and bottom surfaces was performed at once by the method described below. Next, a protruding solder electrode 24 was formed on the upper wiring electrode. Here, the configuration pattern of the solder electrodes was changed for each circuit board according to the wiring route. The solder electrodes were formed using either selective vapor deposition of solder metal or ball-shaped solder material supply, and the height of the solder electrodes was controlled by controlling the amount of solder and controlling the dimensions of the underlying wiring electrodes. Next, as shown in FIG. 4, a support 25 having a height slightly lower than the height of the solder electrode 24 is inserted between the boards, and the solder material deposited on both sides of the support 25 is welded to form an integrated circuit board. 20 mutual adhesion was performed. The solder melting point of the former was set to be higher than that of the latter so that the solder melting and bonding of the support 25 and the mutual solder melting of the substrates could be performed at the same time.

According to the configuration of this embodiment, since a three-dimensional wiring area is provided around the integrated circuit board, it is possible to reduce the wiring area, thereby making it possible to reduce the capacity of the entire module, and also to Since the configuration pattern of the solder electrodes can be changed arbitrarily, the wiring route between wafers can be freely controlled.

Next, an embodiment of the manufacturing method of the present invention will be described with reference to FIGS. 5 to 9. FIGS. 5(a) and 5(b) are diagrams illustrating the principle of a method for manufacturing a substrate with a three-dimensional wiring structure according to the present invention. FIG. 5(a) shows that a rectangular wafer substrate 101 (a photoresist film 102 is formed on a predetermined portion of its exposed surface) is attached to a vacuum hole 104 (in the direction of the arrow) provided approximately in the center of a wafer holder 103. It shows a state in which the component is placed on top of the device (which is evacuated to . FIG. 5(b) shows a portion of the vertically incident light 107 (indicated by an arrow) on the photomask 106.

As is clear from FIG. 5, which shows a state in which the light is guided into the light reflecting function section 105 and reflected by the light reflecting surface 108, and a part of the side and back surfaces of the wafer substrate 101 are exposed, the method of the present invention For example, a predetermined area from the front surface of the wafer substrate 101 to the back surface via the side surface can be easily exposed all at once in close contact.

Hereinafter, several points in implementing the method of the present invention will be explained in detail.

Photoresist agent A
1350 (manufactured by Silapray) was applied to a thickness of 2 to 4 p using both a dipping method and a spinner rotation method. In general, the spin coating method tends to increase the resist thickness around the wafer, but a method of optimizing the viscosity of the resist agent and changing the spinner rotation speed from high to low speed was effective in making the film thickness uniform. The dipping method was effective for applying the resist agent to the side surfaces.

As shown in FIG. 6, the light reflection function section 105 is a triangular prism-shaped quartz prism 201 with a portion cut away. In order to actually manufacture this prism, prepare in advance the quartz prisms in the (a) and (b) parts divided along the line A-A' in Figure 6, and select the desired stripe pattern (material After forming Cr) 202 by a normal contact exposure method, each was coated with an ultraviolet curing adhesive (product name:
Norland Optical Adhesive
61) was used to bond and integrate. The light reflecting surface 108 was formed by depositing AQ.

FIG. 7 shows a total of 4 integrated quartz prisms 201 as described above.
5 is shown mounted on a wafer holder 103 (corresponding to the view seen from above, excluding the wafer substrate 101 and photomask 106 in FIG. 5).

FIG. 8 is a plan view of the photomask 106 shown in FIG.
A pattern (made of Cr) 403 is formed. dashed line 4
The area surrounded by 02 corresponds to the integrated circuit section 502 described in FIG.

As described above, by using the parts and construction methods shown in FIGS. 6, 7, and 8, three-dimensional three-dimensional exposure using the contact method shown in FIG. 5 was realized. FIG. 9(a) shows a 5i-WSI wafer 501 on which three-dimensional wiring was performed according to this embodiment.
5 is an external view of a striped AD extending in all directions from an integrated circuit section 502.

As shown in the enlarged cross-sectional view of FIG. 9(b), the wiring 4@503 is formed continuously through the side surface of the wafer to a required portion of the back surface. AQ wiring was formed by exposing and developing a photoresist film to form a stripe pattern, then vapor depositing AQ, and then removing the resist agent by a lift-off method. FIG. 9(c) shows an application example of the present invention in which the 5L-WSI wafers 501 are stack-mounted, and signal transmission between wafers is made possible by wiring connections using solder bumps 503.

According to this example, three three-dimensional surfaces (front, side, and back surfaces) of a wafer substrate can be exposed at once, making it easy and simple to perform three-dimensional wiring of three-dimensionally mounted devices, including stack mounting of wafers. It can be achieved through the process, so it is technically
The economic effect is extremely large.

Note that although the quartz prism 201 is used in the light reflecting function section 105 in the above embodiment, a light reflecting mirror may simply be used instead. That is, the V-groove portion (the portion that holds the quartz prism) of the wafer holder 103 in FIG. 5 may be mirror-finished. However, in this case, the exposure pattern for the side and back surfaces of the wafer is formed on the photomask 106, so it is not a perfect contact exposure and is a method that is somewhat unsuitable for forming fine patterns. Compared to the method of the above embodiment in which the prisms are prepared in advance, the process is simpler and the method is economically effective.

Furthermore, in the embodiments described so far as a method for manufacturing a three-dimensional wiring structure, a case has been described in which wiring patterns are formed on three sides of a semiconductor wafer all at once. It can also be applied to the formation of wiring for carrier (carrier) elements. That is, in an LCC element, external connection terminal lines are formed on the side surface of the chip, but according to this manufacturing method, the wiring pattern on the chip surface and the external connection terminal line on the side surface are formed in a continuous manner at once. can do.

〔Effect of the invention〕

According to the laminated integrated circuit configuration of the present invention, the side surface of the integrated circuit board can be used as a wiring route in the laminated mounting of a wafer-scale integrated circuit, so the wiring area occupied on the integrated circuit board can be reduced, and therefore the integrated circuit board The reduction in dimensions has the effect of reducing the total capacity of the mounted module.

Furthermore, according to the three-dimensional wiring structure manufacturing method of the present invention, contact exposure can be performed on three three-dimensional surfaces of the wafer, namely the front, side and back surfaces, at once, and the process of forming wiring patterns on the three three-dimensional surfaces can be greatly simplified. It can be simplified and shortened, and has great technical and economical effects in realizing stack mounting of wafers. Further, since the wiring layer processing process can be carried out using ordinary photolithography technology, pattern processing accuracy is excellent and miniaturization is easy. Therefore, the controllability of the wiring resistance is also good, which is effective in improving the performance of the mounted module. On the other hand, the present three-dimensional wiring method does not require processing processes such as forming through holes, and is also effective in terms of process simplification and economic efficiency. Furthermore, by using solder material to connect the wiring between the boards and by inserting a support to create a structure that is stable in terms of mechanical strength, it is effective to improve the reliability of the entire module.

The present invention is effective for mounting not only a stack module in which wafers are mounted three-dimensionally but also a planar module in which wafers are arranged two-dimensionally.

[Brief explanation of the drawing]

FIG. 1 is a perspective view illustrating the present invention in detail, FIG. 2 is a side view, FIG. 3 is a plan view of an embodiment of a wafer-scale CMO3 integrated circuit board of the present invention, and FIG. 4 is a WSI stack according to the present invention. A perspective view of an embodiment of the module, FIGS. 5(a) and 5(b) are explanatory diagrams of the principle of the manufacturing method of the present invention, FIG. 6 is an explanatory diagram of the light reflection function part in FIG. 5, and FIG. The block diagram of the wafer holder in the figure, FIG. 8 is a plan view of the photomask in FIG.
Figure (a) is an external view of an example of a three-dimensional wiring wafer according to the present invention, (b) is a cross-sectional view taken along line AA' thereof, and (Q) is a cross-sectional view showing an example of a stacked state. Explanation of symbols 10... Integrated circuit board 11... Active element region 13... Wiring layer 14.24... Solder electrodes 15, 25... Support body 101... Wafer substrate 102... Photoresist Film 103...Wafer holder 1'05...Light reflection function section 106...
Photomask 107...Vertical incident light 108...
Light reflecting surface 201...Quartz prism 202...Mask pattern 501...5i-WSI wafer 503...AQ Wiring Representative Patent Attorney Junnosuke Nakamura 1 To Figure 11 - Active cable length ρf. Spear 3 Illustration 5 (Q) 102-・Nemu register l-哄(b) 103-'>"Pa1"'2". 1[]6 +08--Ichishi projection surface 26 Figure 202-・Mass 2 no? Cooleo 7 Figure 108--Ikkou and Kushunmen nl +06--Hotomasu 401--Rokueha Kikuaiken 402--Ikkou nkou route barge Q relative

Claims (1)

[Claims] 1. A plurality of semiconductor integrated circuit boards having a three-dimensional wiring structure in which wiring patterns for electrical connection are formed on the front, back, and side surfaces are stacked, and there is a gap between each integrated circuit board. A semiconductor device characterized in that wiring connections are made via the wiring pattern. 2. The wiring connection between the semiconductor integrated circuit boards having the three-dimensional wiring structure is made by connecting the wiring pattern formed on the lower surface of the upper layer substrate and the wiring pattern formed on the upper surface of the lower layer substrate using a solder material. The semiconductor device according to claim 1, characterized in that the semiconductor device is made by: 3. The stacking of the semiconductor integrated circuit boards having the three-dimensional wiring structure is carried out through supports arranged between each board separately from those for electrical connection. A semiconductor device according to scope 1 or 2. 4. A substrate on which a photoresist film is formed on the required portions of the front, back, and side surfaces is supported by a holder that has a light reflection function around it, and then light is irradiated onto the surface of the substrate through a mask, and the light reflection function described above is applied. A semiconductor integrated circuit having a three-dimensional wiring structure, comprising the step of irradiating the side and back surfaces of a substrate with light reflected from the substrate to simultaneously expose the photoresist films formed on the front, back, and side surfaces. Substrate manufacturing method.