JPS63175266A - Sound signal processor - Google Patents

Abstract

PURPOSE:To restore the original voice information when the voice information is compressed for transmission or record/reproduction, by reading out successively plural frames by each coefficient data to transmit or record them in the form of the voice information scattered among those frames. CONSTITUTION:Plural frames are stored in a 2-frame memory 7 for each unit including the prescribed number of frames of the voice information subjected to the orthogonal conversion and the adaptive quantization. Then those frames are read successively out of the memory 7 for each coefficient data and transmitted or recorded in the form of the voice information where the coefficient data are scattered among the frames. At the reception side or in a reproduction system, the voice information processed scatteringly is divided for each frame and the coefficient data having errors in each frame are scattered. Thus the original voice information can be restored easily and accurately and the reproduced voices have no abnormality even when the error occurring in the coefficient data under transmission can not be corrected even with use of the error correction code.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to digital transmission or recording/reproduction of audio signals, and in particular, orthogonal transformation of audio signals and adaptive quantization of orthogonally transformed data sequences. The present invention relates to an audio signal processing device that compresses the amount of information for transmission, recording, and reproduction.

[Conventional technology]

Currently, in the field of digital audio such as compact disc systems (CD systems), unlike the field of audio communication, linear quantization is the mainstream when digitizing audio signals. For example, in a CD system, a sampling frequency of 44.1 kHz is used to digitize an audio signal, and 16-bit linear quantization is performed. When audio signals are digitized in this way, the transmission bit rate is approximately 1.4 Mb.
If the synchronization signal and error correction code are added, the transmission bit rate is 2Mb i
ts/sec, and the recording capacity that can be played back for one hour is about 7.20 bits.

On the other hand, there is a contradictory desire to be able to record more information and to make the recording medium more compact.In order to achieve this at the same time, it is necessary to perform information compression. , Moreover, the quality of the audio signal must not be degraded.

To this end, conventional techniques have been proposed in which digitalized audio signals are orthogonally transformed and then adaptively encoded to compress information. As an example, JP-A-55
-57900, a predetermined number of sample data of a digital audio signal is subjected to discrete cosine transform (DCT).
) to obtain coefficient data representing the level of each frequency component of the frequency spectrum, and quantize (adaptively encode) each coefficient data into data with the optimal number of bits according to its value. . According to this technique, the number of bits of each beater is not uniform, and each coefficient data has the minimum necessary number of bits, so the transmission bit rate is significantly reduced.

[Problem that the invention seeks to solve]

By the way, when transmitting, recording and reproducing audio data converted in this way, errors occur in the coefficient data due to noise and the like. To this end, an error correction code may be added to the data for transmission, recording, or reproduction, and the error correction code may be used to correct errors in each coefficient data on the receiving side or reproduction system.

However, there are limits to the errors that can be corrected using error correction codes, and if errors that cannot be corrected remain,
There is a problem in that the original audio signal cannot be restored from the received or reproduced audio data, and abnormal sounds occur in the reproduced audio.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an audio signal processing device that solves these problems and can restore the original audio signal when compressing audio information for transmission or recording/reproduction.

[Means for solving problems]

To achieve the above object, the present invention provides a predetermined number of frames (
However, an l frame is a group of coefficient data constituting one frequency spectrum), and multiple frames forming one unit are stored in a memory, and these multiple frames are sequentially read out from the memory one coefficient data at a time. Transmit or record audio information with coefficient data distributed between them, and on the receiving side or playback system, this distributed audio information is divided into each frame and coefficient data with errors within each frame is distributed. It is something.

[Effect]

Even if noise or the like is mixed into multiple coefficient data of distributed audio information and errors occur in these coefficient data, the erroneous coefficient data will be distributed within each frame reconstructed on the receiving side or playback system. Interpolation is possible from error-free coefficient data within the same frame, and
Between the previous and subsequent frames, one of the coefficient data for the same frequency component is error-free, and therefore interpolation is also possible using the correct coefficient data of the previous and subsequent frames.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an audio signal processing device according to the present invention, in which 1 is an input terminal, 2 is an A/D (
analog/digital) converter, 3 is buffer memory,
4 is a DFT (discrete Fourier transform) circuit, 5 is a bit allocation calculation circuit, 6 is an adaptive encoder, 7 is a memory, 8 is an error correction code generator, 9 is a transmission path, 10 is a memory, 11
1 is an error detection and correction circuit, 12 is an adaptive decoder, 13 is a bit allocation calculation circuit, 14 is an interpolation circuit, 15 is an IDFT (discrete inverse Fourier transform) circuit, 16 is a buffer memory, 1
7 is a D/A (digital/analog) converter, and 18 is an output terminal.

In the figure, an analog signal such as a music signal input to an input terminal 1 is converted into a digital signal by an A/D converter 2 and supplied to a buffer memory 3. When a predetermined number of sampling data are accumulated in the buffer memory 3,
The DFT circuit 4 performs Fourier transform on these sampled data, and outputs 16-bit data (hereinafter referred to as coefficient data) representing the level (ie, DFT coefficient) of each discrete frequency component.

The coefficient data of each frequency component is collectively called one frame.

The coefficient data is sent to the bit allocation calculation circuit 5 and the adaptive encoder 6.
and will be supplied. These compress the coefficient data by changing the number of bits according to the content (level) of the coefficient data, thereby reducing the transmission bit rate. The DFT circuit 4 forms and outputs coefficient data of the same number of bits, 16 bits, for each frequency component, whether its level is high or low. However, for high-level frequency components, it is necessary to use 16-bit data to represent the contents of the coefficient data in detail, but for low-level frequency components, the contents of the coefficient data must be expressed in less detail. In some cases, it is not necessary to do so, and in this case, the coefficient data is sufficient as, for example, 8-bit data.

Therefore, if 16-bit coefficient data is converted to 8-bit data, the transmission bit rate will be reduced.

The bit allocation calculation circuit 5 calculates the number of bits suitable for the supplied coefficient data from the contents of the supplied coefficient data. The adaptive encoder 6 converts the number of bits of the supplied coefficient data into the number of bits calculated by the bit allocation calculation circuit 5, and adaptively encodes each coefficient data.

The coefficient data encoded by the adaptive encoder 6 and the number of bits calculated by the bit allocation calculation circuit 5 are stored in the memory 7. When two frames of coefficient data are stored in the memory 7, an error correction code generated by an error correction code generator 8 is stored in each frame.

The coefficient data is added, and then one coefficient data is read out alternately every two frames, the data is distributed, and the data is sequentially sent out to the transmission line 9.

Here, this data distribution will be explained with reference to FIG.

In the same figure (a), the Nth frame (hereinafter referred to as N frame) is stored in frame memory A in memory 7, and the (N+1)th frame (hereinafter referred to as (N+1) frame) is stored in frame memory B. remembered. It is also assumed that each frame consists of (P+1) pieces of coefficient data, and that the coefficient data of each frame is stored in order from address 0 to address P in each frame memory.

Therefore, when reading these frames, first access address O to the frame memory and read the O-th coefficient data (coefficient data 0° and below) of N frame, and then as shown by the solid arrow, , accesses address 1 of frame memory B and reads coefficient data 1 of (N+1) frames. Next, address 2 of the frame memory is accessed to read coefficient data 2 of N frames, and address 3 of frame memory B is further accessed to read coefficient data 3 of frames (N+1). In this way, the two frame memories are accessed alternately while shifting the address by 1, and when the address P of frame memory B is accessed and the coefficient data P of the (N+1) frame is read out, next, this Access address 0 of frame memory B and read coefficient data 0 of the frame (N+1>frame. After that, as shown by the dashed-dotted arrow, address 1 of frame memory A - address 2 of frame memory B, etc.) 1. Access frame memory A in the order of address P.

As a result, as shown in FIG. 2(b), every other coefficient data of one frame is replaced with every other coefficient data of the other frame, and two frames become a unit. Data is transmitted.

Returning to FIG. 1, each coefficient data transmitted through the transmission line 9 is supplied to the memory 10.

In the memory 10, the coefficient data distributed over the frames are summarized for each frame.

That is, coefficient data is sequentially supplied to the memory 10, but as shown in FIG.
This coefficient data O is stored at address 0 of ``, and the coefficient data 1 of the next (N+1) frame supplied is stored at address 1 of the other frame memory B''. Coefficient data 2 is stored in address 2 of frame memory A', coefficient data 3 of (N+1) frames is stored in address 3 of frame memory B', etc., in the order indicated by the solid arrows in each frame memory A'.
, B' are stored with coefficient data. Then, when the coefficient data P of the (N+1) frame is stored at the address P of the frame memory B', the coefficient data O of the (N+1) frame is stored at the address 0 of the frame memory B', and so on. The coefficient data is stored in the order shown by the dashed-dotted arrow.As a result, each coefficient data of N frames is stored in the frame memory A' in the same order as in the memory 7 shown in Fig. 2(a). Similarly, each coefficient data of (N+1) frames is stored in the frame memory B', and the variance between two frames is returned.

Thereafter, the two frames stored in the memory 10 undergo error correction for each coefficient data by the error detection and correction circuit 11. For coefficient data for which error correction could not be performed, a flag is sent from the error detection and correction circuit 11 to the interpolation circuit 14. The coefficient data that has been subjected to the error correction process is supplied to the adaptive decoder 12 after separating the data of the number of bits obtained by the bit allocation calculation circuit 5, and is sent to the memory 10.
Based on the data of this number of bits sent to the bit allocation calculation circuit 13, it is decoded into the original 16-bit data. The decoded coefficient data is supplied to the interpolation circuit 14.

The interpolation circuit 14 performs interpolation using correct coefficient data for the coefficient data whose error could not be corrected by the error detection and correction circuit 11, and restores the original coefficient data.

The coefficient data output from the interpolation circuit 14 is supplied to the IDFT circuit 15, where it undergoes inverse Fourier transform for each frame to form sampling data of a digital signal. These sampling data are temporarily stored in the buffer memory 16 and read out sequentially to become digital signals. This digital signal is converted into an original analog signal by the D/A converter 17 and outputted from the output terminal 18.

Now, a case will be described in which an error occurs due to noise being mixed into the coefficient data while it is being read from the memory 7 and being transmitted over the transmission line 9.

As shown in FIG. 3(b), when each coefficient data is transmitted in a distributed manner between two frames, there is continuous noise from coefficient data 1 of (N+1) frame to coefficient data 4 of N frame. If this is mixed in, an error will occur in these coefficient data. However, in Memo January 0, when the coefficient data is separated for each frame and the variance is restored, as shown by hatching in Figure 3 (al),
N frame.

Coefficient data with errors in all (N+1) frames are arranged every other frame. Moreover, N frames and (
(N+1) frame, the address where the erroneous coefficient data is stored is different. This means that the coefficient data written at the same address in these frames corresponds to the same frequency component of the frequency segment tram, so even if noise that is longer than the transmission data length occurs continuously on the transmission path 9, This means that there is no error in coefficient data regarding the same frequency component between frames. However, if noise occurs in the transmission path 9 continuously for more than one frame length, an error will occur in the coefficient data regarding the same frequency component between two frames, but this is an extremely abnormal case. It is.

The error detection and correction circuit 11 performs error correction processing on the coefficient data having errors as described above, and although there is some coefficient data whose errors are corrected, there is also coefficient data whose errors cannot be corrected. For this coefficient data, the interpolation circuit 1
4 utilizes the arrangement relationship between the two frames of coefficient data with errors shown in Figure 3, and since the data contents are similar between adjacent frames, the same frequency of the previous and previous frames is used. Interpolation is performed using correct coefficient data of the components.

FIG. 4 is a block diagram showing an example of the interpolation circuit 14 in FIG. 1, in which 20.21 is an input terminal;
3 is a shift register, 24 is a counter, 25 is a decoder, 26 to 28 are shift registers, 29 is an averaging circuit, 3
0 is a switch, and 31 is an output terminal.

In the figure, coefficient data decoded into 16-bit data by the adaptive decoder 12 (FIG. 1) is sequentially input to an input terminal 20, and coefficient data having an error at the input terminal 20 is input to an input terminal 21. At the same time, a flag is input from the error detection and correction circuit 11 (FIG. 1). The shift registers 22 and 23 have a capacity for one frame, and the flag input to the input terminal 21 is delayed by one frame in the shift register 22, and then further delayed by one frame in the shift register 23. It will be delayed by one minute. The counter 24 is reset every frame period and the shift register 2
The flag output from 2 is counted, and when the count value becomes, for example, half or more of the number of coefficient data in one frame, the output becomes "H" (high level).

The decoder consists of shift registers 22, 23 and counter 2.
4 outputs and switch 30 according to these outputs.
is controlled by switching as shown in the table below.

However, in the above table, the outputs of shift registers 22 and 23 are rHJ when they are outputting flags.

Furthermore, when the output of the counter 24 is "H", the switch 3 is
0 closes to the C side.

The shift registers 26 to 28 also have a capacity for one frame of coefficient data. The coefficient data input from the input terminal 20 is delayed by one frame in the shift register 26, and
Furthermore, the signal is delayed by one frame in the shift register 27 and is supplied to the A side of the switch 30.

The coefficient data that has passed through the switch 30 is supplied to the output terminal 31, and is also delayed by one frame in the shift register 28 and supplied to the C side of the switch 30.

Further, the coefficient data output from the shift registers 26 and 28 are respectively supplied to an averaging circuit 29, and coefficient data representing these average values is formed and supplied to the B side of the switch 30.

Therefore, if it is assumed that all the coefficient data sequentially input to the input terminal 20 have been error-corrected, then the input terminal 2
1, the flag is not input, and the shift register 22
．． 23 does not output a flag, the switch 30 is closed to the A side, and each coefficient data is stored in the shift register 26.
．． 27, the signal is delayed by two frames and is supplied to the output terminal 31. Therefore, in this state, the coefficient data output from the shift register 27 is used as a reference, and this is
If the coefficient data of a frame is m, then the coefficient data output from the shift register 26 is the coefficient data m of (N+1) frames, and the coefficient data output from the shift register 28 is the coefficient data m of (Nl) frames. .

Thereafter, when coefficient data with an error is input to the input terminal 20, a flag is input to the input terminal 21 at the same time.

These are delayed by one frame each in shift registers 22 and 26, and then supplied to shift registers 23 and 27.
During this time, as is clear from the table above, the switch 30 is
The output terminal 31 is closed to the side, and the shift register 27 is connected to the output terminal 31.
The error-free coefficient data output by is obtained.

When erroneous coefficient data is output from the shift register 27, a flag is also output from the shift register 23. For this purpose, the switch 30 is switched to the B side, and the coefficient data from the averaging circuit 29 is supplied to the output terminal 31 and the shift register 28. Assuming that the erroneous coefficient data output from the shift register 27 is the coefficient data m of N frames, the coefficient data output from the averaging circuit 29 is the coefficient data m of the (N-1) frame, which is the previous frame. The coefficient data has the average information content of the coefficient data m and the coefficient data m of the next (N+1) frame. This averaged coefficient data becomes interpolation data for the erroneous coefficient data output from the shift register 27.

If two frames in which coefficient data are distributed mutually are called a distribution unit, it is rare for there to be an error in the coefficient data of the same frequency component between frames within the same distribution unit, but such a situation may occur. In this case, or between frames of consecutive dispersion units, the coefficient data of the same frequency component may have an error, and in this case, the coefficient data simultaneously output from the shift registers 26 and 27 may An error exists and a flag is simultaneously output from shift registers 22 and 23. At this time, the switch 30 is closed to the C side, and the coefficient data output from the shift register 28 is supplied to the output terminal 31 as interpolation data. It is almost impossible for coefficient data of the same frequency component to have an error between three consecutive frames.

Further, when the number of coefficient data having errors becomes % or more of the number of coefficient data of one frame, the switch 30 is closed to the C side by the output of the counter 24, and the coefficient data of the previous frame is supplied to the output terminal 31 again. be done.

The above operation will be explained with reference to FIG. 5 using frequency spectra of three frames. In addition, in the same figure (al is the (N-1) frame output from the shift register 28, in the same figure (bl is the N frame output from the shift register 27, and in the same figure (C) is the (N-1) frame output from the shift register 28.
The frequency spectrum of the N+1) frame is shown, with the horizontal axis representing the frequency component and the vertical axis representing the level of the frequency component. Here, similarly to the above, it is assumed that there are (P+1) frequency components in one frame, and coefficient data whose information content is a level is set for each frequency component. Furthermore, in FIGS. 5A to 5C, white circles represent that there are no errors in the coefficient data, and black circles represent that there are errors in the coefficient data.

When there is an error in the coefficient data m of N frames output from the shift register 27, the switch 30 closes to the B side and the coefficient data output from the averaging circuit 29 is transferred to the output terminal 3.
1, but this means that the mth frequency component of the N frame is not at the correct level as shown in FIG. 5(b). This results in interpolation using the average level of the m-th correct level frequency component of the frame and the m-th correct level frequency component of the (N+1) frame shown in FIG. 5(C).
The rectangular points in al, (b) indicate the level interpolated with the average value in this way.

If less than half of the coefficient data in one frame has an error, there will be no error in the same frequency component between two frames, as in the relationship shown in Figure 5(a), (bl).
The original frequency spectrum 7 can be restored by the above interpolation. On the other hand, if more than half of the coefficient data in one frame has an error, the same frequency component between two frames will also have an error, as shown in Figure 5(b). There will be an error in this. In this case, the previous frame is repeated to avoid an abnormal frequency spectrum.

In the above embodiment, the dispersion unit is two frames, but it is not limited to this and can be any plurality of frames. As the number of frames per variance unit increases, the distribution of erroneous coefficient data in a frame becomes coarser, and the number of erroneous coefficient data in one frame decreases, making the reproducibility of each frame better. .

Furthermore, in the above embodiment, interpolation was performed using the coefficient data of the previous and subsequent frames, but since the information contents of adjacent coefficient data are similar even within the same frame, interpolation is performed using adjacent coefficient data. You may also do so.

Furthermore, although the above embodiments have been described using the transmission of audio signals as an example, it goes without saying that the present invention can also be applied to recording and reproducing on a recording medium.

〔Effect of the invention〕

As explained above, according to the present invention, even if an error that occurs in coefficient data during transmission cannot be corrected using an error correction code, it can be easily and accurately restored. There's nothing to do.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the audio signal processing device according to the present invention, FIG.
1 is a schematic diagram showing the arrangement relationship of coefficient data to be transmitted, FIG. 3(a) is an explanatory diagram showing the write operation of the receiving side memory in FIG. b) is a schematic diagram showing an example of error occurrence in a transmission signal, FIG. 4 is a block diagram showing a specific example of the interpolation circuit in FIG. 1, and FIG. 5 is an explanatory diagram of its operation. i-1111--audio signal input terminal, 2...A/D
Converter, 3-...--Buffer memory, 4---
Discrete Fourier transform circuit, 5--bit allocation calculation circuit, 6--adaptive encoder, 7--memory, 8-- error correction code generator, 9-・---
-1 transmission line, 10...-memory, 11...-
error detection and correction circuit, 12----adaptive decoder,
13-...Bit allocation calculation circuit, 14-...
- Interphase circuit, 15-...Discrete inverse Fourier transform circuit, 16 Buffer memory, 17--Figure 1 Figure 2 (a) (b) 11-t Figure 3 (a) (b) Transferred Sanskrit five

Claims (1)

[Claims] 1. A first means for digitizing and orthogonally transforming an audio signal into audio information in units of frames consisting of a plurality of coefficient data, and adaptively encoding the audio information for each coefficient data. a second means for compressing the compressed audio information; a third means for transmitting or recording and reproducing the compressed audio information; a fourth means for adaptively decoding the received or reproduced audio information; and a fifth means for obtaining the original audio signal by inversely orthogonally transforming the audio information and converting it into analog, the audio signal processing device stores the adaptively encoded audio information in units of multiple frames, and converts the multiple frames into one. a sixth means for sequentially reading the coefficient data one by one and supplying it to the third means as audio information dispersed among the plurality of frames; and a seventh means for supplying the audio information to the fourth means, and is configured to be able to distribute erroneous coefficient data for each frame. 2. In claim 1, an eighth means for adding an error correction code to the audio information adaptively encoded by the second means; and an error correction code obtained by the seventh means. and a ninth means for performing error detection and correction of each coefficient data using the error correction code for each frame. 3. Claim 2 provides a tenth means for interpolating the coefficient data for which error correction cannot be performed by the ninth means using error-free coefficient data in the previous and subsequent frames or in the same frame. An audio signal processing device having: