JPS6316736A - Time division packet signal synthesizing device - Google Patents

Abstract

PURPOSE:To enable a packet signal from a multipoint to be received by one packet processing device at a reception side, by providing a packet reproduction circuit, a pattern signal generator, and a synthesizer which synthesizes a reproduced packet signal, with a pattern signal. CONSTITUTION:The packet reproduction circuit 1 identifies that the packet signals of a station A are as 211-213, and those of a station B, as 221 and 222, and that of a station C, as 231, by a reproduction information signal, and stores them by every transmission station. For example, as for the station B, the signal 221 is stored, and the signal 222 is stored following that, and the packet signal is outputted at a time when all of divided packet signals are prepared, to the synthesizer 3. While no signal is outputted from the packet reproduction circuit 1, that is, in sections other than the sections of the packet signals 210, 220, and 230, flag patterns 240, 250, 260, and 270 that are specific pattern signals (g), are outputted from the pattern signal generator 2, and are sent to the synthesizer 3. The synthesizer 3 forms a signal (h) by synthesizing a signal (f) from the packet reproduction circuit 1, with the pattern signal (g), and outputs it from a terminal 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal conversion device for converting a packet signal into a time-division multiplexed signal, and particularly to a time-division packet signal synthesis device.

[Conventional technology]

Traditionally, packet signals have been used for time division multiple access (TDMA) in wireless communications.
(Time Division Multiple A
A method of transmitting data using ``ccess'') has been considered. However, the current system uses only point-to-point lines, and does not assume that a single packet processing device on the receiving side can handle multipoint access.

In packet communications using satellites, access from multiple points is very effective, and packet signals that enable access from multiple points
A DMA signal converter is required.

[Problem that the invention seeks to solve]

However, a signal conversion device that meets the above requirements has not yet been developed.

Therefore, an object of the present invention is to provide a signal that converts a packet signal into a TDMA signal in order to enable a single packet processing device on the receiving side to handle access from multiple points, which was impossible in the conventional system. An object of the present invention is to provide a time-division packet signal synthesis device which is a conversion device.

[Means for solving problems]

The present invention provides a time-division packet signal synthesis device for regenerating each time-division multiplexed packet signal transmitted from a plurality of transmitting stations and converting the time-division multiplexed signal into a time-division multiplexed signal. a packet reproducing circuit that stores and reproduces the original packet signal from each divided packet signal; a pattern signal generator that generates a specific pattern signal when there is no output signal from the packet/) reproducing circuit; The present invention is characterized by comprising: a synthesizer for synthesizing the generated packet signal and the pattern signal.

[Effect]

According to the present invention, a reproduced information signal of a time division multiplexed signal including reproduced information signals transmitted from a plurality of transmitting stations is decoded, and based on the obtained information, divided packet signals for each station are converted into reproduced information signals. It is stored for each station with the .

The original packet signal from the stored divided packet signal is reproduced and converted into a time division multiplexed signal by combining it with a specific pattern signal.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.

This time-division packet signal synthesis device stores each time-division multiplexed packet signal transmitted from a plurality of transmitting stations for each transmitting station, and performs a packet playback function that reproduces the original packet signal from each divided packet signal. It consists of a circuit 1, a pattern signal generator 2 that generates a specific pattern signal when there is no output signal from the packet reproduction circuit 1, and a synthesizer 3 that combines the reproduced packet signal and the pattern signal. .

The operation of such a time-division packet signal synthesis apparatus when time-division packet signals are sent from transmitting stations A, B, and C will be explained based on the signal timing chart of FIG. 2.

A time-divided packet signal a from transmitting stations A, B, and C is input to a terminal 4. That is, as shown in Fig. 2, station A, station B
packet signals 211, 221, which are time-divided by station C and station C.
Suppose that it sends 231, 212, 222, and 213.

The packet signals of station A are 211, 212, 213, the packet signals of station B are 221, 222, and the packet signals of station C are 231.

On the other hand, a reproduction information signal necessary for reproduction of each packet signal, such as slot allocation information, is inputted to the terminal 5.

In the packet reproduction circuit 1, according to the reproduction information signal, the packet signal of the A station is 21L212, 213, the packet signal of the B station is 221, 222, and the packet signal of the C station is 2L212, 213.
31 and stored for each transmitting station.

In FIG. 2, c, d, and e indicate the states stored separately for A, B, and C stations, respectively. For example, for station B, signal 221 is stored, followed by signal 222. Then, when all the divided packet signals are collected, they are output to the combiner 3. The signal f shows the state of the output. At this point, the signals from each transmitting station are combined every round, and the reproduced original packet signal 210.220.2
It is output as 30.

While nothing is being output from the packet reproducing circuit 1, that is, in an interval other than the packet signals 210, 220, and 230,
The pattern signal generator 2 generates flag patterns 240, 250, 260, 27 which are specific pattern signals g.
0 is output and sent to the combiner 3.

The synthesizer 3 synthesizes the signal f from the packet reproducing circuit 1 and the pattern signal g to form a signal, and outputs the signal from the terminal 6.

FIG. 3 is a block diagram showing an example of the packet reproducing circuit 1. As shown in FIG.

This packet reproducing circuit 1 includes a reproduction information processor 11 that decodes a reproduction information signal of a time division multiplexed signal to obtain station information;
A switch 12 that switches according to the station information output from the reproduction information processor, and a storage circuit 1 that stores only time-divided packet signals excluding reproduction information signals for each transmitting station.
3.14.15, a read control circuit 16 that controls reading of these memory circuits, and each memory circuit 13.14.1
5 and a readout storage circuit 17 that performs output while controlling the outputs from 5 so that they do not overlap.

The operation of such a packet generation circuit will be explained with reference to the timing chart of FIG. 4 showing the state of signals.

In the case of this embodiment shown in FIG. 1, the signals input to terminals 4 and 5 are synthesized and time-divided packet signals a
It is assumed that a reproduction information signal is inserted at the beginning of the file. Therefore, terminals 4 and 5 are replaced by one terminal 8 in FIG. A time division multiplexed signal i is input to this terminal 8. In FIG. 4, 21.22.23 is a divided packet signal from station A, 31.32.33 is a divided packet signal from B station, and 41 is a divided packet signal from 0 station. B
The two divided packet signals 32 and 33 from the station are multiplexed into one slot signal. Also during signal i, 51, 52
．． 53 is a reproduction information signal from station A, 6L62 is a reproduction information signal from station B, and 71 is a reproduction information signal from station 0.

When the time division multiplexed signal i is input, the reproduction information processor 11
The reproduced information signal is decoded to obtain station information, and based on this station information, the switch 12 is switched to the storage circuits 13, 14, and 15 assigned to each station A, B, and C.

Then, only the time-divided packet signals excluding the reproduction information signal are stored in the storage circuits 13, 14, and 15 for each transmitting station.

The memory states of each memory circuit 13, 14, and 15 are shown in FIG. 4j.

k, shown in 1. The storage circuit 13 stores only the divided packet signals 21, 22, 23 from the A station, the storage circuit 14 stores only the divided packet signals 3L32.33 from the B station, and the storage circuit 15 stores the divided packet signals 21, 22, 23 from the A station. Only the divided packet signal 41 is stored.

Furthermore, when the reproduction information processor 11 detects a packet transmission end signal from the reproduction information signal, it activates the read control circuit 16 to output the data currently in the storage circuit. The readout storage circuit 17 includes each storage circuit 13.14.
．． The appearance of the output signal, which is outputted from the terminal 9 while being controlled so that the outputs from the terminals 15 and 15 do not overlap, is shown by m in FIG. The signal 81 is the output from the memory circuit 13, and the signal 82 is the output from the memory circuit 13.
is the output from the memory circuit 14, and the signal 83 is the output from the memory circuit 15.
The output from each is shown. In this case, two packets 32 and 33 (current and next packet signals) from station B are multiplexed into one slot signal, so in order to output only the current packet signal 32, multiple points are added to the reproduction information signal. Similarly, the readout control circuit 16 extracts the information indicated by the signal 3, leaving the next packet signal 33.
1.32 is synthesized and a signal 82 is created and output.

〔Effect of the invention〕

According to the present invention, it is possible to handle packet signal access from multiple points with one packet processing device on the receiving side.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1, FIG. 3 is a block diagram showing an example of a packet reproducing circuit, FIG. 4 is a timing chart for explaining the operation of the packet reproducing circuit shown in FIG. 1...Packet reproducing circuit 2...Pattern signal generator 3...Synthesizer 11...Reproduction information processor 12...Switches 13, 14.15.・Memory circuit

Claims (1)

[Claims] (1) In a time-division packet signal synthesis device that reproduces each time-division multiplexed packet signal transmitted from a plurality of transmitting stations and converts it into a time-division multiplexed signal, the time-division multiplexed signal is stored for each transmitting station. a packet reproducing circuit that reproduces the original packet signal from each divided packet signal; a pattern signal generator that generates a specific pattern signal when there is no output signal from the packet reproducing circuit; and the reproduced packet signal. A time division pattern signal synthesis device comprising: a synthesizer for synthesizing the pattern signal and the pattern signal.