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JPS63164343A - Flip chip ic device - Google Patents

Flip chip ic device

Info

Publication number
JPS63164343A
JPS63164343A JP61312102A JP31210286A JPS63164343A JP S63164343 A JPS63164343 A JP S63164343A JP 61312102 A JP61312102 A JP 61312102A JP 31210286 A JP31210286 A JP 31210286A JP S63164343 A JPS63164343 A JP S63164343A
Authority
JP
Japan
Prior art keywords
film
solder
bump contact
chip
aluminum electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61312102A
Other languages
Japanese (ja)
Inventor
Yoshifumi Kitayama
北山 喜文
Yukio Maeda
幸男 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61312102A priority Critical patent/JPS63164343A/en
Publication of JPS63164343A publication Critical patent/JPS63164343A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To form a conical bump contact at low cost by a simple process by forming a metallic film having excellent adhesiveness to solder onto an electrode through electroless plating and shaping the conical bump contact onto the metallic film through solder dipping. CONSTITUTION:A passivation film 3 is formed onto approximately the whole surface excluding an aluminum electrode 2 on one surface of an IC chip 1. A metallic film 4 consisting of a metal having excellent adhesiveness to solder is shaped onto the aluminum electrode 2 through electroless plating, using the passivation film 3 as a resist film. A conical bump contact 5 is formed onto the metallic film 4 through solder dipping. No mask is needed by utilizing the passivation film 3 as the resist film, and no golden thin-film is needed, either. Nickel is optimum as the material of the metallic film 4, and the metallic film 4 may be shaped in thickness of approximately 1-10mum, thus forming the bump contact 5 composed of solder at low cost through a simple process.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はフリップチップIC装置に関するものである。[Detailed description of the invention] Industrial applications The present invention relates to flip-chip IC devices.

従来の技術 従来のフリップチップIC装置においで、その−面に半
田からなる山形のバンプ接点を形成する際には、第2図
に示すように、ICチップ11のアルミニウム電極12
には半[11が付かないため、ICチップ11のアルミ
ニウム電極12を配置された一面]二に、真空蒸着やス
パッタリングによりて、アルミニウム電極12との接着
性の良好なりローム薄膜13を形成し、次にその上に銅
薄膜14を形成し、さらにその上に金またはニッケルの
薄膜15を形成し、次にこれらの薄膜上にレノスト膜を
形成するとともに、フォトリングラフィによってアルミ
ニウム電極12上のレジスト膜を除去し、前記薄膜13
.14.15を共通電極として半田メッキを行うことに
より半田からなる山形のバンプ接、α16を形成し、そ
の後前記レノスト膜を除去するとと6に、前記バンプ接
点16上にレジスト膜を形成し、バンプ接、−居16以
外の部分の前記各薄膜13.14.15を除去しでいた
2. Description of the Related Art In a conventional flip chip IC device, when a chevron-shaped bump contact made of solder is formed on the negative side of the device, as shown in FIG.
Form a loam thin film 13 with good adhesion to the aluminum electrode 12 by vacuum evaporation or sputtering on the second half [11 is not attached, so one side on which the aluminum electrode 12 of the IC chip 11 is arranged], Next, a copper thin film 14 is formed thereon, a gold or nickel thin film 15 is further formed thereon, a renost film is formed on these thin films, and a resist film on the aluminum electrode 12 is formed by photolithography. Remove the film and remove the thin film 13.
.. 14. By performing solder plating using 15 as a common electrode, a chevron-shaped bump contact α16 made of solder is formed, and then the Renost film is removed. In step 6, a resist film is formed on the bump contact 16, and the bump The thin films 13, 14, and 15 other than the contact and contact portions 16 were completely removed.

また、上記と同様にICチップlの一面上にクローム薄
膜13と銅薄膜14を形成した後、m薄ff5!14上
にレジスト膜を形成するとともに、7オトリソグラフイ
によってアルミニウム1庵12上のレジスト膜のみを残
して除去し、次にアルミニウム電1131−以外の前記
薄膜13.14を除去した後、銅薄膜14−ヒのレノス
ト膜も除去することにより、前記アルミニウム電極12
上にのみ薄v13.14を形成し、その後メタルマスク
を用いて前記アルミニウム電極12上の銅薄膜14上に
のみ半田を真空蒸着して山形のバンプ接点16を形成す
る方法も採用されていた。尚、第2図において、17は
ICチップ1の一面上のパシベーション膜である。
In addition, after forming a chrome thin film 13 and a copper thin film 14 on one surface of the IC chip l in the same manner as above, a resist film is formed on the m-thin FF5! The aluminum electrode 12 is removed by leaving only the resist film, and then removing the thin films 13 and 14 other than the aluminum electrode 1131-, and then also removing the copper thin film 14-1.
A method has also been adopted in which a thin film 13.14 is formed only on the aluminum electrode 12, and then solder is vacuum-deposited only on the copper thin film 14 on the aluminum electrode 12 using a metal mask to form a chevron-shaped bump contact 16. In FIG. 2, 17 is a passivation film on one surface of the IC chip 1. As shown in FIG.

発明が解決しようとする問題点 ところが、上記のように山形のバンブ接点を形成するの
に、3/iijまたは2層の金E4薄膜を形成した後、
エツチングを行い、さらに真空蒸着や電気メッキを行う
という複雑な工程が必要であり、しかも7オトリソグラ
フイに1±マスクが必要であるためコスト高となるとい
う問題があった。
Problems to be Solved by the Invention However, in order to form a chevron-shaped bump contact as described above, after forming a 3/iij or two-layer gold E4 thin film,
This method requires complicated steps such as etching, vacuum deposition and electroplating, and also requires 1± mask for 7 otolithography, resulting in high cost.

本発明は従来のこの上うな間り代に鑑み、簡略な工程に
より低コストで山形のバンプ接点を形成できるフリップ
チップIC装置の提供を目的とする。
In view of the conventional machining margin, it is an object of the present invention to provide a flip-chip IC device that can form chevron-shaped bump contacts at low cost through simple steps.

問題点を解決するための手段 本発明のフリップチップIC装置は、上記目的を達成す
るため、ICチップの一面に形成されたアルミニウム電
極上に半田に対して接着性の良い金属膜を無電解メッキ
にて形成し、この金!XIKの上に半田ディツプにて山
形のバンブ接点を形成したことを特徴とする。
Means for Solving the Problems In order to achieve the above object, the flip-chip IC device of the present invention employs electroless plating of a metal film with good adhesion to solder on an aluminum electrode formed on one surface of an IC chip. Formed in this gold! A feature is that a chevron-shaped bump contact is formed on the XIK with solder dip.

作用 本発明は上記構成を有するので、無電解メッキを行う際
に、ICチップの一面のアルミニウム電極を除(はぼ全
面に形成されているバシベーシ5ン膜をレノスト膜とし
て利用することができ、ICチップを無電解メッキする
ことによりマスク無しで半田に対して付着性の良い金属
膜を形成でき、この金属膜に半田ディツプにて容易に山
形のバンブ接点を形成することがで島る。
Operation Since the present invention has the above-mentioned configuration, when performing electroless plating, the aluminum electrode on one side of the IC chip is removed (the Basibase film formed on almost the entire surface can be used as a Renost film, By electroless plating an IC chip, a metal film with good adhesion to solder can be formed without a mask, and a chevron-shaped bump contact can be easily formed on this metal film using a solder dip.

実施例 以下、本発明の一実施例を第1図を参照しながら説明す
る。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.

1はICチップであって、その−面には略8000A程
度の厚さのアルミニウム電極2が形成されでおり、かつ
このICチップ1の一面には、アルミニウム電極2を除
いて略全面にパシベーシタン11i3が形成されている
。このパシベーション膜3をレノスト膜としてM′II
l解メッキセメツキアルミニウム電極2」−に半田に対
して接着性の良い金属からなる金属膜4が形成されでい
る。この金属F!4の材質としてはニッケルが最適であ
り、又この金属膜4は1〜10μm程度の厚さに形成す
ればよい。そして、この金属膜4上に半田ディツプにて
山形のバンプ接点5が形成されている。
Reference numeral 1 denotes an IC chip, and an aluminum electrode 2 having a thickness of about 8000A is formed on the negative side of the IC chip. is formed. M'II with this passivation film 3 as a Renost film.
A metal film 4 made of a metal with good adhesion to solder is formed on the electrolytically plated aluminum electrode 2. This metal F! The most suitable material for the metal film 4 is nickel, and the metal film 4 may be formed to have a thickness of about 1 to 10 μm. A chevron-shaped bump contact 5 is formed on this metal film 4 by soldering dip.

このように、パシベーション膜3をレジスト膜として利
用することによってマスクが不要となり、また金の薄膜
も不要となり、簡単な工程によって低コストで半田から
なるバンブ接点5を形成することができる。
In this way, by using the passivation film 3 as a resist film, a mask and a thin gold film are not required, and the bump contact 5 made of solder can be formed at low cost through a simple process.

本発明は上記実施例に限定されるものではなく、例えば
金属膜としてニッケルからなるものを例示したが、無電
解メッキが可能でかつ半田に対する接着性の良好な他の
金属、例えば銅や鉛にて構成しても良いことは言うまで
もない。
The present invention is not limited to the above embodiments. For example, the metal film is made of nickel, but other metals that can be plated electrolessly and have good adhesion to solder, such as copper or lead, may also be used. Needless to say, it may be configured as follows.

発明の効果 本発明のフリップチップIC装置によれば、以上のよう
に、ICチップの一面に形成されているパシベーション
膜をレノスト膜として利用することによって、マスク無
しで半田に対して接着性の良い金属膜をアルミニウム電
極上に無電解メッキにて形成でき、この金属膜に半田デ
ィツプにで容易に山形のバンブ接点を形成することがで
きる。
Effects of the Invention According to the flip-chip IC device of the present invention, as described above, by using the passivation film formed on one surface of the IC chip as a Renost film, it is possible to achieve good adhesion to solder without a mask. A metal film can be formed on the aluminum electrode by electroless plating, and a chevron-shaped bump contact can be easily formed on this metal film by solder dip.

したがって、簡略な工程により低コストで半田からなる
山形のバンプ接、αを有するフリップチップIC装置を
製造で終るという効果がある。
Therefore, there is an effect that a flip-chip IC device having a chevron-shaped bump contact made of solder, α, can be manufactured at low cost through a simple process.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の断面図、第2図は従来例の
断面図である。 1・・・・・・・・・ICチップ 2・・・・・・・・・アルミニウム電極3・・・・・・
・・・パンベーン1ン膜4・・・・・・・・・金jA膜
FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional example. 1...IC chip 2...Aluminum electrode 3...
... Pan vane 1 membrane 4 ... Gold jA membrane

Claims (1)

【特許請求の範囲】[Claims] ICチップの一面に形成されたアルミニウム電極上に半
田に対して接着性の良い金属膜を無電解メッキにて形成
し、この金属膜の上に半田ディップにて山形のバンプ接
点を形成したことを特徴とするフリップチップIC装置
A metal film with good adhesion to solder is formed by electroless plating on the aluminum electrode formed on one side of the IC chip, and a chevron-shaped bump contact is formed on this metal film by solder dipping. Features of flip chip IC device.
JP61312102A 1986-12-26 1986-12-26 Flip chip ic device Pending JPS63164343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61312102A JPS63164343A (en) 1986-12-26 1986-12-26 Flip chip ic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61312102A JPS63164343A (en) 1986-12-26 1986-12-26 Flip chip ic device

Publications (1)

Publication Number Publication Date
JPS63164343A true JPS63164343A (en) 1988-07-07

Family

ID=18025262

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61312102A Pending JPS63164343A (en) 1986-12-26 1986-12-26 Flip chip ic device

Country Status (1)

Country Link
JP (1) JPS63164343A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5478007A (en) * 1993-04-14 1995-12-26 Amkor Electronics, Inc. Method for interconnection of integrated circuit chip and substrate
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
US6908311B2 (en) 2002-04-26 2005-06-21 Sharp Kabushiki Kaisha Connection terminal and a semiconductor device including at least one connection terminal

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5478007A (en) * 1993-04-14 1995-12-26 Amkor Electronics, Inc. Method for interconnection of integrated circuit chip and substrate
US5795818A (en) * 1996-12-06 1998-08-18 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection and method
US6163463A (en) * 1996-12-06 2000-12-19 Amkor Technology, Inc. Integrated circuit chip to substrate interconnection
US6908311B2 (en) 2002-04-26 2005-06-21 Sharp Kabushiki Kaisha Connection terminal and a semiconductor device including at least one connection terminal

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