JPS63142840A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63142840A JPS63142840A JP61291095A JP29109586A JPS63142840A JP S63142840 A JPS63142840 A JP S63142840A JP 61291095 A JP61291095 A JP 61291095A JP 29109586 A JP29109586 A JP 29109586A JP S63142840 A JPS63142840 A JP S63142840A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- plating layer
- outer lead
- copper foil
- onto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 229910000679 solder Inorganic materials 0.000 claims abstract description 33
- 238000007747 plating Methods 0.000 claims abstract description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 18
- 239000011889 copper foil Substances 0.000 abstract description 18
- 238000000034 method Methods 0.000 abstract description 4
- 238000000465 moulding Methods 0.000 abstract description 4
- 238000007689 inspection Methods 0.000 abstract 1
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 239000000155 melt Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はプリント基板への実装効率を高めることができ
る半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device that can be mounted more efficiently on a printed circuit board.
従来の技術
一般に半導体装置においては、プリント基板への半田付
は作業が容易に行えるように、外部ＩＪ −ドの表面に
あらかじめ半田、すす等のメッキが施しである。2. Description of the Related Art In general, in semiconductor devices, the surface of an external IJ is plated with solder, soot, etc. in advance to facilitate soldering to a printed circuit board.
第３図ａ、ｂはこのような従来の半導体装置を示すもの
である。第３図ａ、ｂにおいて、リードフレーム１の中
央に半導体チップ２が載置され、半導体チップ２のポン
ディングパッド部（図示せず）とリードフレーム１の所
定個所とが金線等のワイヤ３で接続され、これらのリー
ドフレーム１の中心付近と半導体チップ２とワイヤ３と
が樹脂４で封止されている。そして樹脂４の外部に露出
している外部リード５の表面には、樹脂封止後に例えば
、半田デイツプ処理を施すことによって半田のメッキ層
６が形成される。その後、タイバーカット、外部リード
成型、特性検査等の各工程を経て半導体装置が完成する
。FIGS. 3a and 3b show such a conventional semiconductor device. In FIGS. 3a and 3b, a semiconductor chip 2 is placed in the center of a lead frame 1, and a bonding pad portion (not shown) of the semiconductor chip 2 and a predetermined location of the lead frame 1 are connected to a wire 3 such as a gold wire. The vicinity of the center of these lead frames 1, the semiconductor chip 2, and the wires 3 are sealed with a resin 4. A solder plating layer 6 is formed on the surface of the external lead 5 exposed to the outside of the resin 4 by, for example, performing a solder dip treatment after resin sealing. Thereafter, the semiconductor device is completed through various processes such as tie bar cutting, external lead molding, and characteristic testing.
このような半導体装置をプリント基板に実装するときに
は、第４図ａ、ｂに示すように、外部リード６の先端付
近をプリント基板７の銅箔８の表面に接触させ、この状
態でリフロー、レーザー照射、熱圧着等の方法で外部リ
ード表面のメッキ層６と銅箔８上にあらかじめ付着され
た半田（図示せず）を溶かして外部リード５を銅箔８に
接着する０
発明が解決しようとする問題点
ところが、このような半導体装置では外部り−ド５のす
べてをプリント基板７の銅箔８上に接着できない場合が
多い。特に第３国電に示すような面実装タイプの半導体
装置においては、樹脂４の全周に数十水〜百本もの外部
リード５が出ているものも多く、しかもこれらの外部リ
ード６の成型角度が微妙にばらつくため、すべての外部
リード６を一度で完全に接着することは極めて困難であ
る。また第３図すに示すような外部リード６の先端を銅
箔８の表面に点接触させるタイプの半導体装置において
は、銅箔８との接触面積が小さいため、外部リード５の
表面の半田と銅箔８の表面の半田だけでは十分良好な接
着強度が得られないことが多い。When mounting such a semiconductor device on a printed circuit board, as shown in FIG. Solder (not shown) previously attached to the plating layer 6 and copper foil 8 on the surface of the external lead is melted by a method such as irradiation or thermocompression bonding, and the external lead 5 is bonded to the copper foil 8. However, in such a semiconductor device, it is often not possible to bond all of the external leads 5 onto the copper foil 8 of the printed circuit board 7. In particular, in surface-mount type semiconductor devices such as those shown in the third National Electric Power Company, there are many cases in which dozens to hundreds of external leads 5 are protruded around the entire circumference of the resin 4, and the molding angle of these external leads 6 is very small. It is extremely difficult to completely bond all the external leads 6 at once because of slight variations in the bonding. Furthermore, in a semiconductor device of the type in which the tips of the external leads 6 are brought into point contact with the surface of the copper foil 8 as shown in FIG. In many cases, sufficient adhesion strength cannot be obtained with solder alone on the surface of the copper foil 8.
本発明はこのような問題を解決することができる半導体
装置を提供するものである。The present invention provides a semiconductor device that can solve these problems.
問題点を解決するための手段
本発明は表面にあらかじめメッキ層が設けられ、かつ、
所定の形状に成型された外部リードの表面にさらに半田
を付着させるものである。Means for Solving the Problems The present invention has a plated layer provided on the surface in advance, and
Solder is further applied to the surface of the external lead molded into a predetermined shape.
作用
このようにすれば、外部リードの表面にあらかじめ設け
であるメッキ層のほかに、その後付着された半田がのる
ことになる。このため外部リード表面にのる総半田量が
多くなる。その結果、面実装タイプの半導体装置におい
ても、点接触タイプの半導体装置においても、外部リー
ドをプリント基板の銅箔に確実に接着することができる
。By doing this, in addition to the plating layer provided in advance, the solder that is subsequently applied will be on the surface of the external lead. Therefore, the total amount of solder on the surface of the external leads increases. As a result, the external leads can be reliably bonded to the copper foil of the printed circuit board in both surface-mount type semiconductor devices and point-contact type semiconductor devices.
実施例
以下、本発明の一実施例を第１図、第２図とともに説明
する。EXAMPLE An example of the present invention will be described below with reference to FIGS. 1 and 2.
第１図、第２図において、第３図、第４図と同一の部分
には第３図、第４図と同一の符号を付して説明を省略す
る。第１図ａ、ｂに示すように、外部リード５の先端付
近には、あらかじめ設けられているメッキ層６の表面に
さらに半田９が付着されている。In FIGS. 1 and 2, the same parts as in FIGS. 3 and 4 are given the same reference numerals as in FIGS. 3 and 4, and their explanations will be omitted. As shown in FIGS. 1a and 1b, near the tips of the external leads 5, solder 9 is further adhered to the surface of the plating layer 6 provided in advance.
半田９の付着は、最初のメッキ層らを形成後、タイバー
カット、外部リード成型の工程を経て、特性検査を行う
前に行う。半田９の付着時に、あらかじめ設けられてい
るメッキ層６も一部溶けるが、大半は外部リード５の表
面に残っている。The solder 9 is attached after forming the first plating layer, through the steps of tie bar cutting and external lead molding, and before performing a characteristic test. When the solder 9 is attached, a portion of the plating layer 6 provided in advance also melts, but most of it remains on the surface of the external lead 5.
したがって第１図ａ、ｂに示すように２重の半田層に相
当する量の半田が外部リード６の表面に残ることになる
。Therefore, as shown in FIGS. 1a and 1b, an amount of solder equivalent to two layers of solder remains on the surface of the external lead 6.
このようにして得た半導体装置の外部リード５を第２図
ａ、ｂに示すようにプリント基板７の銅箔８０表面に接
触させ、従来と同様にリフロー。The external leads 5 of the semiconductor device thus obtained are brought into contact with the surface of the copper foil 80 of the printed circuit board 7 as shown in FIGS. 2a and 2b, and reflowed as in the conventional method.
レーザー照射、熱圧着等の方法で外部リード５０表面の
メッキ層６の半田とその表面の半田９とを溶かすと、多
量の半田が外部リード５と銅箔８の間に溶は出す。この
とき、銅箔８上にあらかじめ半田を付着させておけば、
この半田も溶けて外部リード５と銅箔８間に溶は込む。When the solder of the plating layer 6 on the surface of the external lead 50 and the solder 9 on the surface are melted by a method such as laser irradiation or thermocompression bonding, a large amount of solder melts between the external lead 5 and the copper foil 8. At this time, if you apply solder on the copper foil 8 in advance,
This solder also melts and penetrates between the external lead 5 and the copper foil 8.
その結果、第１国電の面実装タイプの半導体装置におい
ても、第１図すの点接触タイプの半導体装置においても
、外部リード５をプリント基板子の銅箔８に確実に接着
することができる。なお、実施例ではメッキ層らとして
半田を例示したが、錫などの他の金属でメッキ層を形成
してもよい。As a result, the external leads 5 can be reliably bonded to the copper foil 8 of the printed circuit board in both the surface mount type semiconductor device of the first national electric power company and the point contact type semiconductor device of FIG. In addition, although solder was illustrated as the plating layer in the embodiment, the plating layer may be formed of other metals such as tin.
発明の効果
本発明の半導体装置はあらかじめメッキ層を設けた外部
リード表面にさらに半田を付着させたものであるから
外部リードの形状の如何にかかわらず、外部リードを銅
箔に確実に接着することができ、半導体装置のプリント
基板への実装効率を高めることができる。Effects of the Invention The semiconductor device of the present invention is one in which solder is further adhered to the surface of the external lead on which a plating layer has been provided in advance.
Regardless of the shape of the external lead, the external lead can be reliably bonded to the copper foil, and the efficiency of mounting the semiconductor device onto the printed circuit board can be increased.
第１図ａ、ｂは本発明の実施例における半導体装置の断
面図、第２図ａ、ｂはその実装時の断面図、第３図ａ、
ｂは従来の半導体装置の断面図、第４図ａ、ｂはその実
装時の断面図である。
１・・・・・・リードフレーム、２・・・・・・半導体
チップ、３・・・・・・ワイヤ、４・・・・・・樹脂、
５・・・・・・外部リード、６・・・・・・あらかじめ
設けられたメッキ層、ア・・・・・・プリント基板、８
・・・・・・銅箔、９・・・・・・半田。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名／−
一−ワード７レーム ５−−−ダト音ｐワード４−
徊脂 デー半田
乃 ２ 図
第３図
第４図1A and 1B are cross-sectional views of a semiconductor device according to an embodiment of the present invention, FIGS. 2A and 2B are sectional views when the semiconductor device is mounted, and FIGS.
4b is a sectional view of a conventional semiconductor device, and FIGS. 4a and 4b are sectional views when the device is mounted. 1... Lead frame, 2... Semiconductor chip, 3... Wire, 4... Resin,
5... External lead, 6... Plating layer provided in advance, A... Printed circuit board, 8
......Copper foil, 9...Solder. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
1-word 7 rheme 5---dato sound p word 4-
Figure 3 Figure 4
Claims (1)
またはスズ等のメッキ層が設けられかつ所定の形状に成
形された外部リードの表面に、さらに半田を付着させた
ことを特徴とする半導体装置。1. A semiconductor device characterized in that solder is further adhered to the surface of an external lead which is led out of a package, has a solder or tin plating layer formed on the surface, and is formed into a predetermined shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61291095A JPS63142840A (en) | 1986-12-05 | 1986-12-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61291095A JPS63142840A (en) | 1986-12-05 | 1986-12-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63142840A true JPS63142840A (en) | 1988-06-15 |
Family
ID=17764381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61291095A Pending JPS63142840A (en) | 1986-12-05 | 1986-12-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63142840A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0385750A (en) * | 1989-08-30 | 1991-04-10 | Yamaha Corp | Semiconductor device and its mounting method |
| JPH05343586A (en) * | 1991-03-22 | 1993-12-24 | Akira Kitahara | Surface mounting component and manufacture thereof |
| KR100743231B1 (en) | 2001-05-10 | 2007-07-27 | 엘지전자 주식회사 | Making method of PCB |
-
1986
- 1986-12-05 JP JP61291095A patent/JPS63142840A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0385750A (en) * | 1989-08-30 | 1991-04-10 | Yamaha Corp | Semiconductor device and its mounting method |
| JPH05343586A (en) * | 1991-03-22 | 1993-12-24 | Akira Kitahara | Surface mounting component and manufacture thereof |
| KR100743231B1 (en) | 2001-05-10 | 2007-07-27 | 엘지전자 주식회사 | Making method of PCB |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8076181B1 (en) | Lead plating technique for singulated IC packages | |
| JPH11260985A (en) | Lead frame, resin-sealed semiconductor device and its manufacture | |
| JP2000286374A (en) | Semiconductor integrated circuit device | |
| JPH0355859A (en) | Semiconductor die bonding method, strip carrier and integrated circuit bonding tape | |
| KR20070046804A (en) | Semiconductor device | |
| JP7089388B2 (en) | Semiconductor devices and methods for manufacturing semiconductor devices | |
| WO1998018161A1 (en) | Semiconductor device, method of its manufacture, circuit substrate, and film carrier tape | |
| JP5125975B2 (en) | Resin case manufacturing method | |
| TWI291756B (en) | Low cost lead-free preplated leadframe having improved adhesion and solderability | |
| JP2001345414A (en) | Lead frame, semiconductor device and its manufacturing method, circuit board, and electronic equipment | |
| JP2012243943A (en) | Wire bonding structure, electronic apparatus, and manufacturing method of electronic apparatus | |
| JP2569400B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JP2014082385A (en) | Method of manufacturing semiconductor device, and semiconductor device | |
| JPS63142840A (en) | Semiconductor device | |
| US11004742B2 (en) | Methods and apparatus for an improved integrated circuit package | |
| JP2001077268A (en) | Resin sealed semiconductor device and manufacture thereof | |
| JP3716101B2 (en) | Lead frame, semiconductor device manufacturing method using the same, and semiconductor device | |
| US20210296216A1 (en) | Semiconductor device, lead frame, and method for manufacturing semiconductor device | |
| JPH0870082A (en) | Semiconductor integrated circuit device and its manufacture, and lead frame | |
| JP2004335947A (en) | Semiconductor device and formation method thereof | |
| KR100230751B1 (en) | Semiconductor package manufacturing method | |
| JP4311294B2 (en) | Electronic device and manufacturing method thereof | |
| JP2002164497A (en) | Semiconductor device and method for manufacturing the same | |
| JPS6242549A (en) | Package for electronic part and manufacture thereof | |
| JPH02301144A (en) | Method of peeling outer sealing resin |