JPS63136718A - Pll circuit - Google Patents

Abstract

PURPOSE:To improve the PSRR characteristic of jitter by constituting the PLL circuit by plural phase control circuit connected substantially in series each including a phase comparator, a loop filter and a voltage controlled oscillator circuit and plural frequency divider circuits connected in series so as to decrease the peak of the phase transfer function as the entire PLL circuit. CONSTITUTION:The PLL circuit is provided with phase control circuits PC1, PC2 each comprising a phase comparator, a loop filter and a voltage controlled oscillator circuit. The oscillated clock signal 4 from the voltage controlled oscillator circuit VCO2 of the phase control circuit PC2 is given to two frequency divider circuits FD2, FD1 connected in series. Thus, the phase control circuits PC1, PC2 and the frequency divider circuits FD1, FD2 form a double PLL loop. The phase transfer functions Hs in the PLL circuit has a peak value 2 and decreased to 1/2.5 in comparison with a peak value 5 of the PLL circuit, then the PSRR (Power Supply Rejection Ratio) characteristic of jitter is improved accordingly.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is a PLL (phase long loop)
Regarding circuits, for example, PL used in GODEC (kneader/decoder) of digital telephone exchange equipment, etc.
This article relates to a technique that is effective when used in L circuits.

[Conventional technology]

Regarding C0DEC with built-in PLL circuit, for example,
It is described in "Integrated Circuit Application Handbook J," pages 593 to 600, published by Asakura Shoten on June 30, 1981.

[Problem that the invention seeks to solve]

An example of the PLL circuit used in the above CODEC is shown in the fifth section.
As shown in the figure. In the figure, the frequency of the oscillating clock signal φ4 output from the voltage-controlled oscillation circuit VCO is indirectly controlled by the control voltage Vc formed according to the phase difference signals U and d in the loop filter LF, and The above phase difference signal U supplied from the circuit PFC
and d.

By the way, the phase transfer function H(51) in such a PLL circuit can be obtained by the following equation, for example, in the book Basics of PLL and its Applications J by Hideo Tsunoda, published by Tokyo Denki University Press, April 20, 1983. It is described on pages 11 to 29 of . That is, the reference input clock signal φO
When the phase of the clock signal φ1 divided by θo1 is 01, the damping factor is ζ, the natural angular frequency is ωn, and the Laplace variable is S, H(51=θ, /θ0 = (2ζωns+ωn2)/( S2+2ζa+ns+a+n2) Here, the natural angular frequency ωn and the damping factor ζ are A, the frequency control gain due to the control voltage Vc of the voltage controlled oscillation circuit VCO, Δf the phase control gain due to the phase difference signals U and d, and the loop When the charging/discharging current value of the filter LF and the capacitance value of the load capacitance are set as the dividing ratio of the I and C1 frequency dividing circuit FD to 1/N, ωn= ((A/N)(Ilo)) ”'ζ−Δf /(
2ωnN).

The phase transfer function Ho (
3) exhibits a peak value as shown in FIG. 4 at ωn=l, for example, when N=4 ζ=0.1.

On the other hand, in a PLL circuit, the amount of jitter generated by noise superimposed on the power supply voltage is expressed as the jitter P S RR (
Posver 5uply Rejection
Rati.

) defined as a characteristic. In addition, this PSRR characteristic is
It has been experimentally confirmed that the smaller the peak value of the phase transfer function H (sl) shown in FIG. 4, the more improved it is.

As described in the above document, the peak value of the phase transfer function H(&) is inversely proportional to the magnitude of the damping factor. Therefore, in the conventional PLL circuit, the damping factor ζ is increased by increasing the phase control gain Δf of the voltage-controlled oscillator circuit VCO, which is relatively easy to set among the factors that determine the damping factor ζ. , P
Methods have been adopted to improve the jitter PSRR characteristics of LL circuits.

However, if this phase control gain Δf is made thicker than a certain level (for example, a signal processing device such as a digital signal processor connected to the subsequent stage of a PLL circuit will malfunction), the phase control gain Δf is The rate of change is limited to a value of about 25% or less.For this reason, it is difficult to improve the jitter PSRR characteristics of the PLL circuit beyond a certain level.

An object of the present invention is to provide a PLL circuit with further improved jitter PSRR characteristics.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, each PLL circuit is a phase comparison circuit.

A plurality of phase control circuits including a loop filter and a voltage-controlled oscillator circuit are substantially connected in series, and each output signal corresponds to the output signal of the last phase control circuit among the plurality of phase control circuits. It is constructed by a plurality of frequency dividing circuits in series, each of which is supplied as a branch clock signal to a phase control circuit.

[For production]

According to the above means, since the peak value of the phase transfer function of the entire PLL circuit can be reduced, the PLL circuit can be
The jitter PSRR characteristics of the L circuit can be improved.

〔Example〕

FIG. 1 shows a block diagram of an embodiment of a PLL circuit to which the present invention is applied. Although not particularly limited,
Circuit elements constituting each block in the figure are formed on a single semiconductor substrate such as single-crystal silicon using known semiconductor integrated circuit manufacturing techniques.

The PLL circuit PLL of this embodiment includes, but is not particularly limited to, two sets of phase control circuits P that are substantially connected in series.
It is composed of CI and PO2, and two frequency divider circuits FD2 and FDl in series that receive the output signal of the phase control circuit PC2, that is, the oscillation clock signal φ4. Among these, the phase control circuit PCI is composed of a phase comparator circuit PFC1, a loop filter LFI, and a voltage controlled oscillator circuit VCOL, and the phase control circuit PC2 is composed of a phase comparator circuit PF
C2, loop filter LF2 and voltage controlled oscillation circuit V
Consists of CO2.

In FIG. 1, a reference input clock signal φ0 supplied from the outside is input as a reference clock signal to a phase comparison circuit PFCI constituting a phase control circuit PCI. A frequency dividing circuit FD is connected to the other input terminal of the phase comparison circuit PFC1.
A frequency-divided clock signal φ1 supplied from I is input.

Here, the reference manual clock signal φ0 is supplied from, for example, a digital telephone exchange system (not shown), and its frequency is, for example, 8 KHz.

The phase comparison circuit PPCl compares the phases (frequencies) of the reference input clock signal φ0 and the frequency-divided clock signal φ1 to form a phase difference signal u1 or dl.

That is, when the phases (frequencies) of the reference human clock signal φ0 and the frequency-divided clock signal φ1 match, both the phase difference signals u1 and di are set to a low level. If the phase of the frequency-divided clock signal φI is delayed with respect to the reference human clock signal φ0, in other words, the frequency-divided clock signal φ1
When the frequency of the reference human clock signal φO is lower than the frequency of the reference human clock signal φO, the phase difference signal u1 is kept at a high level for a time corresponding to the phase difference, and the phase difference signal d1 is kept at a low level. On the other hand, if the phase of the divided clock signal φ1 is ahead of the reference human clock signal φ0, in other words, if the frequency of the divided clock signal φ1 is higher than the frequency of the reference input clock signal φ0, the phase difference signal d1 is The pi level is maintained for a time corresponding to the phase difference, and the phase difference signal u
l remains at low level.

Phase difference signal u formed by phase comparison circuit PFCI
1 and dl are supplied to the loop filter LFI and directly to the voltage controlled oscillation circuit VCO1.

As shown in FIG. 2, the loop filter LFI is selectively turned on according to the phase difference signals u1 and dl supplied from the charging current source C3I, the discharging current source DS1, and the 1-phase comparison circuit PPCl. Charging switch MO3
It includes FETQCI, a discharge switch MO3FETCDI, and a load capacitor C1 that is selectively charged and discharged by the current sources C3I and DSI. The charging current source C3I and the discharging current source DSL are both designed to flow the same current value ri.

The load capacitance CI of the loop filter LFI is the phase difference signal u
1 is set to a high level, MO3FETQC1 is turned on and charged, and its potential rises.

Further, the load capacitor C1 is discharged and its potential is lowered when the phase difference signal d1 is set to a high level and the MO3FET QDI is turned on. Loop filter L
The potential of the load capacitor C1 of the FI is set as the control voltage Vcl,
It is supplied to the voltage controlled oscillation circuit vcoi.

The voltage controlled oscillation circuit VCOL receives an oscillation clock signal φ2
form. The frequency of this oscillation clock signal φ2 is controlled by the control voltage Vcl supplied from the loop filter LFI, and is also directly controlled by the phase difference signals u1 and dl directly supplied from the phase comparison circuit PPCl.

The voltage controlled oscillator circuit vcoi includes an oscillation circuit that utilizes charging and discharging of a capacitor (not shown) and a current control circuit that supplies charging current to this capacitor.The charging current supplied to the capacitor from the current control circuit is controlled by the above-described control. Voltage V
Its value is controlled by cl and phase difference signals ul and dl, and as a result, the oscillation frequency of the voltage controlled oscillation circuit VCOI is controlled. That is, when the phase difference signal u1 becomes high level, the control voltage V
cl is increased and the charging current is increased.

As a result, the frequency of the oscillation clock signal φ2 output from the voltage-controlled oscillator circuit VCOI is increased.
While the phase difference signal u1 is at a high level, the charging current supplied from the current control circuit is temporarily further increased by the high level of the phase difference signal u1, and the frequency of the oscillation clock signal φ2 is temporarily further increased. be destroyed.

On the other hand, when the phase difference signal d1 becomes high level, the control voltage Vcl is lowered by the loop filter LFI, and the charging current is reduced. As a result, the frequency of the oscillation clock signal φ2 output from the voltage controlled oscillation circuit VCO1 is lowered. Further, while the phase difference signal d1 is at a high level, the charging current is temporarily further reduced by the phase difference signal d1, and the frequency of the oscillation clock signal φ2 is temporarily further reduced.

In this way, according to the control voltage Vcl formed based on the phase difference signals u1 and dl, the voltage controlled oscillator circuit VCO
The frequency control gain A1 as a voltage controlled oscillator circuit VCOI is determined by the rate at which the oscillation frequency of I is directly controlled.
is set. In addition, according to the phase difference signals u1 and dl, the oscillation frequency of the voltage controlled oscillator circuit VCOI is indirectly controlled depending on the rate at which the voltage controlled oscillator circuit VCOL
A phase control gain Δf1 is set.

The oscillation clock signal φ2 formed by the voltage-controlled oscillation circuit VCOI is supplied as a reference clock signal to the phase comparator circuit PFC2 forming the phase control circuit PC2.

The phase control circuit PC2 is composed of a phase comparator circuit PFC2, a loop filter LF2, and a voltage-controlled oscillation circuit VCO2, similar to the above-described phase control circuit PCI. The phase control circuit PC2 adjusts the above-mentioned phase with respect to the oscillation clock signal φ2 supplied from the voltage-controlled oscillator circuit VCOI of the phase control circuit Pct as a reference clock signal and the 0-clock signal φ3 supplied from the frequency dividing circuit FD2. Control circuit P
Performs phase control operation similar to CI. That is, the phase comparator circuit PFC2 compares the phases of the oscillation clock signal φ2 and the frequency-divided clock signal φ3, and forms a phase difference signal u2 or d2 depending on the phase difference.

These phase difference signals are supplied to the loop filter LF2 and also directly to the voltage controlled oscillation circuit VCO2. The loop filter LF2 has the same circuit configuration as the loop filter LFI of the phase control circuit PCI, as shown in FIG. supply

The voltage controlled oscillation circuit VCO2 receives an oscillation clock signal φ4.
form. The frequency of this oscillation clock signal φ4 is controlled by the control voltage Vc2 and indirectly controlled by the phase difference signals u2 and d2.

The frequency of the oscillation clock signal φ4 outputted from the voltage controlled oscillation circuit VCO2 is directly controlled according to the control voltage Vc2 supplied from the loop filter LF2, so that the voltage controlled oscillation circuit VC of the phase control circuit pc2 is controlled directly according to the control voltage Vc2 supplied from the loop filter LF2.
A frequency control gain A2 as O2 is set. Also,
The phase control gain Δf2 of the phase control circuit PC2 as the voltage controlled oscillation circuit VCO2 is set by the rate at which the frequency of the oscillation clock signal φ4 is indirectly controlled according to the phase difference signals u2 and d2.

The oscillation clock signal φ4 output from the voltage-controlled oscillation circuit VC02 of the phase control circuit PC2 is supplied to a clock pulse generation circuit CPG (not shown) and also to the input terminal of the frequency dividing circuit FD2. The clock pulse generation circuit CPG forms various operating clock signals using the oscillation clock signal φ4 and supplies them to other circuits such as the A/D-D/A conversion circuit in the C0DEC including this PLL circuit.

The frequency dividing circuit FD2 is constituted by, for example, a pinary counter having a configuration of several bits, and divides the oscillation clock signal φ4 supplied from the voltage controlled oscillation circuit VCO2 at a fixed frequency division ratio of 1/N2. A lock signal φ3 is formed.

Division clock signal φ formed by frequency dividing circuit FD2
3 is supplied to the phase comparator circuit PFC2 of the phase control circuit PC2, as described above, and is also supplied to the input terminal of the frequency dividing circuit FDI.

The frequency dividing circuit FDI divides the frequency divided clock signal φ3 supplied from the frequency dividing circuit FD2 at a fixed frequency division ratio of 1/N+ to form the frequency divided clock signal φ1. As mentioned above, this frequency-divided clock signal φ1 is supplied to the phase control circuit PC.
It is supplied to the phase comparator circuit PFCI of I.

As described above, the PLL circuit of this embodiment is provided with phase control circuits PCI and PO2 each consisting of a phase comparison circuit, a loop filter, and a voltage-controlled oscillation circuit.

A reference human clock signal φ0 supplied from the outside is input as a reference clock signal to one input terminal of the phase control circuit PCI, and a phase control clock signal φ0 supplied from the outside is input as a reference clock signal to one input terminal of the phase control circuit PC2. Circuit Pct
The output signal of , that is, the oscillation clock signal φ2 is input. Thereby, the two phase control circuits PCI and PO2 are substantially connected in series. The output signal of the voltage-controlled oscillation circuit VCO2 of the phase control circuit PC2, that is, the oscillation clock signal φ4, is generated by two frequency dividing circuits FD connected in series.
2 and FDI. The output signals of these frequency dividing circuits FD2 and FDI, that is, the frequency divided clock signals φ3 and φ1, are supplied to the other input terminals of the phase control circuits PC2 and PCI, respectively. As a result, the phase control circuit P
C1, PC2 and frequency divider circuits FDI, FD2 are double PL
Form an L loop.

Phase transfer function H(S) in the PLL circuit of this example
The phase of the reference human clock signal φ0 is divided by θO1 The phase of the clock signal φ1 is 01, and the damping factor and natural angular frequency of the phase control circuit PCI are C1 and ωn'
, when the damping factor and natural angular frequency of the phase-controlled m circuit PC2 are C2 and ωn2, H(S) = θ, /θO ((2ζH61fl 3+a+nl 2)×(2ζ
2ωn2 S+a+n22)1 /((S2 +2ζ3
6) fkl +ωn+ 2 )X (32+2
ζ2 ωn2 +ωn22)-32(2ζ1 ωn
l S+a+nl 2)).

Here, these natural angular frequencies ωnl, ωn2 and damping factors ζ1. C2 is the charging/discharging current value of the loop filter LFI of the phase control circuit PCI, C11 is the capacitance value of its load capacitance, AI is the frequency control gain of the voltage controlled oscillator circuit VCOI, Δfl is the phase control gain, and is the frequency dividing circuit FDI. The frequency division ratio of is set to 1/N1, and the phase control circuit P
The charging/discharging current value of the loop filter LF2 of C2 is 12, the capacitance value of its load capacitance is 02, and the voltage controlled oscillator circuit VC0.
2 frequency control gain is A2, and its phase I11 control gain is Δ
f2, when the frequency division ratio of the frequency divider circuit FD2 is 1/N2, ωn+ −((At /Nt )(1+ /C+ ))
”ωn2- ((A2 /N2) (I2 /C2))
"C1-Δf+/(2a+nlN1)C2-Δ
f2/(261n2N2).

Here, the phase transfer function Ho of the conventional PLL circuit mentioned above is
As in the case (a), for example, the frequency dividing circuits FD1 and F
The frequency division ratio of D2 is 1/N+, 1/N2, NlXN2 =
N-4 (NI = N2 = 2), and the loop filter L
The capacitance value C of the load capacitance of FI and LF2, and the current value 11 and I2 of C2 and the charging/discharging current source, are expressed as follows: 1+ /(, + = 12 /C2-1/C% The frequency of the voltage-controlled oscillator circuit vcot and VCO2 Control gain A' and A2 and phase control gain Δf and Δf2, AI/N+ = A2 / (NI XN2) - A/N
Δf+/N1=Δf 2 / (Ns XN2)
f/N.

Also, for example, when ωn11=l+1 ωf12yo2L/2 ζ+=0.05 C2-0,07, the phase transfer function H (sl exhibits the characteristics as shown in Fig. 3, and its peak value is “2 ”.

The peak value of this phase transfer function H(+1) is 1/2.5 smaller than the peak value of the conventional PLL circuit shown in FIG. 4, which is 15''.

As described above, in a PLL circuit, the PSRR characteristic that defines the amount of jitter generated by power supply voltage noise depends on the peak value of this phase transfer function H(S). Since the peak value of the phase transfer function H (31) of the PLL circuit of this example is 1/2.5 compared to the conventional PLL circuit,
Its PSRR characteristics are improved accordingly.

As shown in the above embodiment, when the present invention is applied to a PLL circuit used in C0DP:C of a digital telephone exchange, the following effects can be obtained. That is, (1) the PLL circuit is connected to two sets of phase control circuits that are substantially connected in series, each including a phase comparator circuit, a loop filter, and a voltage-controlled oscillator circuit, and the output of the subsequent phase control circuit. By configuring two frequency divider circuits in series, each of which receives a signal and supplies each output signal as a divided clock signal to the corresponding phase control circuit, the PLL
The effect is that the peak value of the phase transfer function H (31) as a circuit can be reduced.

(2) According to the above (11), it is possible to improve the jitter PSRR characteristics of the PLL circuit without increasing the phase control gain of the voltage controlled oscillation circuit.

(3) According to item (2) above, the S/N ratio as a communication system is improved while preventing malfunctions of communication processing devices such as digital signal processors connected to the subsequent stage of the PLL circuit.
The effect is that the ratio can be improved.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without advancing the gist of the invention. Nor. For example, in the embodiment shown in FIG. 1, the PLL circuit is composed of two sets of phase control circuits and frequency dividing circuits, but it may be composed of three or more sets of phase control circuits and frequency dividing circuits. In this case, the reference input clock signal is input as a reference clock signal to the first phase control circuit, and the output signal of each phase control circuit is supplied as a reference clock signal to the next phase control circuit.

Further, the output signals of the frequency dividing circuits in each stage are supplied as frequency divided clock signals to the corresponding phase control circuits. The loop filter shown in FIG. 2 may be provided with a circuit for initially setting the control voltage Vc to a predetermined level when the PLL circuit is activated. In addition, the block configuration of the PLL circuit shown in FIG. 1 includes, for example, a walking circuit and a phase difference amplifier circuit provided after the phase comparison circuit.
Various embodiments are possible.

The above explanation will mainly focus on the invention made by the present inventor and the C0DE of the digital telephone exchange device which is the background of the invention.
Although the description has been made of the case where the application is applied to a PLL circuit used in The present invention can be widely applied to a PLL circuit having a voltage-controlled oscillation circuit whose frequency is controlled according to a phase difference signal and a control voltage formed by these phase difference signals, or a semiconductor device incorporating such a PLL circuit.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the PLL circuit is replaced with a phase comparison circuit,
A plurality of phase control circuits including a loop filter and a voltage-controlled oscillator circuit are substantially connected in series, and the output signal of the last phase control circuit is received, and each output signal is frequency-divided by the corresponding phase control circuit. By configuring multiple frequency dividing circuits in series that are supplied as clock signals, P
The peak value of the phase transfer function of the LL circuit can be reduced, and the PSRR characteristics of the PLL circuit can be improved without increasing the phase control gain of the voltage controlled oscillator circuit. This can improve the ratio.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit to which the present invention is applied, FIG. 2 is a circuit diagram showing an embodiment of a loop filter of the PLL circuit of FIG. 1, and FIG. FIG. 1 is a characteristic diagram showing an example of the phase transfer function of the PLL circuit. FIG. 4 is a characteristic diagram showing an example of the phase transfer function of the conventional PLL1J path. FIG. 5 is an example of the conventional PLL circuit. FIG. PLL...PLL circuit, PCI, PO2...phase control circuit, PFCI, PFC2, PFC...phase comparison circuit, LFI, LF2. LF...Loop 74)'Lt
, VCOl, VCO2, VCO-...voltage controlled oscillation circuit, FDi, FD2, FD...
Frequency divider circuit, CPG...Clock pulse generation circuit. C3I, C32, C3... Charging current source, DSl, D
S2. DS...Discharge current source, QCI. QC2, QC, QDI, QD2. QD...N channel MO3FET, CI, C2, C...capacitor. Figure 1 Figure 2 Figure 3 Figure 4-tun
-+ LLI nFigure 5

Claims (1)

[Claims] 1. A phase comparison circuit that compares the phases of a reference clock signal and a frequency-divided clock signal and forms a phase difference signal according to the phase difference; and a loop filter that forms a control voltage according to the phase difference signal; and a voltage-controlled oscillation circuit whose oscillation frequency is controlled according to the phase difference signal and the control voltage, and the output signal of the previous-stage voltage-controlled oscillation circuit is used as the reference clock signal of the next-stage phase comparison circuit. A plurality of phase control circuits are arranged in series to be supplied, and output signals of a voltage controlled oscillator circuit of the final stage phase control circuit among the plurality of phase control circuits are input, and each output signal corresponds to the output signal of the voltage controlled oscillator circuit. A PLL circuit comprising: a plurality of frequency dividing circuits in a cascade configuration, which are supplied as the frequency divided clock signal of the phase control circuit. 2. The PLL circuit according to claim 1, wherein the PLL circuit is constituted by two sets of the phase control circuits and two sets of the frequency dividing circuits.