JPS63127614A - Peek detector circuit - Google Patents

Abstract

PURPOSE:To provide both sufficient responsiveness and excellent storage characteristic even to an analog input signal having a high frequency signal component by providing separately a peak detector means and a peak hold means separately and providing an arithmetic means applying OR operation to output signals of both means to generate a peak detector output signal. CONSTITUTION:The peak detector means 2 sets the settling time from the reception of an analog input signal till the detection of its peak state and detects the peak state of an analog input signal after the settling time elapses. Moreover, the peak hold means 3 sets the settling time to keep the peak state of an analog input signal given separately from the settling time to keep the peak state of the input signal over the holding time. Then analog arithmetic means 4 applies OR operation to a peak state output signal by the peak detector means 2 and a peak state keep signal by the peak hold means 3 to generate a peek detector output signal. Thus, the settling time and the holding time are set separately to apply the peak detection of the analog input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a peak detector circuit that detects a peak state of an analog input signal after a settling time has elapsed and outputs the peak state over a holding time.

(Prior Art) Peak detector circuits are extremely important electronic circuits when accurately receiving steep signal changes in analog transmission signals or when detecting transient phenomena with high precision.Generally, peak detector circuits are Therefore, it is required that the switching time from when an analog input signal is applied to when its peak state is detected is short, and that the device has excellent high-speed response characteristics.

Further, it is also required that the holding time for maintaining the peak state after the peak state is detected is long, and that the holding property is excellent.

FIG. 6 (A> is a circuit diagram showing an example of the configuration of a conventional peak detector circuit, and FIG. A peak detector output signal is applied to the base of transistor Q, and a peak detector output signal is output from the emitter of transistor Q. An emitter resistor R and a capacitor C are connected in parallel to the emitter of transistor Q, forming a time constant circuit. There is.

Next, the operation of the above conventional example will be explained. When an input signal is applied to the base of the emitter follower transistor Q, the transistor Q becomes conductive and the impedance between the collector and emitter becomes a small value r. Therefore, a charging current with a time constant rC flows into the capacitor C from the collector bias power supply. And the time constant r at this time
C governs the settling time t of the peak detector circuit, and the time constant rC determines the response characteristics of the peak detector circuit.

When the input of the analog input signal stops, the transistor Q
returns to a high impedance state, so a discharge current with a time constant RC flows out from the capacitor C via the resistor R. The time constant RC at this time governs the holding time of the peak detector circuit, and the holding characteristic of the peak detector circuit is determined by the time constant RC.

(Problem to be solved by the invention) However, according to the above-mentioned prior art, the transistor Q
Even in the conductive state, it is normal and necessary to have an impedance of about 5 to 6 Ω, so in order to speed up the settling time and improve the response characteristics of the peak detector circuit, the capacitance value of capacitor C should be made as small as possible. It is desirable to set it.

On the other hand, in order to improve the holding characteristics of the peak detector circuit, it is necessary to lengthen the holding time, and the capacitance value of capacitor C is limited by the above.
The resistance value of the resistor R is set to be large. However, according to this, the emitter potential of the transistor Q is increased, so the collector bias voltage must be set high. Moreover, since the output impedance of the peak detector circuit becomes high, many problems arise, such as difficulty in handling the peak detector output signal.

For this reason, in the prior art, it has been considered impossible to achieve both response characteristics and retention characteristics of the peak hold circuit, since it is contradictory to speed up the settling time and lengthen the holding time. As a result, there has been a problem in that it cannot be used to receive analog input signals that have particularly steep signal changes or to receive optical signal transmissions that have a direct current component.

Therefore, the present invention solves the above-mentioned antinomic constraints of the prior art and makes it possible to set the settling time and holding time separately, thereby providing a peak detector that achieves both response characteristics and retention characteristics. The purpose is to provide circuits.

[Means for solving problems]

To achieve the above objects, the present invention provides peak detector means for receiving an analog input signal and detecting its peak state after a settling time; and receiving the analog input signal and maintaining its peak state for a holding time. It is characterized by comprising a peak hold means and an analog calculation means for ORing the outputs of the peak detector means and the peak bold means and outputting a peak detector output signal.

(Function) Since the peak detector circuit of the present invention is configured as described above, the peak detector means sets a settling time from when an analog input signal is applied until detecting its peak state, and after the settling time has elapsed, the peak detector circuit The peak hold means operates to detect the peak state of the input signal, and the peak hold means sets a holding time separately from the settling time to maintain the peak state of the applied analog input signal, and maintains the peak state of the analog input signal over the holding time. The analog calculation means performs an OR operation on the peak state output signal output by the peak detector means after the settling time has elapsed, and the peak state maintenance signal maintained and outputted by the peak hold means during the holding time, and outputs the peak state output signal to the peak detector. It operates to generate an output signal, thereby independently setting the settling time and holding time to perform peak crossing of the analog input signal.

[Embodiments] Several embodiments of the present invention will be described below with reference to FIGS. 1 to 5. In the following description of the drawings, the same elements are given the same reference numerals to avoid duplication of the description.

FIG. 1 is a circuit diagram showing the configuration of the first embodiment. As shown in the figure, the peak detector circuit 1 is composed of a peak detector means 2, a peak hold means 3, and an analog calculation means 4. The peak detector means 2 to which an analog input signal is applied is provided with a first transistor Q1 to which this input signal is applied to the base, its emitter follower resistor R1 and a first capacitor C1 connected in parallel to the resistor R1. There is. The peak hold means 3 is also supplied with an analog input signal, and this peak hold means 3 includes a second transistor Q2 to which the analog input signal is applied, its emits follower resistor R2, and a resistor R.
A second capacitor C2 is connected in parallel to the first transistor Q1 in the conductive state.
The time constant C1 set by the impedance 2 and the capacitor C1 is the resistor R2 of the peak hold means 3.
and the time constant R2C2 set by capacitor C2.
It is set to be smaller than.

The analog calculation means 4 is provided with a third transistor Q3 whose base is supplied with an emitter follower output signal from the emitter of the transistor Q1. The calculation means 4 is also provided with a fourth transistor Q4 whose base is supplied with an emitter follower output signal from the emitter of the transistor Q2. And both transistors Q
3.

The emitter of Q4 is connected to a shared pull-down resistor R3, from which a peak detector output signal is generated. In addition, transistors Q, Q
, Q3. A bias voltage is applied to the collector of Q4.

Next, the operation of the above embodiment will be explained with reference to FIG.

FIG. 2 is a waveform diagram showing signal waveforms at various parts in the first embodiment. Note that the analog input signal has an uneven duty ratio and is shown as a waveform with sporadic pulse-like signal changes.

The capacitor C1 of the peak detector means 2 is selected to have a small capacitance @fFf in order to accelerate the settling time t1. Therefore, the analog input signal applied to the transistor Q1 makes the transistor Q1 conductive, and the capacitor C1
to charge. As a result, the peak state of the analog input signal is detected with a quick settling time ↑1, and the device responds quickly to changes in the analog input signal. This emitter follower output signal is then supplied to analog calculation means 4.

Note that when the supply of the analog input signal is stopped, the emitter follower output signal has a relatively fast time constant R1 set by the capacitor C1 and the emitter follower resistor R1.
Since it is attenuated by C1, the peak hold time T1 of the peak detector means 2 becomes short.

The capacitor C2 of the peak hold means 3 has a suitable capacitance (directly selected) in order to lengthen the holding time T2. Therefore, even after the analog input signal applied to the transistor Q2 has stopped, the capacitor C remains the emitter follower resistor. It discharges slowly based on the slow time constant R2C2 set by the resistance value of R2 and the capacitance value of capacitor C2.As a result, the peak state of the analog input signal is maintained for a long holding time T2, and the peak state of the analog input signal is maintained for a long holding time T2. The emitter follower output signal whose peak state is maintained for a long time is supplied to the analog calculation means 4.

The transistor Q3 of the analog calculation means 4 receives the output signals of the peak detector means 2 and the peak hold means 3.
．． Q4 forms an OR circuit.

Therefore, the peak detector output signal obtained from the analog calculation means 4 is a signal obtained by detecting the peak state of the analog input signal at the early settling time t1 set in the peak detector means 2, and is separately transmitted to the peak hold means 3. The peak state continues for the set long hold time T2. As a result, the peak detector circuit of the embodiment can provide a peak detector output signal that eliminates the trade-off between settling time and holding time in the prior art.

As an example, when the settling time of peak detector means 2 is set to 1 microsecond, the holding time of that means 2 is typically about 100 seconds of the settling time.
The time will be doubled to approximately 100 microseconds. Therefore, since the settling time of the peak hold means 3 can be set to about 100 microseconds, the holding time of the means 3 can be set as a long time of about 10 milliseconds. As a result, it is possible to provide a peak detector circuit that can sufficiently respond to analog input signals with high frequency components and can maintain a peak state for a long time.

Next, a second embodiment will be described with reference to FIG. Third
The figure is a block diagram showing the configuration of the second embodiment. In the figure, an analog input signal is applied to a plurality of peak detector means 21 set at different settling times and a plurality of peak hold means 31 set at different holding times. The outputs of all the peak detector means 21 and the peak hold means 31 are given to the analog OR calculation means 4, and the analog OR calculation means 4 generates a peak detector output signal.

According to this embodiment, a plurality of peak detector means 21
Since many types of settling times are set corresponding to the frequency bands of analog input signals, it is possible to realize a peak detector circuit with sufficient response characteristics even for wideband analog input signals.

Further, since a sufficiently long holding time can be set cumulatively in the plurality of peak hold means 31, the peak detector circuit can be provided with a long-time holding characteristic.

FIG. 4 is a block diagram showing the configuration of the third embodiment. The analog input signal is passed to the first peak detector means 22.
The signal is supplied to the analog OR calculation means 4 via the peak hold means 32, and is also supplied to the analog OR@ calculation means 4 via the peak hold means 32. Furthermore, the output of the first peak detector means 22 is supplied to the analog OR calculation means 4 via the second peak detector means 23,
The calculation means 4 generates a peak detector output signal.

According to this third embodiment, a fast settling time is set for the first peak detector means 22, and the peak state of the analog input signal is detected at high speed and supplied to the analog OR calculation means 4. Furthermore, the second peak detector means 23 is provided with the peak state of the analog input signal held for the holding time of the first peak detector means 22. Therefore, since the second peak detector means 23 has a relaxed response characteristic to the input signal, the settling time of the second peak detector means 23 can be set to be relatively long. As a result, the second peak detector means 23 has a longer holding time, so that the peak hold means 32 can be set to a more sufficient holding time. Furthermore, the analog OR operation means 4 provides a peak detector output signal that sufficiently responds to the analog input signal and that is cumulatively held in a peak state for a long time.

According to the third embodiment, the peak detector means and the peak hold means are connected in series and parallel to the analog input signal supply source and the signal source, so that the load on the supply source can be reduced. Must have.

FIG. 5 is a block diagram showing the configuration of the fourth embodiment.

The analog input signal is applied to the high speed analog peak detector means 24 and at the same time is applied to the low speed digital peak hold means 33. The low-speed digital peak hold means 33 has an AD input signal that inputs an analog input signal.
A converter (A/D>34, a comparator (COMP) 35 which receives a digitally converted input signal as one input, a DA converter (D/A) 36 which manually inputs the comparison output, and a memory (M [EMO) 37 is provided, and the readout signal from the memory 37 is given to the other input of the comparator 35.Then, the power signals of both the high speed analog peak detector means 24 and the low speed digital peak hold means 33 are analog ORed. The peak detector output signal is supplied to a calculation means 4, from which a peak detector output signal is generated.

According to the fourth embodiment, since the high-speed analog peak detector means 24 is set with a fast settling time, it can sufficiently follow steep changes in the analog input signal to detect the peak state, and the analog OR calculation means The output signal is supplied to 4. The comparator 35 of the low-speed digital peak hold means 33 digitally compares the read signal from the memory 37 and the digitally converted input signal. If the input signal is smaller than the read signal, the previous peak state stored in the memory 37 is supplied to the analog OR calculation means 4 via the DA converter 36. Further, if the input signal is larger than the read signal, the previous peak state stored in the memory 37 is updated to a new peak state output from the comparator 35, and the new peak state is converted to the analog OR calculation means. 4. As a result, in response to a sharp change in the analog input signal, the peak state detected by the high speed analog peak detector means 24 is held for a long period of time by the low speed digital peak hold means 33. Further, the analog OR calculation means 4 generates a peak detector output signal as an OR output of these output signals.

According to the fourth embodiment, the low-speed digital peak hold means 33 is provided with a memory 37 that can update the peak state one by one and hold it for a long period of time, thereby eliminating restrictions such as setting a time constant. A peak state can be maintained for a long period of time. In addition, there is a special effect that there is no fear that the peak state will be attenuated due to discharge.

The present invention is not limited to the above embodiments, and various modifications are possible. For example, in the description of the embodiment, the peak detector means and the peak hold means have been explained separately, but each can have the same function as the other.

Further, by using the emitter follower resistor as a variable resistor, selectivity and variability can be added to its function.

〔Effect of the invention〕

As described above, according to the present invention, the peak detector means for setting the settling time and the peak hold means for setting the holding time are separately provided, and furthermore, the output signal of the peak detector means and the output signal of the peak hold means are provided separately. By providing an analog calculation means for generating a peak detector output signal by performing an OR operation with Therefore, it is possible to provide a peak detector circuit that has sufficient response characteristics even for analog input signals having high-frequency signal components and also has excellent holding characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a waveform diagram explaining the operation of the first embodiment, and FIG. 3 is a block diagram showing the configuration of the second embodiment. 4 is a block diagram showing the configuration of the third embodiment, FIG. 5 is a block diagram showing the configuration of the fourth embodiment, and FIG. 6 is an explanatory diagram illustrating the prior art. DESCRIPTION OF SYMBOLS 1... Peak detector circuit, 2... Peak detector means, 3... Peak hold means, 4... Analog calculation means. Patent Applicant Sumitomo Electric Industries Co., Ltd. Representative Patent Attorney Yoshiki Hase Circuit Diagram of First Embodiment Figure 1 Input Signal 3T3 Q3+Q4 Output 1'! Waveform diagram of Example 2 Figure 2 Configuration diagram of Example 8 Figure 3 Configuration diagram of Example 3 Figure 4

Claims (1)

[Claims] 1. Peak detector means for receiving an analog input signal and detecting its peak state after a settling time has elapsed; and for receiving the analog input signal and maintaining its peak state over a holding time. peak hold means; and analog calculation means for performing an OR operation upon receiving the output of the peak detector means and the output of the peak hold means, wherein the settling time is set by the peak detector means, and the holding time is set by the peak hold means. 1. A peak detector circuit characterized in that a peak detector output signal is obtained by performing an OR operation on the outputs thereof by the analog calculation means. 2. The peak detector means and the peak hold means each have a separate emitter follower transistor to which the analog input signal is applied, and the peak detector means and the peak hold means each have a separate emitter follower transistor to which the analog input signal is applied, and the peak detector means and the peak hold means each have a separate emitter follower transistor to which the analog input signal is applied, and the peak detector means and the peak hold means each have a separate emitter follower transistor to which the analog input signal is applied. 2. The peak detector circuit according to claim 1, wherein separate time constants are set for each peak detector circuit. 3. The peak hold means includes an AD converter that AD converts the analog input signal, inputs the digital output signal of the AD converter to one input terminal, and inputs the past maximum peak state to the other input terminal. a comparator that compares these digital output signals with a past maximum peak state and outputs a comparison output signal; 2. The peak detector circuit according to claim 1, comprising a memory for storing the output signal as a new peak state, and a DA converter for inputting the comparison output signal of the comparator.