JPS63126265A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS63126265A JPS63126265A JP61271849A JP27184986A JPS63126265A JP S63126265 A JPS63126265 A JP S63126265A JP 61271849 A JP61271849 A JP 61271849A JP 27184986 A JP27184986 A JP 27184986A JP S63126265 A JPS63126265 A JP S63126265A
- Authority
- JP
- Japan
- Prior art keywords
- region
- circuit
- semiconductor
- semiconductor region
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 230000003071 parasitic effect Effects 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 230000000295 complement effect Effects 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路装置、特に、相補型M I
S FETを有する半導体集積回路装置に適用して有効
な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuit devices, particularly complementary MI
The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device having an SFET.
アナログ回路・ディジタル回路混在型の半導体集積回路
装置は、低消′R電力化を図るために、相補型MI S
FET(0MO3)で構成されている。Semiconductor integrated circuit devices with a mixture of analog circuits and digital circuits are equipped with complementary MIS in order to reduce power consumption.
It is composed of FET (0MO3).
前記アナログ回路のpチャネルM I S FETのソ
ース領域には動作電源電圧(例えば5[V])VeCが
印加されている。同様に、アナログ回路のnチャネルM
I S FETのソース領域には基準電源電圧(例え
ば0 [V] )Vs sが印加されている。An operating power supply voltage (for example, 5 [V]) VeC is applied to the source region of the p-channel MI S FET of the analog circuit. Similarly, the n-channel M of an analog circuit
A reference power supply voltage (for example, 0 [V]) Vss is applied to the source region of the ISFET.
一方、同様に、ディジタル回路のpチャネルMISFE
Tのソース領域には動作電源電圧Vc c。On the other hand, similarly, p-channel MISFE of digital circuit
The operating power supply voltage Vcc is applied to the source region of T.
nチャネルMISFETのソース領域には基準電源電圧
Vssが印加されている。A reference power supply voltage Vss is applied to the source region of the n-channel MISFET.
前記アナログ回路の電源電圧Vcc、Vssを供給する
夫々の電源配線は、ディジタル回路の電源電圧Vec、
Vssを供給する夫々の電源配線に対して独立に形成さ
れる。つまり、同一電位の夫々の電源配線は、1つの外
部端子(ポンディングパッド)から引出して即座に分割
し延在させるか、或は2つの外部端子から夫々独立に延
在させている。このように、独立に形成される電源配線
は、例えば、ディジタル回路側で発生した電源電位の変
動(ノイズ)を、アナログ回路の電g電位に伝達しない
ようにすることができる。The respective power supply wirings that supply the power supply voltages Vcc and Vss of the analog circuit are connected to the power supply voltages Vec and Vss of the digital circuit, respectively.
It is formed independently for each power supply wiring that supplies Vss. That is, each power supply wiring having the same potential is drawn out from one external terminal (ponding pad) and immediately divided and extended, or is extended independently from two external terminals. In this way, the independently formed power supply wiring can prevent, for example, fluctuations (noise) in the power supply potential generated on the digital circuit side from being transmitted to the electric potential g of the analog circuit.
この種の混在型の半導体集積回路装置においては、基板
に基板電位(n型基板の場合は動作電源電圧Vcc)、
ウェル領域にウェル電位(p型ウェル領域の場合は基準
電源を圧Vss)を夫々印加している。基板電位は、基
板と同一導電型でそれより高不純物濃度の基板電位供給
用半導体領域(ガートバンド)を介して印加されている
。ウェル電位は、ウェル領域と同一導電型でそれより高
不純物濃度のウェル領域供給用半導体領域(ガートバン
ド)を介して印加されている。この基板電位、ウェル電
位の夫々の供給は、ラッチアップを防止するように構成
されている6
なお、相補型M I S FETを有する半導体集積回
路装置においては、例えば1日経マグロウヒル社発行、
日経エレクトロニクス、1982年6月21号。In this type of mixed type semiconductor integrated circuit device, the substrate has a substrate potential (operating power supply voltage Vcc in the case of an n-type substrate),
A well potential (in the case of a p-type well region, a reference power supply voltage Vss) is applied to each well region. The substrate potential is applied via a substrate potential supply semiconductor region (girt band) that has the same conductivity type as the substrate and has a higher impurity concentration than the substrate. The well potential is applied via a well region supplying semiconductor region (girt band) which has the same conductivity type as the well region and has a higher impurity concentration than the well region. The respective supplies of the substrate potential and the well potential are configured to prevent latch-up.
Nikkei Electronics, June 21, 1982 issue.
pP135〜162に記載されている。It is described on pP135-162.
しかしながら、本発明者は、前述の混在型の半導体集積
回路装置において、次の問題点が生じることを見出した
。However, the present inventor found that the following problem occurs in the above-mentioned mixed type semiconductor integrated circuit device.
アナログ回路の電源電圧は比較的安定しているが、ディ
ジタル回路の電源電圧特に動作電源電圧Vccが著しく
変動する。ディジタル回路の動作電源電圧Vccの変動
は、アナログ回路の動作電源電圧Vccとの間に電位差
を生じさせる。このため、ディジタル回路の相補型MI
SFETで構成される寄生バイポーラトランジスタが動
作(ON)し、コレクタ電流が流れる。このコレクタ電
流は、アナログ回路の相補型M I S FETで構成
される寄生バイポーラトランジスタのベース電流となっ
てそれを動作させる。つまり、ディジタル回路側の寄生
バイポーラトランジスタとアナログ回路側の寄生バイポ
ーラトランジスタとで形成されるサイリスタが動作し、
ラッチアップを生じる。Although the power supply voltage of analog circuits is relatively stable, the power supply voltage of digital circuits, especially the operating power supply voltage Vcc, fluctuates significantly. Fluctuations in the operating power supply voltage Vcc of the digital circuit cause a potential difference between it and the operating power supply voltage Vcc of the analog circuit. Therefore, complementary MI of digital circuit
A parasitic bipolar transistor composed of an SFET is activated (ON), and a collector current flows. This collector current becomes a base current of a parasitic bipolar transistor constituted by a complementary M I S FET of an analog circuit and operates it. In other words, the thyristor formed by the parasitic bipolar transistor on the digital circuit side and the parasitic bipolar transistor on the analog circuit side operates,
Causes latch-up.
通常、基板には基板電位、ウェル領域にはウェル電位を
供給しているが、これにもかかわずラッチアップが生じ
るという問題があった。Normally, a substrate potential is supplied to the substrate and a well potential is supplied to the well region, but there is a problem in that latch-up occurs despite this.
本発明の目的は、相補型M I S FETで構成され
る複数の回路に夫々独立に形成される電源配線が接続さ
れる半導体集積回路装置において、ラッチアップを防止
することが可能な技術を提供することにある。An object of the present invention is to provide a technique that can prevent latch-up in a semiconductor integrated circuit device in which power supply wiring formed independently is connected to a plurality of circuits each composed of complementary MISFETs. It's about doing.
本発明の他の目的は、前記目的を達成すると共に、静電
気破壊耐圧を向上することが可能な技術を提供すること
にある。Another object of the present invention is to provide a technique that can achieve the above object and improve the electrostatic breakdown voltage.
本発明の前記ならびにその他の目的と新規な特徴は1本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち1代表的なものの概
要を説明すれば、下記のとおりである。An overview of one typical invention disclosed in this application is as follows.
相補型M I S FETで構成される複数の回路に、
夫々、独立に形成された電源配線が接続される半導体集
積回路装置において、前記回路間の基板主面部に、寄生
バイポーラトランジスタのコレクタ′領域として作用す
る、基板と反対導電型で所定の電位が印加された半導体
領域を設ける。In multiple circuits composed of complementary MI S FETs,
In a semiconductor integrated circuit device to which independently formed power supply wirings are connected, a predetermined potential of a conductivity type opposite to that of the substrate is applied to the main surface of the substrate between the circuits, which acts as a collector region of a parasitic bipolar transistor. A semiconductor region is provided.
上記した手段によれば、1つの回路で形成される寄生バ
イポーラトランジスタのコレクタ電流を。According to the above-mentioned means, the collector current of the parasitic bipolar transistor formed in one circuit.
他の回路で形成される寄生バイポーラ1ヘランジスタの
ベース電流となる前に前記半導体領域で吸収することが
できるので、夫々の寄生バイポーラトランジスタで形成
されるサイリスタの動作を防止し、ラッチアップを防止
することができる。Since the semiconductor region can absorb the current before it becomes the base current of the parasitic bipolar transistor formed in another circuit, it prevents the operation of the thyristor formed by each parasitic bipolar transistor and prevents latch-up. be able to.
以下1本発明の構成について、アナログ回路・ディジタ
ル回路混在型の半導体集積回路装置に本発明を適用した
一実施例とともに説明する。The configuration of the present invention will be described below along with an embodiment in which the present invention is applied to a semiconductor integrated circuit device of a mixed type with analog circuits and digital circuits.
なお、全回において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。In addition, in all the episodes, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
本発明の実施例Iであるアナログ回路・ディジタル回路
混在型の半導体集積回路装置の構成を第1図(概略平面
図)で示し、第1図の■−■線部分の具体的な構成を第
2図(要部断面図)で示す。FIG. 1 (schematic plan view) shows the configuration of a semiconductor integrated circuit device of mixed analog circuit and digital circuit type, which is Embodiment I of the present invention. It is shown in Figure 2 (cross-sectional view of main parts).
第1図に示すように、アナログ回路・ディジタル回路混
在型の半導体集積回路袋[2i1Gは、周辺部に複数の
外部端子(ポンディングパッド)BPが設けられている
。図示していないが、外部端子BPに近接する半導体集
積回路装置ICの周辺部には、人出力バッフ7回路が設
けられている。As shown in FIG. 1, the analog circuit/digital circuit mixed type semiconductor integrated circuit bag [2i1G] is provided with a plurality of external terminals (ponding pads) BP at the periphery. Although not shown, a human output buffer 7 circuit is provided in the peripheral portion of the semiconductor integrated circuit device IC near the external terminal BP.
半導体集積回路装置ICの中央部には、アナログ回路A
C及びディジタル回路DCが設けられている。An analog circuit A is located in the center of the semiconductor integrated circuit device IC.
C and a digital circuit DC are provided.
この種の半導体集積回路装置ICにおいては、電g電圧
用の外部端子BPが夫々独立に設けられている。アナロ
グ回路ACには、動作電源電圧Vce用の外部端子BP
(AVcc)、基準電源電圧Vss用の外部端子BP(
AVss)の夫々から引出された電源配線を接続してい
る。ディジタル回路DCには、動作11!!電圧Vcc
用の外部端子BP(DVcc)、基準電源電圧V s
s用の外部端子、、、””13 P (D V s s
)の夫々から引出された電源配線を、パ麹続している
。In this type of semiconductor integrated circuit device IC, external terminals BP for electric g voltage are provided independently. The analog circuit AC has an external terminal BP for the operating power supply voltage Vce.
(AVcc), external terminal BP for reference power supply voltage Vss (
The power supply wiring drawn out from each of the AVss) is connected. Digital circuit DC has operation 11! ! Voltage Vcc
external terminal BP (DVcc), reference power supply voltage V s
External terminal for s,...”13 P (DV s s
) are connected to the power supply wiring drawn out from each of them.
アナログ回路AC、ディジタル回路DCの夫々は、低消
費電力化を図るために、第2図に示すように、相補型M
I S FETで構成されている。アナログ回路AC
の相補型MISFETは、PチャネルMISFETAQ
PとnチャネルMISFETAQnとで構成されている
。ディジタル回路DCの相補型M I S FETは、
pチャネルMISFETDQPとnチャネルMI 5F
ETDQnとで構成されている。In order to reduce power consumption, each of the analog circuit AC and the digital circuit DC is a complementary type M circuit, as shown in FIG.
It is composed of IS FET. analog circuit ac
The complementary MISFET is P-channel MISFETAQ
It is composed of P and n-channel MISFETAQn. Complementary type MI S FET of digital circuit DC is
p channel MISFET DQP and n channel MI 5F
It is composed of ETDQn.
pチャネルMISFETAQp、DQpの夫々は、n−
型半導体基板1の主面に形成され、ゲート絶縁膜3、ゲ
ート電極4、ソース領域或はドレイン領域であるP4型
型半体領域6で構成されている。Each of p-channel MISFETAQp and DQp is n-
It is formed on the main surface of a type semiconductor substrate 1, and is composed of a gate insulating film 3, a gate electrode 4, and a P4 type half region 6 which is a source region or a drain region.
nチャネルMf 5FETAQn、DQnの夫々は、p
”型ウェル領域2の主面に形成され、ゲート絶縁膜3、
ゲート電極4、ソース領域或はドレイン領域であるn゛
型半導体領域5で構成されている。Each of n-channel Mf 5FETAQn and DQn is p
” is formed on the main surface of the type well region 2, and the gate insulating film 3,
It is composed of a gate electrode 4 and an n-type semiconductor region 5 which is a source region or a drain region.
pチャネルMISFETAQp、DQpの夫々れている
。基板電位供給用半導体領域5Aは、動作電源電圧AV
cc、DVecの夫々が印加さ九ている。nチャネルM
I 5FETA、Qn、DQnの夫々の近傍のウェル領
域2の主面部には、P4型ウェル領域電位供給用半導体
領域(ガートバンド)6Aが設けられている。ウェル領
域電位供給用半導体領域6Aは、基準電源電圧AVss
、DVsSの夫々が印加されている。p-channel MISFETAQp and DQp, respectively. The substrate potential supply semiconductor region 5A has an operating power supply voltage AV.
Each of cc and DVec is applied. n channel M
A P4 type well region potential supply semiconductor region (guard band) 6A is provided on the main surface of the well region 2 near each of I5FETA, Qn, and DQn. The well region potential supply semiconductor region 6A has a reference power supply voltage AVss.
, DVsS are applied.
前記基板電位供給用半導体領域5Aは、nチャネルMI
SFETAQn、DQnの夫々の半導体領域5と同一製
造工程で形成される。ウェル領域電位供給用半導体領域
6Δは、pチャネルMISFETAQp、DQpの夫々
の半導体領域6と同一製造工程で形成される。The substrate potential supply semiconductor region 5A is an n-channel MI
It is formed in the same manufacturing process as semiconductor regions 5 of SFETAQn and DQn. The well region potential supply semiconductor region 6Δ is formed in the same manufacturing process as the semiconductor regions 6 of the p-channel MISFETAQp and DQp.
このように構成されるアナログ回路ACとディジタル回
路DCとの間、具体的にはガートバンドとして使用され
る半導体領域SA間の半導体基板1の主面部には、半導
体領域7が設けられている。A semiconductor region 7 is provided on the main surface of the semiconductor substrate 1 between the analog circuit AC and the digital circuit DC configured as described above, specifically between the semiconductor region SA used as a guard band.
・半導体領域7は、半導体基板1と反対導電型で低、不
純物濃度のP−型半導体領域2Aと、その主面部jに形
成された、高不純物濃度のP°型半導体領域6Bとで構
成されている。- The semiconductor region 7 is composed of a P-type semiconductor region 2A having a conductivity type opposite to that of the semiconductor substrate 1 and having a low impurity concentration, and a P°-type semiconductor region 6B having a high impurity concentration formed on its main surface portion j. ing.
アナログ回路AC側の半導体領域7の半導体領域6Bに
は、アナログ回MAC及びディジタル回路DCに電源を
供給する外部端子BPに対して独立的に(或はアナログ
回路ACと共通に)設けられた外部端子BP(AVss
)から基準電源電圧AVssが供給される。ディジモル
回路DC側の半導体領域7の半導体領域6Bには、アナ
ログ回路AC及びディジタル回路DCに電源を供給する
外部端子BPに対して独立的に(或はディジタル回路D
Cと共通に)設けられた外部端子BP(DVsS)から
基準電源電圧DVssが供給される。In the semiconductor region 6B of the semiconductor region 7 on the analog circuit AC side, an external Terminal BP (AVss
) is supplied with a reference power supply voltage AVss. The semiconductor region 6B of the semiconductor region 7 on the side of the Digimol circuit DC is provided with an external terminal BP that supplies power to the analog circuit AC and the digital circuit DC (or a digital circuit D).
A reference power supply voltage DVss is supplied from an external terminal BP (DVsS) provided in common with C.
半導体領域2Aはウェル領域2と同一製造工程で形成さ
れ、半導体領域6BはpチャネルM I 5FETAQ
P又はDQpの半導体領域6と同一製造工程で形成さ九
る。The semiconductor region 2A is formed in the same manufacturing process as the well region 2, and the semiconductor region 6B is a p-channel MI5FETAQ.
It is formed in the same manufacturing process as the P or DQp semiconductor region 6.
このように、アナログ回路ACとディジタル回路DCと
の間に半導体領域7を設けることにより、−1−吟一
り
迭のようにラッチアップを防止することができる。By providing the semiconductor region 7 between the analog circuit AC and the digital circuit DC in this way, latch-up can be prevented as in the case of -1-Ginichiri.
シー まず、例えば、ディジタル回路DCの動作電源電
圧DVccに正の電位変動(ノイズ)を生じた場合、エ
ミッタ領域−ベース領域間に電流1+が流れ、寄生pn
p型バイポーラトランジスタT r rが動作(ON)
する、このトランジスタT r +は、ディジタル回路
DCのpチャネルM I S FETDQpのソース領
域である半導体領域6をエミッタ領域、半導体基板1を
ベース領域、アナログ回路ACのnチャネルM I S
F E T A Q nが設けられたウェル領域2を
コレクタ領域として構成される。First, for example, when a positive potential fluctuation (noise) occurs in the operating power supply voltage DVcc of the digital circuit DC, a current 1+ flows between the emitter region and the base region, causing the parasitic pn
P-type bipolar transistor T r r operates (ON)
This transistor T r + uses the semiconductor region 6 which is the source region of the p-channel M I S FET DQp of the digital circuit DC as the emitter region, the semiconductor substrate 1 as the base region, and the n-channel M I S of the analog circuit AC.
The well region 2 provided with FET A Q n is configured as a collector region.
トランジスタTr+のコレクタ電流■2は、ウェル抵抗
RJが存在するために、寄生npn型バイポーラトラン
ジスタT r 2のベースエミッタ間に電位差を生じさ
せ、それを動作させようとする。The collector current 2 of the transistor Tr+ generates a potential difference between the base and emitter of the parasitic npn bipolar transistor Tr2 due to the presence of the well resistance RJ, and tries to operate it.
トランジスタTr2は、ウェル領域2をベース領域、半
導体基板1をコレクタ領域、nチャネルMISFETA
Qnのソース領域である半導体領域5をエミッタ領域と
して構成される。The transistor Tr2 has a well region 2 as a base region, a semiconductor substrate 1 as a collector region, and an n-channel MISFETA.
The semiconductor region 5, which is the source region of Qn, is configured as an emitter region.
ところが、本発明により設けられた半導体領域のベース
領域に流れる前に、コレクタ電流工、戊は■4として積
極的に吸収することができる。つまり、半導体領域7は
、トランジスタT r 2の動作を防止し、コレクタ電
流I5及び■6の引込みをなくすことができるので、寄
生pnp型バイポーラトランジスタTr3の動作を防止
することができる。このため、トランジスタT r I
及びTr2またはTrs及びT r 2によるサイリス
タ動作を防止し、ラッチアップを防止することができる
。However, before flowing into the base region of the semiconductor region provided according to the present invention, the collector current can be actively absorbed as (4). In other words, the semiconductor region 7 can prevent the operation of the transistor Tr2 and prevent the collector currents I5 and 16 from being drawn in, thereby preventing the operation of the parasitic pnp bipolar transistor Tr3. Therefore, the transistor T r I
It is possible to prevent the thyristor operation by Tr2 or Trs and Tr2, and to prevent latch-up.
また、前記半導体領域7を高不純物濃度の半導体領域6
Bとその外周に沿って形成される低不純物濃度の半導体
領域2Aとで構成することにより、半導体基板工とのp
n接合耐圧を向上することができるので、特に、サージ
電圧の入力による半導体領域7の静電気破壊を防止する
ことができる。Further, the semiconductor region 7 is replaced with a semiconductor region 6 having a high impurity concentration.
B and the semiconductor region 2A with low impurity concentration formed along its outer periphery, the p
Since the n-junction withstand voltage can be improved, electrostatic damage to the semiconductor region 7 due to input of surge voltage can be particularly prevented.
本実施例■は、本発明の他の実施例である。 Example 2 is another example of the present invention.
本発明の実施例■であるアナログ回路・ディジ本実施例
Iは、第3図に示すように、トランジスタTr+のコレ
クタ領域として作用する半導体領域7を、ガートバンド
として使用する半導体領域5Aよりもアナログ回路AC
側、ディジモル回路DC側に夫々近接させている。As shown in FIG. 3, in this embodiment I, which is Embodiment ① of the present invention, the semiconductor region 7 that acts as the collector region of the transistor Tr+ is used as the analog circuit and the digital circuit. circuit ac
and the DC side of the Digimol circuit, respectively.
このように構成される半導体集積回路装置[Cは、前記
実施例Iと同様にラッチアップを防止することができる
。The semiconductor integrated circuit device [C configured in this manner can prevent latch-up as in the embodiment I above.
本実施例■は、アナログ回路・ディジタル回路混在型の
半導体集積回路装置をP型半導体基板で構成した、本発
明の他の実施例である。Embodiment 2 is another embodiment of the present invention in which a semiconductor integrated circuit device of mixed analog circuit and digital circuit type is constructed of a P-type semiconductor substrate.
本発明の実施例mであるアナログ回路・ディジタル回路
混在型の半導体集積回路装置の具体的な構成を第4図(
要部断面図)で示す。FIG. 4 (
(Cross-sectional view of main parts)
本実施例■は、第4図に示すように、半導体集積回路装
置ICをp”型半導体基板lとrl−型ウェル領域2と
で構成している。アナログ回路ACとディジタル回路D
Cとの間に設けられた半導体領域も、□
7は、n−型半導体領域2Aとn゛型半導体領域5B、
2・i
l;とで構成され、動作電源電圧AVcc、DVccの
夫々が印加される。In this embodiment (2), as shown in FIG. 4, a semiconductor integrated circuit device IC is constituted by a p'' type semiconductor substrate l and an rl- type well region 2.An analog circuit AC and a digital circuit D
The semiconductor region provided between
2·i l;, and each of the operating power supply voltages AVcc and DVcc is applied thereto.
このように構成される半導体集積回路装+itcは、前
記実施例Iと同様に、寄生n p nバイポーラトラン
ジスタT r +のコレクタ電流を積極的に吸収し、ラ
ッチアップを防止することができる。The semiconductor integrated circuit device +itc configured in this manner can actively absorb the collector current of the parasitic n p n bipolar transistor T r + to prevent latch-up, as in the above embodiment I.
以上、本発明者によってなされた発明を、前記実施例に
基づき具体的に説明したが、本発明は、前記実施例に限
定されるものではなく、その要旨を逸脱しない範囲にお
いて、種々変形し得ることは勿論である。As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.
例えば1本発明は、動作電源電圧或は基準電源電圧が夫
々独立に接続される入出カバソファ回路と内部回路との
間に、寄生バイポーラトランジスタのコレクタ領域とし
て作用する所定導電型の半導体領域を設けてもよい。For example, one aspect of the present invention provides a semiconductor region of a predetermined conductivity type that acts as a collector region of a parasitic bipolar transistor between an input/output cover sofa circuit and an internal circuit to which the operating power supply voltage or reference power supply voltage is independently connected. Good too.
また、本発明は、ガートバンドとして使用される前記電
位供給用半導体領域5A、6Aを設けな(でもよい。Further, in the present invention, the potential supply semiconductor regions 5A and 6A used as guard bands may not be provided.
本発明は、夫々独立した2系統以上の電源を有文1′
する半導体集積回路装置に広く適用することがでものに
よって得ることができる効果を簡単に説明すれば1次の
とおりである。The effects that can be obtained by widely applying the present invention to semiconductor integrated circuit devices that use two or more independent power supply systems can be briefly described as follows.
相補型M I S FETで構成される複数の回路に。For multiple circuits composed of complementary MIS FETs.
夫々、独立的に形成された電源配線が接続される半導体
集積回路′!A置において、ラッチアップを防止するこ
とができる。Semiconductor integrated circuits to which independently formed power supply wirings are connected! At position A, latch-up can be prevented.
第1図は、本発明の実施例!であるアナログ回路・ディ
ジタル回路混在型の半導体集積回路装置の構成を示す概
略平面図、
第2図は、第1図のII −1I線部分の具体的な構成
を示す要部断面図、
第3図は、本発明の実施例■であるアナログ回路・ディ
ジタル回路混在型の半導体集積回路装置の具体的な構成
を示す要部断面図、
第4Igは、本発明の実施例■であるアナログ回路・デ
ィジタル回路混在型の半導体集積回路装置の具体的な構
成を示す要部断面図である。
図中、IC・・・半導体集積回路装置、BP・・・外部
端子、AC・・・アナログ回路、DC・・・ディジタル
回路、Vec・・・動作電源電圧、V c c・・・基
準電′tXi!圧、Q・・・MISFET、1・・・半
導体基板、2・・ウェル領域、3・・・ゲート絶縁膜、
4・・・ゲート電極、5.5B、6.6B、7・・・半
導体領域、5A、6A・・・電位供給用半導体領域であ
る。Figure 1 is an example of the present invention! 2 is a schematic plan view showing the configuration of a mixed analog circuit/digital circuit type semiconductor integrated circuit device; FIG. The figure is a cross-sectional view of main parts showing a specific configuration of a semiconductor integrated circuit device with a mixture of analog circuits and digital circuits, which is an embodiment (■) of the present invention. 1 is a sectional view of a main part showing a specific configuration of a digital circuit mixed type semiconductor integrated circuit device. In the figure, IC...semiconductor integrated circuit device, BP...external terminal, AC...analog circuit, DC...digital circuit, Vec...operating power supply voltage, V c c... reference voltage' tXi! pressure, Q... MISFET, 1... semiconductor substrate, 2... well region, 3... gate insulating film,
4...Gate electrode, 5.5B, 6.6B, 7...Semiconductor region, 5A, 6A...Semiconductor region for potential supply.
Claims (1)
回路に、夫々、独立的に形成された電源配線が接続され
る半導体集積回路装置において、前記第1回路と第2回
路との間の基板主面部に、寄生バイポーラトランジスタ
のコレクタ領域として作用する、基板と反対導電型で所
定の電位が印加された半導体領域を設けたことを特徴と
する半導体集積回路装置。 2、前記半導体領域は、前記基板と反対導電型のウェル
領域と同一製造工程で形成される低不純物濃度の第1半
導体領域と、該第1半導体領域の主面部に設けられた、
第1半導体領域と同一導電型で前記MISFETのソー
ス領域又はドレイン領域と同一製造工程で形成される高
不純物濃度の第2半導体領域とで構成されていることを
特徴とする特許請求の範囲第1項に記載の半導体集積回
路装置。 3、前記半導体領域の近傍の基板主面部には、基板と同
一導電型でかつそれよりも高い不純物濃度で形成される
基板電位供給用半導体領域が設けられていることを特徴
とする特許請求の範囲第1項又は第2項に記載の半導体
集積回路装置。 4、前記第1回路はアナログ回路であり、前記第2回路
はディジタル回路であることを特徴とする特許請求の範
囲第1項乃至第3項に記載の夫夫の半導体集積回路装置
。[Claims] 1. A first circuit and a second circuit composed of complementary MISFETs.
In a semiconductor integrated circuit device in which power supply wirings formed independently are connected to the circuits, a main surface portion of the substrate between the first circuit and the second circuit acts as a collector region of a parasitic bipolar transistor. A semiconductor integrated circuit device comprising a semiconductor region having a conductivity type opposite to that of a substrate and to which a predetermined potential is applied. 2. The semiconductor region includes a first semiconductor region with a low impurity concentration formed in the same manufacturing process as a well region having a conductivity type opposite to that of the substrate, and a first semiconductor region provided on the main surface of the first semiconductor region.
Claim 1: The second semiconductor region is of the same conductivity type as the first semiconductor region and has a high impurity concentration and is formed in the same manufacturing process as the source region or drain region of the MISFET. 2. The semiconductor integrated circuit device described in 2. 3. A semiconductor region for supplying a substrate potential, which is formed on the main surface of the substrate near the semiconductor region and has the same conductivity type as the substrate and has an impurity concentration higher than that of the substrate, is provided. A semiconductor integrated circuit device according to scope 1 or 2. 4. The husband's semiconductor integrated circuit device according to claims 1 to 3, wherein the first circuit is an analog circuit, and the second circuit is a digital circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61271849A JPS63126265A (en) | 1986-11-17 | 1986-11-17 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61271849A JPS63126265A (en) | 1986-11-17 | 1986-11-17 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63126265A true JPS63126265A (en) | 1988-05-30 |
Family
ID=17505735
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61271849A Pending JPS63126265A (en) | 1986-11-17 | 1986-11-17 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63126265A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008140824A (en) * | 2006-11-30 | 2008-06-19 | Toshiba Corp | Semiconductor device |
-
1986
- 1986-11-17 JP JP61271849A patent/JPS63126265A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008140824A (en) * | 2006-11-30 | 2008-06-19 | Toshiba Corp | Semiconductor device |
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