JPS63110840A - Synchronization detection circuit - Google Patents

Abstract

PURPOSE:To allow one-Nth of a clock from a transmission line to detect synchronization and operate a protection circuit and to reduce power consumption by detecting a frame in a frame synchronization detection circuit with the aid of a parallel data signal after it is serial/parallel converted by one-Nth of the clock. CONSTITUTION:A serial/parallel conversion circuit 3 converts an input serial data signal A into one-Nth of a parallel data signal. At that time a timing detection circuit 2 detects frame synchronization from the signal A. The timing signal B is inputted to the circuit 3 through an AND gate 7, and a conversion timing is reset. A frame synchronization detection circuit 4 detects frame synchronization included in parallel data in the circuit 3, and the circuit 3 operates by a frequency one-Nthe of a clock frequency from the transmission line. A pulse generator circuit 5 inputting the detection signal outputs a control signal C used at a synchronization protection circuit 6 and a separator circuit 1. Recognition signals D to which synchronization is confirmed by the circuit 6 are applied to the gate 7 to control the circuit 3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a synchronization detection circuit, and in particular, detects a timing signal from a serial data signal on a transmission line, converts it into a 1/N parallel data signal, and decodes it. This invention relates to a synchronization detection circuit used in a circuit that performs.

[Conventional technology]

FIG. 2 shows an example of a conventional synchronization detection circuit.

This synchronization detection circuit consists of a frame synchronization detection circuit 22 and a synchronization protection circuit 23. Serial/Parallel Conversion Circuit 24 Consists of a pulse generation circuit 25 for resetting the serial/parallel conversion circuit 24. Note that 21 is a separation circuit.

The frame synchronization detection circuit 22 detects frame synchronization from a frame synchronization signal included in the serial data signal A, which is an input signal. The detection signal E is transmitted to the synchronization protection circuit 23.
This is the f number used to operate the pulse generation circuit 25 that resets the serial/parallel conversion circuit 24. The serial/parallel conversion circuit 24 also includes a pulse generation circuit 2 that resets the serial/parallel conversion circuit.
It is controlled by a reset signal F output from 5.

The signals used in these circuits operate at the clock frequency of the transmission line.

[Problem that the invention seeks to solve]

The conventional synchronization detection circuit described above has a configuration that operates at the same clock frequency as the transmission line, so when the clock frequency is high, for example, 50 MHz or higher, the hardware configuration is ECL (Emitter Couple).
d Logic), the hardware scale becomes large and power consumption increases, especially in the part of the synchronization protection circuit.

An object of the present invention is to eliminate such drawbacks and to provide a synchronization detection circuit with a small hardware scale and low power consumption.

[Means for solving problems]

The present invention provides a synchronization detection circuit used in a circuit that detects a timing signal from a serial data signal on a transmission line, converts it into a 1/N parallel signal, and decodes the signal. Serial/parallel converter that performs 1/N serial/parallel conversion on the serial data signal and converts it into a parallel data signal. A conversion circuit, a frame synchronization detection circuit that detects frame synchronization from a frame synchronization signal included in a parallel data signal, a pulse generation circuit that is controlled by the detection signal of the frame synchronization detection circuit and forms a control signal, and a pulse generation circuit that generates a control signal. It is characterized by having a synchronization protection circuit that receives a control signal and performs synchronization protection, and a gate circuit that controls the output from the timing detection circuit to the serial/parallel conversion circuit according to the output result of the synchronization protection circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This synchronization detection circuit includes a timing detection circuit 2 that detects a frame synchronization signal from a serial data signal on a transmission path, and a conversion timing that is reset by the detected frame synchronization signal. Serial/parallel conversion circuit 3 that performs parallel conversion
, a frame synchronization detection circuit 4 that detects frame synchronization at a frequency of 1/N from the frame synchronization signal included in the parallel data signal after conversion, and a pulse generation circuit 5 that generates a control signal based on the detection signal of the frame synchronization detection circuit. This control signal is input to the synchronization protection circuit 6 which operates at a frequency of 1/N, and the output from the timing detection circuit 2 to the serial/parallel conversion circuit 3 is controlled according to the output result of the synchronization protection circuit 6. and the AND gate 7. Note that 1 is a separation circuit.

Next, the operation of this embodiment will be explained.

The serial data signal A, which is the input signal from the transmission line, is
The serial/parallel conversion circuit 3 performs 1/N serial/parallel conversion into a parallel data signal. At this time, the timing detection circuit 2 detects a frame synchronization signal from the serial data signal A, and transmits the timing signal B to the serial/parallel conversion circuit 3 via the AND gate 7.
and reset the conversion timing.

The frame synchronization detection circuit 4 detects frame synchronization from the frame synchronization signal included in the parallel data signal output from the serial/parallel conversion circuit 3. In this case, the frame synchronization detection circuit is 1 of the clock frequency of the transmission path.
/H frequency. The detection signal is generated by the pulse generation circuit 5
The pulse generating circuit 5 generates a control signal C used in the synchronization protection circuit 6 and the separation circuit l.

The synchronization protection circuit 6 protects synchronization against errors occurring in the transmission path, and outputs an identification signal indicating whether synchronization is achieved. In this case, the synchronization protection circuit operates at a frequency that is 1/N of the clock frequency of the transmission line. The timing signal B for resetting the serial/parallel conversion circuit 3 is controlled by the AND gate 7 based on the identification signal.

In the above process, the only parts that operate based on the transmission line clock are the timing detection circuit 2 and the serial/parallel conversion circuit 3, and the frame synchronization detection circuit 4. Since the synchronization protection circuit 6 and the like operate with a clock that is 1/H of the transmission line clock,
If the clock frequency of the transmission path is high, for example 50MHz
In the above case, there are few parts of the hardware configuration that are performed by ECL, and not only can the scale of the hardware be reduced, but also power consumption can be reduced. Furthermore, if the clock frequency of the transmission line is, for example, about 10 MHz, most of the hardware configuration is TTL (Transistor Tractor).
nsistorLogic) to CM OS (Com
(plementary MOS), and power consumption can be significantly reduced.

〔Effect of the invention〕

As explained above, in the present invention, the frame synchronization detection circuit detects frame synchronization from the parallel data signal after 1/N serial/parallel conversion. It can be operated at a frequency that is 1/N of the clock frequency of the transmission line. Therefore, if the clock frequency of the transmission path is high, for example 50MHz or higher, the hardware configuration should be ECL.
This has the effect of reducing power consumption as well as reducing the amount of hardware required. In addition, if the clock frequency of the transmission line is, for example, about 10MHz, most of the hardware configuration can be changed from TTL to CMO.
It can be replaced with S, and has the effect of significantly reducing power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional synchronization detection circuit. 1... Separation circuit 2... Timing detection circuit 3... Serial/parallel conversion circuit 4...
Frame synchronization detection circuit 5... Pulse generation circuit 6... Synchronization protection circuit 7... AND gate

Claims (1)

[Claims] (1) After detecting a timing signal from a serial data signal on a transmission line, a synchronization detection circuit used in a circuit that converts it into a 1/N parallel signal and decodes it detects a frame synchronization signal from a serial data signal on a transmission line. The timing of serial/parallel conversion is reset by the timing detection circuit and the detected frame synchronization signal, and serial/parallel conversion performs 1/N serial/parallel conversion on the serial data signal to convert it into a parallel data signal. a frame synchronization detection circuit that detects frame synchronization from a frame synchronization signal included in a parallel data signal; a pulse generation circuit that is controlled by the detection signal of the frame synchronization detection circuit and forms a control signal; and control of the pulse generation circuit. Synchronous detection characterized by having a synchronization protection circuit that receives a signal and performs synchronization protection, and a gate circuit that controls the output from the timing detection circuit to the serial/parallel conversion circuit according to the output result of the synchronization protection circuit. circuit.