JPS63102369A - Vertical type mis field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a high speed operating function as the function of a switching device by a method wherein the 3rd semiconductor region of a 2nd conductivity type is formed in the 2nd semiconductor layer from the side opposite to the side of a semiconductor substrate or a 1st semiconductor layer. CONSTITUTION:An island shape p-type semiconductor region 3 is formed in the region 4 of a semiconductor layer 2 as 2nd drain region from the side opposite to the side of a semiconductor substrate 1 as 1st drain region. The region of a conductive layer 10 as a gate electrode facing a semiconductor region 31 is removed and a window 32 is formed. It is to be noted that, practically, the semiconductor region 31 can be formed by introducing a p-type impurity into the semiconductor region 2 with the semiconductor layer 10 which has the window 32 as a mask after the window 32 is formed in the conductive layer 10 as the gate electrode at the position facing the semiconductor region 31.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to improvements in vertical MXS field effect transistors.

Prior Art Conventionally, a vertical M■ having the configuration described below with reference to FIG.
S field effect transistors have been proposed.

That is, on the semiconductor substrate or the first semiconductor layer (hereinafter referred to as the semiconductor substrate for simplicity) 1 as the n+ type first drain region, it has the same n type but has a higher concentration than the semiconductor substrate 1. A second semiconductor layer 2 serving as a second drain region having a specific resistance is formed by, for example, epitaxial growth.

Further, in the semiconductor layer 2, from the side opposite to the semiconductor substrate 1 side, a first semiconductor region 3 serving as an n-type channel forming region forms a region 4 of the semiconductor layer 2 surrounded by the first semiconductor region 3. It is formed by a p-type impurity introduction process.

Furthermore, a second semiconductor region 5 as an n-type source region is formed in the semiconductor region 3 from the side opposite to the semiconductor layer 2 side.
It is formed by an n-type impurity introduction process so as to form a region 6 of the semiconductor region 3 surrounded by it.

Furthermore, a first conductive layer 7 serving as a source electrode, which is also connected to the semiconductor region 3, is ohmically connected to the semiconductor region 5 on the surface opposite to the semiconductor layer 2 side.

Further, a second conductive layer 8 serving as a drain electrode is ohmically connected to the semiconductor substrate 1 on the surface opposite to the semiconductor layer 2 side.

Further, on the semiconductor region 3, at least in the region above the region 6, a gate is formed so as to face the semiconductor layer 2 via an insulating layer 9 as a gate insulating layer which also extends to the region 41 of the semiconductor layer 2. A third conductive layer 10 is formed as an electrode.

Further, on the insulating layer 9, an insulating layer 11 as a living room insulating layer is provided.
is formed by embedding the conductive layer 10.

Note that the insulating layer 9 as the gate insulating layer described above actually extends continuously on the surface of the semiconductor layer 2 and the semiconductor regions 3 and 5 opposite to the semiconductor substrate 1 side, and also serves as an interlayer insulating layer. The insulating layer 11 extends over the entire area on the insulating layer 9, and exposes the semiconductor region 5 as a source region and the semiconductor region 3 as a channel forming region to the outside of the insulating layers 9 and 11. A window 12 is formed, and the conductive layer 7 as a source electrode is connected to the semiconductor regions 5 and 3 through the window 12 from above the insulating layer 11 as a living room insulating layer.

In addition, the semiconductor region 3 is actually formed by forming a conductive layer 10 as a gate electrode in an island shape on an insulating layer 9 as a gate insulating layer, and then using the conductive layer 10 as a mask inside the semiconductor region 2. It is formed in a so-called cell line method by introducing a p-type impurity into the structure. however,
This semiconductor region 3 extends slightly laterally below the conductive layer 10 so that a region 6 is formed. Further, the semiconductor region 5 is also formed in a so-called self-line method by introducing an n-type impurity into the semiconductor region 3 using the same conductive layer 10 as a gate electrode as a mask. However, this semiconductor region 5 extends horizontally only slightly below the conductive layer 10 to such an extent that the region 6 does not disappear.

The above is the configuration of the conventionally proposed vertical MIS field effect transistor.

According to the vertical MIS field effect transistor having such a configuration, a power source (not shown) is connected between the conductive layer 7 as the source electrode and the conductive layer 8 as the drain electrode.
is polarized with the conductive layer 7 side as the opening, and a load (not shown) is applied.
A control voltage is applied between the conductive layer 10 as the gate insulating layer and the conductive layer t'1F47 as the source electrode with the polarity positive on the conductive layer 10 side. For example, an n-channel layer is formed in the region 6 of the semiconductor region 3 as a channel formation region on the side of the insulating layer 9 as the gate insulating layer. and the semiconductor substrate 1 and the semiconductor layer 2 as the second drain region, the n-channel layer now formed in the region 6 of the semiconductor region 3, the semiconductor region 5 as the source region, and '' as the source electrode.
A current is supplied through the four conductive layers 7 in their order.

Further, a power source is connected through the load between the conductive layer 7 as the source electrode and the conductive layer 8 as the drain electrode, as described above, and the conductive layer 8 as the gate electrode 10 and the conductive layer 7 as the source electrode, when a control voltage is applied with a polarity such that the conductive layer 10 side is negative, the region 6 of the semiconductor region 3 as the channel formation region The n-channel layer mentioned above is not formed and therefore provides virtually no current to the load.

Therefore, the vertical MIS field effect transistor shown in FIG. 3 functions as a switching element.

However, the conventional vertical M! shown in FIG. In the case of the S field effect Sung I transistor, the conductive layer 7 as the source electrode
and the conductive layer 8 serving as the drain electrode, with the power supply connected through the load as described above,
When a control 211 voltage is applied between the conductive layer 10 as a gate electrode and the conductive layer 7 as a source electrode with a polarity such that the conductive layer side is negative, the voltage is applied to the region 6 of the semiconductor region 3. Since no n-channel layer is formed, a reverse bias is applied to the PN junction between the semiconductor layer 2 and the semiconductor region 3, and therefore, as shown in FIG. Since the expanding depletion layer 21 is formed and the MIS structure is made up of a conductive layer 10 as a gate electrode, an insulating layer 9 as a gate insulating layer, and a semiconductor layer 2 as a drain region, , semiconductor layer Li! From the surface of the insulating layer 9 side of the semiconductor substrate 1
A depletion layer 22 is formed that expands to the side.

Therefore, between the S conductive layer 10 as a gate electrode and the conductive layer 8 as a drain electrode, as shown in FIG.
Effect of depletion layer 22! It forms a capacitance Cgd given by the following equation, which is a series capacitance with Cd.

Cgd=C, -C, / (C, 10G,)...
(1) Note that between the conductive layers 10 and 8, there is also a capacitance ω consisting of the series capacitance of the capacitance due to the insulating layer 9 and the capacitance due to the depletion layer 21.
Although it is formed in parallel with the capacitor in equation (1), the following discussion will ignore that capacitor for the sake of simplicity.

By the way, the capacitances C1 and Cd in equation (1) are calculated by assuming that the dielectric constant of the insulating layer 9 is 811, the thickness is TI, the dielectric constant of the semiconductor layer 1ff12 is ε1, and the thickness of the depletion layer 22 is . , Roughly speaking, the length of the semiconductor region 2 of the conductive layer 10 in the left-right direction facing the region 4 is W. , if the length in the front-rear direction is the length if, the length in the left-right direction of the conductive layer 10 facing the depletion layer 21 is Wl, and the length in the front-rear direction is unit length, then the following equation is obtained. Given.

C1-ε・/T・・(W −2・Wl)・・・・
・・・・・・(2) C=ε/T −(W.−2−Wl)dd ・・・・・・・・・(3) Therefore, the conventional vertical M■S electric field shown in FIG. In the case of an effect transistor, (2) and (
3) By substituting the capacitances C1 and cd given by the formula, 1q
The gate-drain capacitance a has a capacitance ff1c,C given by equation (1), and has a relatively large value.

For this reason, the conventional vertical MISm field effect transistor shown in FIG. 3 has the drawback that the above-mentioned function as a switching element can only be obtained at a relatively low speed and is accompanied by a relatively large loss. was.

By means of solving the problems, the present invention provides a new vertical type M without the above-mentioned drawbacks.
This paper attempts to propose an IS field effect transistor.

Vertical according to the invention! MIS field effect transistor is
As in the case of the conventional vertical M■S field effect transistor described above in FIG. 3, on the semiconductor substrate or the first semiconductor layer as the first drain region having the first conductivity type,
A second semiconductor layer is formed as a second drain region, which has a first core type but has a higher resistivity than the semiconductor substrate or the first semiconductor layer; A second conductivity type opposite to the first conductivity type is added into the semiconductor layer of the semiconductor substrate or the second semiconductor layer from the side opposite to the first semiconductor layer side.
A first semiconductor region as a channel formation region having a conductivity type of a second semiconductor region as a source region is formed, and a first conductive layer as a source electrode is connected to the second semiconductor region and also connected to the first semiconductor region; , a second conductive layer as a drain electrode is connected to the semiconductor substrate or the first semiconductor layer, and a second conductive layer is connected to the first semiconductor region and extends to the second semiconductor layer -L. A third conductive layer as a gate electrode is formed so as to also face the second semiconductor layer via an insulating layer as a gate insulating layer.

However, in the vertical xM1s field effect transistor according to the present invention, in such a configuration, a second semiconductor layer is formed in the second semiconductor layer from above the semiconductor (from the plate or from the side opposite to the first semiconductor layer side). A third semiconductor region having a conductivity type is formed.

Effects and Effects According to the vertical MIS field effect transistor according to the present invention described above, a third semiconductor region having a second conductivity type is formed in the second semiconductor layer serving as the second drain region. Except for the conventional vertical MI described above in FIG.
Since the structure is similar to that of the S field effect transistor, a detailed explanation will be omitted, but as in the case of the conventional vertical MIS field effect transistor described above in FIG. a third conductive layer as a gate electrode and a first conductive layer as a source electrode with a power supply connected through a load between the conductive layer and the second conductive layer as a drain electrode. If a control voltage is applied between the first conductive layer and the first conductive layer with the first polarity being positive or negative, the gate isolation I1 layer of the first semiconductor region as a channel forming region is applied. A channel layer is formed on the insulating layer side of the transistor, thereby supplying current to the load. Moreover, as mentioned above, between the first and second conductive layers,
With the power source connected through the load, a controlled 21I voltage is applied between the third and first conductive layers, with the first conductive layer side facing a second polarity opposite to the first polarity described above. When the voltage is applied as follows, the above-mentioned channel layer is not formed in the first semiconductor region, and therefore no current is substantially supplied to the load. Therefore, the conventional vertical MIS described above in FIG.
Like a field effect transistor, it functions as a switching element.

Further, in the case of the vertical MIS field effect transistor according to the present invention, as described above, in a state where the power supply is connected between the first and second conductive layers (1 layer through the load), the third and first conductive layers are connected to each other through the load. Between the sexual layers, control 21I electric Jr, the first '4
j When the voltage is applied to the conductive layer side as the second polarity, the conventional vertical MI described above in FIG. 3 is applied between the first and second conductive layers.
As in the case of the S field effect transistor, the capacitance C due to the insulating layer as the gate insulating layer, the third conductive layer as the gate electrode, the insulating layer as the gate insulating layer, and the capacitance C as the second drain region. Due to the M1S configuration with the second semiconductor layer, the first depletion layer spreads from the insulating layer side as the gate insulating layer of the second semiconductor layer to the semiconductor substrate or first semiconductor layer side as the first drain region. 'a
By M Cd, eight villages corresponding to the above-mentioned equation (1) are formed.

However, a third semiconductor region having a second conductivity type is formed in the second semiconductor layer as a second drain region, and a third semiconductor region is formed between the third semiconductor region and the second semiconductor layer. Since a PN junction is formed, a second depletion layer is formed in the second semiconductor layer from the PN junction and extends vertically toward the semiconductor substrate or the first semiconductor layer as the first drain region. In addition, the third electrode as a gate electrode
A third depletion layer is formed that extends laterally below the conductive layer. Depending on the second depletion layer, a third conductive layer serves as a gate electrode and a second conductive layer serves as a drain electrode.
The third depletion layer does not form a capacitance between the third conductive layer as the gate electrode and the second conductive layer as the drain electrode. form, but
The third depletion layer has a larger thickness than the first depletion layer described above when viewed in the direction connecting the third conductive layer as the gate electrode and the second conductive layer as the drain electrode. have Therefore, the package corresponding to the above-mentioned formula (1) has a value that is significantly smaller than that of the conventional vertical MIS field effect transistor described above in FIG.

Therefore, according to the vertical MIS field effect transistor according to the present invention, the function as a switching element can be obtained at a much higher speed than in the case of the conventional vertical MIS field effect transistor described above in FIG. Significantly lower losses are involved than in the case of the conventional vertical MIS field effect transistor described above in FIG.

Embodiment 1 Next, a first embodiment of the vertical MIS field effect transistor according to the present invention will be described with reference to FIG.

In FIG. 1, parts corresponding to those in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The vertical MIS field effect transistor according to the present invention shown in FIG.
It has a similar configuration to an S field effect transistor.

That is, a p-type semiconductor region 3 is formed in an island shape in a region 4 of the semiconductor layer 2 as a second drain region from the side opposite to the semiconductor substrate 1 side as the first drain region. .

Moreover, the region facing the semiconductor region 31 of the conductive layer 10 serving as the electrode 1 is removed, and a window 32 is formed.

Note that the semiconductor layer [31 described above is actually formed by forming a window 32 on the conductive layer 10 as a gate electrode or the like at a position opposite to the semiconductor layer 1 or 31, and having the window 32. It can be formed by introducing p-type impurities into the semiconductor region Vi2 using the conductive layer 10 as a mask.

The above is the configuration of the first embodiment of the vertical MIS field effect transistor according to the present invention.

According to the vertical MIS field effect transistor according to the present invention having such a configuration, as in the case of the conventional vertical M]S field effect transistor described above in FIG. 7 and the conductive layer 8 as a drain electrode, a power source (not shown) is connected through a load (not shown) with the conductive layer 7 side being negative in polarity, If a control I lightning voltage is applied between the conductive layer 10 as a gate electrode and the conductive layer 7 as a source electrode with the polarity positive on the conductive layer 10 side, the semiconductor as a chitunnel formation region In the region 1iit6 of the region 3, a channel layer () is formed on the side of the insulating layer 9 serving as the gate insulating layer, so that the drain m? 4, a semiconductor substrate 1 and a semiconductor layer 2 as first and second train regions, an n-channel layer now formed in the channel region 6 of the semiconductor layer 13, and a semiconductor region 5 as a source region. , and the conductive layer 7 as a source electrode in that order.

Similarly, as in the case of the conventional 1i-type MIS field effect transistor described above in FIG. 3, the above-mentioned Similarly, with the power supply connected through the load, a control voltage is applied between the conductive layer 10 as the gate electrode and the conductive layer 7 as the source electrode, with the conductive layer 10 side being negative. When the voltage is applied with the polarity , the above-mentioned n-Brenner layer I is not formed in the region 6 of the semiconductor region 3 serving as the channel forming region, and therefore no current is substantially supplied to the load.

Accordingly, the vertical MIS field effect transistor shown in FIG. 1 functions as a switching element in the same way as the conventional vertical MIS field effect transistor 1 to transistor described above in FIG.

In addition, in the case of the vertical MIS field effect transistor according to the present invention shown in FIG. 1, and in the case of the conventional vertical MIS field effect transistor shown in FIG. As described above, a control t211 is applied between the conductive layer 10 as the gate electrode and the conductive layer 7 as the source electrode while the power source is connected to the conductive layer 8 through the load. When a voltage is applied with a polarity such that the conductive layer side is negative, since no n-channel layer is formed in region 6 of semiconductor region 3, a reverse bias is applied to the PN junction between semiconductor layer 2 and semiconductor region 3. Therefore, as shown in FIG. 2, the I) depletion extends laterally and vertically from the N junction! r! J21 is formed, and the conductive layer 10 as a gate electrode is formed.
Since it has an MIS configuration consisting of an insulating layer 9 as a gate insulating layer and a semiconductor layer 2 as a drain region, depletion spreading from the surface of the semiconductor region 2 on the insulating layer 9 side to the semiconductor substrate 1 side A layer 22 is formed. For this reason,
As in the case of the conventional vertical MIS field effect transistor described above in FIG. 3, between the conductive layer 10 as the gate electrode and the conductive layer 8 as the drain pole, As shown in FIG. ing.

c, d=ci ” C6/ (CH+Cd)...
(4) In the case of the vertical MIS field effect transistor according to the present invention shown in FIG. 1, the conventional vertical MIS field effect transistor described above in FIG.
As in the case of the S field effect i transistor, the conductive layer 1
Between 0 and 8, a capacitor consisting of a series capacitance of a capacitor a by the insulating layer 9 and a capacitor '88 by the depletion layer 21 is also formed in parallel with the capacitor of equation (4). Therefore, consider ignoring the capacity.

Further, as shown in FIG. 1, in the case of the vertical MIS field effect transistor according to the present invention, a semiconductor region 31 is formed in the semiconductor layer 2 as the second drain region so as to form a PN junction therebetween. Therefore, from that PN junction,
A depletion layer 23 extending vertically is formed in the semiconductor substrate 1 (ll), and a conductive layer 1 as a gate voltage collector is formed.
A depletion layer 24 is formed that extends laterally to below zero.

The depletion layer 23 does not form a capacitance between the conductive layer 8 serving as the gate electrode and the conductive layer 8 serving as the drain electrode.

Further, the depletion layer 24 is formed by the conductive layer 10 as a gate electrode.
and the conductive layer 8 as a drain electrode, and the depletion layer 24 is formed when viewed in the direction connecting the conductive layer 10 as the electrode and the conductive layer 8 as the train electrode, It has a larger thickness than the depletion layer 22 described above.

However, for simplicity's sake, we will ignore this capacity.

By the way, the capacitances C1 and cd in equation (4) are calculated by setting the dielectric constant of the insulating layer 9 to εi, as described above with reference to FIG.
, the thickness is T, and the dielectric constant of the semiconductor region 2 is C0.
, the thickness of the depletion layer 22 is Td, and the conductive layer 10
The length of the semiconductor region 2 in the left-right direction facing the region 4 is W. , the length in the front-back direction is taken as a unit length, and the quality of the conductive layer 10 in the left-right direction facing the depletion layer 21 is Wl
, +in, the length in the rear direction is taken as a unit length, furthermore, the length in the left-right direction of the semiconductor region 31 is taken as W2. , where the front-to-back direction expansion is the unit length and the length is given by the following formula.

C・=ε, /T−−(W.−2−Wl−Wl
1 1 2-2・w3) ・・・・・・・・・(5
)C=ε/1−−(W.−2−Wl−Wdd 2−2・W3) ・・・・・・・・・(6
) Therefore, in the case of the vertical MIS field effect l-run raster according to the present invention shown in FIG. 1, as in the case of the conventional vertical MIS field effect transistor described above in FIG. 10 and the conductive layer 8 as the drain 7 heptode, the capacitance C0° given by the formula (4) is obtained by substituting the capacitances c and cd given by the formulas (5) and (6). is the gate-drain distance ω. However, if we compare equations (2) and (3) with equations (5) and (6), it becomes clear that Compared to the case of , it has a small value.

Therefore, in the case of the vertical MIS field effect transistor according to the present invention shown in FIG. 1, the function as a switching element described in FIG. In comparison, it can be obtained at high speed and with only small losses compared to the case of the conventional vertical M[S field effect transistor described above in FIG.

Note that the above description merely shows one example of the present invention, and various modifications and variations may be made without departing from the spirit of the present invention.
There will be no changes.

[Brief explanation of the drawing]

FIG. 1 is a 18-line cross-sectional view showing a first embodiment of a vertical MIS field effect transistor according to the present invention. FIG. 2 is a diagram for explaining the gate-drain capacitance. Figure 3 shows the conventional vertical MIS field effect! - It is a route map showing transistors. FIG. 4 is a diagram for explaining the gate-drain capacitance. 1... Semiconductor substrate 2...
......Gate insulating layer 3.5...
... Semiconductor region 4 ..... Region 6 ......
...... Chitunnel region 7.8.10 ...... Conductive layer 9.11 ...... ...Insulating layer 12...
...... Window 21.22 ...... Depletion layer 31...
...... Semiconductor region 32 ......
...... Window applicant: Nippon Telegraph and Telephone Corporation Agent Attorney: 1) Masaharu Naka 5 )'+/ @Figure 1 Figure 2

Claims (1)

Claims: On a semiconductor substrate or a first semiconductor layer having a first conductivity type as a first drain region; A second semiconductor layer serving as a second drain region having a relatively high specific resistance is formed, and a second semiconductor layer is formed in the second semiconductor layer from a side opposite to the semiconductor substrate or the first semiconductor layer side. A first channel forming region having a second conductivity type opposite to the first conductivity type.
a second semiconductor region as a source region having a first conductivity type is formed in the first semiconductor region from the side opposite to the second semiconductor layer, and the second semiconductor region is formed as a source region having a first conductivity type; A first conductive layer serving as a source electrode, which is also connected to the first semiconductor region, is connected to the second semiconductor region, and a second conductive layer serving as a drain electrode is connected to the semiconductor substrate or the first semiconductor layer. conductive layers are connected to each other, and also face the second semiconductor layer via an insulating layer serving as a gate insulating layer extending over the first semiconductor region and over the second semiconductor layer. A vertical M having a structure in which a third conductive layer is formed as a gate electrode
In the IS field effect transistor, a third semiconductor region having a second conductivity type is formed in the second semiconductor layer from a side opposite to the semiconductor substrate or the first semiconductor layer side. A vertical MIS field effect transistor characterized by: