JPS63104297A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate a noise to a sense amplifier even when the accumulating information pattern of memory cells is changed by arranging a pair of bit lines by twisting it and a pair of bit lines belonging to an adjacent sense amplifier by twisting it. CONSTITUTION:The bit lines belonging to the sense amplifiers S12, S14 of a memory array are twisted in the middle, hence the inter-line parasitic capacitance C11B of bit lines, the inverse of B11, B12 is approximately equal to the inter-line parasitic capacitance C11C of the inverse of lines the inverse of B11, B12. Accordingly, the difference in the influences of noises by inter-line parasitic capacitance when a word line W11 is selected and all the accumulating information in cells M111, 121, 131, 141 are in level 'H' and when the word cells M111, 131 are in 'H' and cells M121, 141 are in level 'L' is eliminated excluding the end bit lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Sedentary Application] The present invention relates to a high-density semiconductor memory device, and more particularly to a semiconductor device using a folded bit line arrangement method.

[Conventional technology]

An example of a conventional folded bit line arrangement is the arrangement shown in Figure 2, which schematically shows the entire memory cell array section of a semiconductor memory device known as a general DRAM. . Here, a 4×4=16 memory cell array consisting of four word lines and four bit line pairs is shown. The operation of this semiconductor memory device will be outlined. For the sake of simplicity, an explanation will be given using an NMO8 circuit. When the word line W21 is selected, the level of B21 is L in the precharged state.
DRAM from oW level to HIGH level 5v single power supply
In this case, change from Ov to 5VKf. At this time, memory cell M211. connected to B21. M221°M2B5. M24
1 is the n bit line B21. B22°B23. B24
The stored information is transmitted to the bit line connected to the bit line.
〇On the other hand, bit line B21.

B22, B23, and B24 are connected to dummy cells that are omitted in FIG. 2. Following the bit line information, sense amplifiers 821, 822, 823, S2
To 4 = the feeling is amplified. M211, M
221. M2B5゜M241's accumulated information is H
If it is IGH, B21, B22, B23
, Is B24 HIGH in the precharged state? ! - Maintain, B21, B22, B23.

100 nib recharge state) (changes from IGH to LOW.256K, high density, fast DR such as IMega
In AM, bit line spacing, memory cell spacing, etc. are becoming smaller in order to prevent an increase in chip area, and the influence of parasitic capacitance between lines is gradually increasing.

Does the bit line in particular have minute noise? Since it is necessary to sense and amplify the sense and the potential change is large, consideration must be given to parasitic capacitance between bit lines.

In the case of the conventional example shown in Fig. 2, M211, M221, M
2B5.

When all the accumulated information of M241 is HIGH and when IVi2
11゜HIG to M2B5)l, M221, M2
The effect of the mutual shadow r'X on the μ bit lines differs depending on when 41 is Low.

In the former case, bit lines B21, B22, B2
3.

B 24 u HIGH C) Low Ki conversion j
B21 remains HIGH. B22. B2
3. It will be affected by the B24 am bit line. Especially when looking at 822, all parties will be influenced by both 321 and B22. C21A, C21B,
. . . This is a diagram illustrating the parasitic tolerance between C24A bit lines.

On the other hand, in the latter case, bit lines B21, 822, B2
3.

B24 changes from HIGH to LowKi and remains HIGH B21 , B22 , B23 , B2
4 Is it the influence of the bit line next to U? I will receive it. B22
Regarding this, it is influenced by 821, but not by B22. In other words, the amount of noise between the bit lines differs depending on the pattern of information stored in the memory cells, resulting in a difference in the operating margin of the semiconductor memory circuit. [Problems to be Solved by the Invention] As mentioned above. However, in the conventional memory cell array method, there is a difference in the operating margin of the semiconductor memory circuit which is formed into the storage information pattern 7 of the memory cell, so when testing the characteristics and functions of the semiconductor product, at least two Must be tested with a pattern. If there is another pattern between the memory cell arrangement and the bit line arrangement, etc., always use the second pattern.
It becomes necessary to test seven times. In high-density, high-speed semiconductor memory devices, the influence of parasitic capacitance tends to increase, and the measurement time for one test pattern also increases from 64 to 25.
6 and IMega, it will be at least 4 times and 16 times more. Therefore, it is considered that the conventional bit line method has the disadvantage that the test time is long. Enter (2n-1) L times n into a pair of bits i, and 2n
The memory cell array has a memory cell array in which a pair of bits ar (n-1) belonging to adjacent sense amplifiers are inputted into n parts.

Here, n is a natural number 0 [Example] Next, the present invention will be explained with reference to the drawings.
The bit lines belonging to the special ah sense amplifiers 812 and 814 of this embodiment are constructed in the middle. It is about being n. In this case, the inter-bit line parasitic capacitance C41B between the bit lines Bll and 812 can be made to be approximately larger than the inter-bit line parasitic capacitance C11C between the bit lines Bll and B12. Similarly, Cl2B and Cl2C, and C13B and C13C, can be set to the same degree.

Now, word line W11 is selected, memory cell Mill
, M121. M131. Consider the case where the accumulated information of M141 is sensed and amplified.
When all the accumulated information of B5 and M141 is HIGii and M
ill, M2B5 is HIG) I, M121. M141
When qVC is LOW, there is no difference in the influence of noise qVC in the line-to-line parasitic capacitance between the bit lines except for the bit line r at the end.

Mill, M121, M2B5, M141
If the accumulated information of is all RIG)i, the bit line Bl
l, B12.

813, B14 changes from)IIG)i to LOWK,
Bll.

B12, B13, B14 are HIGli's 11m
As for the bit line B12, the parasitic capacitance C1113 causes
Cl2Ak Intermediate, TeB12's shadow IJke received. Also B1
As for 2, Parasitic Yado C■C? It is influenced by Bll through. Parasitic capacitance between bit lines, sense amplifier 512i2
Of course, you will be affected by the noise of N.

On the other hand, Mill, M131 is HIGH, M121. M14
When 1ULowrS, By) line Bll, B12
, B13.

B14 changes from HIGH to LOW, Bll,
B12°B13, B14 remain HIGH n
Ru. Is pit line revision 2 C11B'? bit line B12 receives a shadow 4!1 from Bll via C11Ct- and from B12 via Cl2Ak. In other words, the sense antenna 7'812 is affected by the noise # of 92N.

〔Effect of the invention〕

In accordance with the above-described method, the present invention is to arrange the bit lines in the same manner, and to make the noise to the sense amplifier due to the parasitic capacitance between the bit lines not change even if the storage information pattern of the memory cell changes. Can be done. This has the effect of suppressing the increase in measurement time required to test the characteristic functions of semiconductor memory devices, which are becoming increasingly dense.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of a memory cell array according to a first embodiment of the present invention, and FIG. 2 is a conceptual diagram of a conventional memory cell array. Bll, Bll, B12. B12...
..., B24, B24 is the bit line, CIIA,
CIIB, CI IC,..., C24
A is the parasitic capacitance between bit lines, Mill, M121.・
..., M241. MH memory cell, 811. S12. ......, 52
4fl sense amplifier. Agent: Patent Attorney Susumu Uchihara 75, 1 leaf 1 figure 2 foils

Claims (1)

[Claims] In a semiconductor memory device equipped with a bit line folded sense amplifier, where n is a natural number, (2n-1) twists are added to a pair of bit lines belonging to the first sense amplifier to form 2n parts. 1. A semiconductor memory device characterized in that a pair of bit lines belonging to adjacent amplifiers are arranged in n parts with (n-1) twists.