JPS6292051A - memory device - Google Patents

Abstract

PURPOSE:To obtain a memory device which can easily increase the width of a data bus as necessary by providing a memory, plural data buses and a means which selects one of these data buses and connects it to the memory. CONSTITUTION:Based on the contents of a signal SELM1, a multiplexer 2 and a driver 4 select one of the input data buses Data-In and the output data buses Data-Out respectively in terms of the first byte and connect these selected buses to a memory 1. While a multiplexer 2' and a driver 4' select two of the buses Data-In and Data-Out respectively for the second byte by the contents of a signal SELM2 and connect these selected buses to a memory 1'. Here the different memories and data buses receive the accesses. Thus the writing or reading actions are possible exactly at a time to memories. This ensures the effects of extension with data buses.

Description

[Detailed Description of the Invention] [Overview] Writing and reading data to and from a co-memory has conventionally been performed using a data bus having a fixed bus width, and it has been impossible to easily expand the bus width. The present invention discloses a technology related to the configuration of a memory device that allows the bus width of an input/output data bus to be easily expanded as necessary. This makes it possible to provide a memory device that is highly flexible and expandable, such as being able to easily handle processes that require.

Field of Industrial Application] The present invention relates to a memory used in an information processing device, in which the data bus has a normal bus width when high speed is not required, and the bus width is changed when high speed is required. This invention relates to a memory circuit that can be easily expanded.

[Prior Art] Writing data to and reading data from memory in an information processing device is performed through an input data bus or an output data bus (a common bus may be used for input and output). . The bus width (number of read/write bits) of these data buses is fixed and constant in conventional devices; It cannot exceed the size determined by the width.

Some types of information processing equipment are designed to allow storage capacity to be expanded by adding more memory, but even in this case, the bus width of the data bus remains constant without being expanded, and p ) expansion is performed in the depth direction of the address l'''1, and the amount of data that can be read/written in - times does not increase.

[Problems to be Solved by the Invention] When performing image processing using an information processing bag, there are many processes in which a large amount of data is read out from memory at high speed at once, and the speed affects performance.

In addition, as information processing devices are being used in a variety of ways these days, it is important to expand the address direction of memory when using the same hardware, and to expand the bus width of the data bus when using the same hardware. It has been desired to develop a memory device that can flexibly respond to conditions such as expansion of the memory device to read/write a large amount of data in a short period of time.

In the conventional memory devices mentioned above, it was possible to expand in the address direction by adding memory, but even in this case, it was impossible to expand the bus width of the data bus. In order to meet the demand for reading and writing large amounts of data at high speeds, the only way to forcefully expand the width of the data bus was to rebuild the peripheral circuits.

In view of these conventional problems, it is an object of the present invention to provide a memory device in which the bus width of the data bus can be easily expanded as required.

[Means for Solving the Problems] According to the present invention, this object is to provide a memory, a plurality of data buses, and a selection of one of the plurality of data buses. This is achieved by a memory device characterized in that the memory device is provided with means for connecting the memory to the memory, and when additional memories are added, each memory is connected to a different data bus and controlled so as to perform writing or reading at the same time.

"Function" If you wish to expand the bus width of the data bus in the L memory device, you can connect multiple memories to different input data buses and use these manual data buses in parallel. .

As a result, a substantial data bus expansion is realized, and a large amount of data can be written to the memory at high speed.

Furthermore, when reading data, different output data buses may be connected to different memories, and the data simultaneously read from each memory may be sent to each of these output data buses.

By using data buses in parallel in this way, the bus width can be substantially expanded and memory contents can be read out at high speed. Also, if each data bus is used independently,
It is possible to use it as a memory device having a data bus having a normal constant bus width, and in this case, a plurality of memories can be used in a form in which the area is expanded in the address direction.

[Embodiment] FIG. 1 is a diagram showing the configuration of a memory device according to an embodiment of the present invention, in which 1 is a memory and 2 is a multiplexer (MPX).
, 3 is a decoder (DEC), 4 is a driver (DV)
, 51 to 5n are input data buses each having a bus width of 1 byte, 6 is an address bus for upper addresses, and 7 is an address bus for upper addresses.
is an address bus for lower addresses; 8. -8n represent output data buses each having a bus width of 1 byte. The signal SELM is a multi-bit signal that is sent along with information indicating the validity of the memory to the multiplexer 2 or driver 4 on a plurality of data buses 51 to 5n or 8. ~
It has information that instructs which bus among 8n should be selected.

Access to this memory device is performed using an upper address that identifies the memory device and a lower address that is an address within the memory.

FIG. 2 shows an example of the configuration when the above-mentioned memory device is expanded.

In FIG. 2, each reference numeral is the same as in FIG. 1, and the memory device added for expansion is indicated by adding a ' (dash) to each reference numeral.

FIG. 2 shows the case where the input and output data buses are each expanded to 2 bytes. That is, depending on the content of the signal SELMI, the multiplexer 2 selects the input data bus (Data-In) from the long output data bus (Data-In) for the first byte bus.
-Out), the driver 4 selects 1 and connects it to the memory 1, while the second byte bus is connected to the input data bus (Data bus) according to the contents of the signal SELM2.
-I n), the multiplexer 2' also connects the output LTI data node (Data-○ut) to 1)
Driver 4' selects 2 and connects 'C' to memory 1'.

Then, the lower address is decoded by the decoder 3 or ζJ decoder 3' into a value that allows access to the corresponding memory, and then the lower address allows simultaneous access to memory 1 and memory 1'.

, : Since the memory, data, and bus to be accessed are different, as described above, it is possible to read or write data to and from the memory at the same time, thereby achieving the effect of expanding the data bus.

This example shows the case where the bus width is expanded to 2 bytes, but as is clear from the figure, it is possible to expand the data bus to a width of N bytes by adding memory corresponding to the data bus. It is.

Furthermore, if the bus width does not need to be expanded, it is clear from the structure shown in (1) and (2) (7) and (d) that expansion in the address 7i'' direction as in the prior art can be achieved by adding memory.

[Effects of the Invention] According to the memory device of the present invention, the bus width of the data bus can be easily expanded as needed, and the address direction can also be expanded, so it can be used flexibly for various uses with different usage conditions. The effect is great because it is possible to realize an information processing device that is adaptable and highly expandable.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a memory device according to an embodiment of the present invention, and FIG. 2 is a diagram showing an example of the configuration when the memory device is expanded. 1.1'...Memory, 2.2'...Multiplexer, 3.3'...Decoder, 4.4'...Driver, 51-5n...Input data bus, 6...・Address bus for upper addresses, 7...Address bus for lower addresses, 8. ~8n... Data bar for output 7) Indication - αd Meshiri training fee 11
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Claims (1)

[Claims] A memory, a plurality of data buses, and means for selecting one of the plurality of data buses and connecting it to the memory are provided, and when the memory is expanded, each memory is connected to a different data bus and data can be written simultaneously. A memory device characterized in that it is controlled as if it were read or read.