JPS627124A - Annealing device for semiconductor substrate - Google Patents

Abstract

PURPOSE:To suppress the degradation of the ion-implantation layer by providing a molecular ray source generating one molecular ray consisting of one of the substrate compositional elements within a vacuum chamber, and anneal- processing the ion-implantation layer of the substrate in a molecular ray atmosphere. CONSTITUTION:A molecular ray source 3 is attached on the wall surface of a vacuum chamber 1 and filled with especially slippable material of the material constituting the substrate 6 to be annealed. A suitable arsenic molecular ray is generated by heating within the vacuum chamber 1. An ion-implantation GaAs substrate 6 is mounted in the auxiliary chamber 7 of the annealing device, the auxiliary chamber 7 is exhausted of air to the vacuum degree of 1X10<-9>Torr, a gate valve 8 is opened, the ion-implantation GaAs substrate is transferred to the vacuum chamber 1 and held in a suscepter 5, and the gate valve 8 is closed. The vacuum chamber 1 exhausted of air to 1X10<-10>Torr, the arsenic molecular ray source 3 is heated to the temperature of 350-450 deg.C, and the ion-implantation substrate 6 is heated with an infrared ray lamp 4 to 900 deg.C for a few seconds to perform annealing.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a semiconductor device manufacturing apparatus, and more specifically,
The present invention relates to an annealing treatment apparatus for an ion-implanted layer of a semiconductor, a dielectric material, a magnetic material, etc. into which an ion-implanted conductive layer or an n-type conductive layer is implanted.

<Prior art> Generally, when applying ion implantation to semiconductors, dielectrics, magnetic materials, etc., lattice defects induced during implantation are not completely recovered even by subsequent heat treatment, and even more inconveniently, heat treatment Sometimes some of the constituent elements of the substrate may be removed. Such protrusion of constituent elements generates a large number of vacancies in the substrate crystal, and these vacancies, or these vacancies and implanted impurities, or complex defects caused by the combination of vacancies and substrate constituent elements, etc. It behaves in a complicated manner, and has caused significant damage to the characteristics of electronic devices using this type of ion corporation method.

To deal with these inconveniences, in order to suppress the generation of vacancies due to the extraction of substrate constituent elements and at the same time to suppress the extraction of implanted impurities and to improve the quality of the implanted layer, implantation after the ion implantation process is performed. A so-called cap annealing method has been devised in which the surface of the layer is covered with a protective film such as an insulator or dielectric to thermally recover the crystallinity. However, such a cap annealing method is not a foolproof method as it requires the time and effort of forming a protective film on the surface of the injection layer by a vapor deposition method or a CVD method prior to thermal recovery. Due to the difference in thermal expansion coefficient between the protective film and the substrate material, strain is introduced to the surface of the implanted layer during annealing, causing the distribution of ion-implanted elements to deviate significantly from the set distribution, resulting in problems such as deterioration of controllability of device characteristics and performance. there were.

On the other hand, as a way to avoid the above-mentioned problems caused by keep annealing, for example, when annealing an ion-implanted layer on a QaA8 substrate, an appropriate amount of AsH3 (arsine) is added without covering it with a protective film made of a dielectric or an insulator. A method has been proposed in which a substrate is annealed in a pressurized inert gas.

The above-mentioned capless annealing method eliminates the trouble of forming a protective film (cap), and also eliminates the possibility that the distribution of ion-implanted elements will be significantly shifted due to the influence of strain caused by the difference in thermal expansion coefficient between the substrate and the protective film during annealing. In addition, during the heat treatment of the ion-implanted GaAs substrate, the decomposition of As, which has a particularly high decomposition pressure, is suppressed by the As pressure caused by the dissociation of ASH3, so that an ion-implanted layer of relatively high quality can be obtained. However, the AsH gas used in this annealing method is highly toxic and has a serious drawback in practical use.

<Object of the Invention> Therefore, the object of the present invention is to eliminate the use of a highly poisonous gas such as the ASH3 gas, eliminate the trouble of forming a protective film, and improve the crystal quality of the ion-implanted layer caused by the decomposition of the constituent elements of the substrate during annealing. An object of the present invention is to provide an entire annealing apparatus for crystal recovery of an ion-implanted layer that can suppress a decrease in crystallinity.

<Example> Fig. 1 is a schematic diagram showing an ion-implanted layer annealing device according to an embodiment of the present invention, and Fig. 2 shows an example of implanting Si (silicon) ions into an undoped semi-insulating GaAs substrate. FIG. 4 is a comparison diagram of carrier concentration distributions after annealing in a conventional cap annealing method and in a case using an annealing method apparatus according to the present invention.

In the annealing apparatus shown in Fig. 1, ■ is a vacuum chamber, 2 is an exhaust system, and the vacuum chamber 1 is
It has the ability to maintain a vacuum level of 1 to 1 x 10-6 Torr.

A molecular beam source 3 is attached to the wall of the vacuum chamber 1. This molecular beam source 3 is connected to a substrate 6 to be annealed.
The vacuum chamber 1 is filled with a material that is particularly easy to extract, solid arsenic in this embodiment, and can be heated to generate an appropriate arsenic molecular beam within the vacuum chamber 1. Inside the vacuum chamber 1, an infrared lamp 4 for heating the substrate 6 after ion implantation and a susceptor 5 for holding the substrate 6 are provided. Reference numeral 7 denotes a preliminary chamber for loading and unloading the substrate 6, and it is possible to obtain a degree of vacuum of IX10-''~lXl0-')-μ, and this preliminary chamber 7 and the vacuum chamber 1 have a gate It can be blocked by pulp 8.

Next, an annealing method using the above apparatus will be explained. After ion implantation was performed on a commercially available Andog semi-insulating GaAs substrate at a pressure of 100 Kev and a dose of 5 x 10'212, the ion-implanted GaAs
The S substrate was annealed using the above-mentioned annealing apparatus. First, the ion-implanted GaAs substrate 6 was placed in the preliminary chamber 7 of the annealing apparatus, and the preliminary chamber 7 was evacuated to a vacuum level of 1X10-'').Then, the gate pulp 8 was opened, and the ion-implanted GaAs substrate 6 was evacuated to a vacuum level of 1X10-''). The arsenic molecular beam source 3 was heated to 350 to 450°C, and the ion-implanted substrate 6 was heated to 900°C for several seconds using the infrared lamp 4 to perform annealing/L'.This substrate heating In the method, it took only a few seconds to raise the substrate temperature from room temperature to 900°C, and about 1 minute to lower the substrate temperature from 900°C to room temperature.The gate pulp 8 was opened again. The annealed ion-implanted substrate was taken out, and the carrier concentration distribution of the ion-implanted layer was measured by a voltage-capacitance method using an ordinary Schottky junction.The results are shown in FIG.

In the figure, the dotted line a shows the distribution of Si+ ion implanted atoms from the GaAs substrate surface based on the LSII theory, and the dashed line shows the distribution of Si+ ion-implanted atoms from the GaAs substrate surface based on the LSII theory, and the dashed line shows the distribution of the Si+ ion-implanted atoms from the surface of the GaAs substrate.
It shows the carrier concentration distribution after AYP due to electric furnace annealing for 15 minutes, and the solid line C is the result of the carrier concentration distribution after annealing according to the present invention.The ion implantation conditions are the same for both samples, υ, and only the annealing conditions. are different.

As is clear from the comparison of curves S and c in Figure 2, the example of the present invention is better! It is close to the distribution according to DLSS theory a, and the concentration distribution in this embodiment C is steeper than that in the conventional method in the tee μ part.
The electrical activation rate of i-impurity atoms is high.

In this example, an example of annealing under an arsenic molecular beam using a GaAs ion-implanted substrate was explained.
Similar effects can be expected by using a phosphorus molecular beam source for GaP or IwP ion-implanted substrates, and by using arsenic and phosphorus molecular beam sources for InAsP or GaA sP.

<Effects of the Invention> By using the Annie-μ method of the ion implantation layer according to the present invention, a much steeper impurity concentration distribution and a higher electrical activation rate can be obtained. The mutual conductance of the GaAsFET used as the active layer can be improved, and the characteristics of the GaAsFET and GaAsFETIC can be easily controlled.

Further, since the annealing method according to the present invention does not use a highly poisonous gas such as As H3 (arsine), it is advantageous in ensuring work safety.

[Brief explanation of drawings]

Fig. 1 is a conceptual diagram of the ion-implanted layer annealing apparatus used in the present invention, and Fig. 2 shows the carrier concentration distribution obtained in an embodiment of the annealing apparatus according to the present invention and the carrier concentration distribution obtained by the conventional annealing method. FIG. 3 is a diagram showing a comparison of carrier concentration distributions. 1: Vacuum chamber 3: Molecular beam source 4: Red lj lamp 5: Susceptor 6: Substrate agent Patent attorney Yoshihiko Fukushi (and 2 others) ) tm) Be η Reward Reward A Shin AP Part 2! i

Claims (1)

[Claims] 1. A vacuum chamber coupled to a vacuum evacuation system, a heat source installed in the vacuum chamber for irradiating the substrate to be annealed with heat rays, and at least one of the substrate constituent elements in the vacuum chamber. What is claimed is: 1. An annealing apparatus for a semiconductor substrate, comprising: a molecular beam source that generates one molecular beam; and annealing an ion-implanted layer of a semiconductor substrate in a molecular beam atmosphere.