JPS6261125A - Data processor - Google Patents

Abstract

PURPOSE:To speed up saving and restoring operations and to use effectively a main storage area by controlling the effective size of stored address information in an instruction executing process and storing the size information in a control information area prepared for the saving and restoring processing. CONSTITUTION:When a machine word instruction defining operation including the saving and restoring operation of address information to/from a main storage is transferred to an instruction decoding means ID 4 by a data transfer means BTC 1, the recorded result is sent to a sequence control means MSEQ 7 and an execution control means 6. The instruction is executed in accordance with fixed procedure to drive a general register 100 or an exclusive register 101 and a computing element 102 in a data processor. When information stored in the general register and the exclusive register is addresses and is to be saved in the main storage 16, the effective length is discriminated and the information indicating the effective length is stored in a control information storing area of the main storage which is prepared for the saving/restoring operation together with the control information. Consequently, useless operation for receding unnecessary address information to the main storage 16 can be omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device that decodes and executes machine language instructions, and in particular stores address information such as program counters, frame pointers, and argument pointers in main memory. This relates to a control mechanism for saving and restoring operations (for example, subroutine calls).

2. Description of the Related Art A subroutine call and argument transmission mechanism in a conventional data processing device is described in "Programming and Architecture" (Henry M., Levy et al., translated by Katsuhiko Shirai, CQ Publishing).

Figure 2 shows the data structure of the arguments in this conventional subroutine call and argument transmission mechanism, and Figure 3 shows the data structure called a call frame, which manages subroutine link information used by the data processing device when calling the subroutine. This shows that.

In FIG. 2, 601 is an element indicating the number of arguments, and 502 is an argument list, in which the value itself or the value of a pointer indicating the value is stored.

FIG. 3 shows a call frame opened on the stack to transmit control, and 601 is an address indicating an error handling routine, which is used when an exceptional error occurs. 602 is the state of the main routine, such as the result of arithmetic operations, information about the type and number of internal registers saved in 60θ, which will be described later, and information indicating the relationship between this call frame and the argument list that is the data structure of the arguments; When saving a register to the stack (described later in 606), information regarding the skip operation of up to three Pitono stack pointers is included in order to match the data size of the stack memory device and the register size.

Next, 603 is the saved argument pointer (pointer indicating the first value of the argument list), 604H-+=-
The saved frame pointer (pointer λ 605 indicating the start of the call frame opened on the stack) is a saved program counter and stores the return address to the main program.Next, 606 is saved when the subroutine is executed. A group of registers.A subroutine call is executed by opening this call frame on the stack, and various control information (program runtime environment) is saved, the frame pointer is newly updated, and information related to the subroutine chain is saved. It is of paramount importance that the mechanism for always pointing to a data structure or call frame be automated, and this concept is now widely adopted in almost all data processing equipment.

In order to understand what happens to the stack during a subroutine call when there is a difference between a subroutine call and an argument in a conventional data processing device configured as described above, consider the program example shown in Figure 4. . This program is for calling subroutine 5ORTi.

Figure 5 shows the state of the stack resulting from the execution of the call instruction from the $10 PUSHAL instruction in Figure 4. In Figure 6, 01 indicates the data structure of the argument list, and the number of arguments received by the call instruction. is stored at the beginning. Further, 702 is a call frame opened by a call instruction, and in this case register 3 (R3) and register 2 (
R2) has been saved. Next, the program counter (PC), frame pointer (FP), and argument pointer (AP) are automatically stored, and finally, the management information of this call frame is stored.

By completely fixing the point-to-frame pointer for a call frame, it is possible to always find the position of the call frame in the stack even if the called program uses the stack. However, in the above control method, the data type and data size of each of the save information and link information stored in the call frame are generally treated as the natural data size of the data processing device.
Furthermore, in order to increase speed, call frames and argument lists have been arranged on the boundary of the word length of the data processing device, which has completely eliminated the problem of lower stack memory usage efficiency. A
With the introduction of P), there is a problem that the call frame size increases because the save size of various pointers that are automatically saved is fixed even in the conventional example described above. .

In view of the above, the present invention manages the effective size of address pointers, efficiently stores various address pointers that are saved when opening a call frame, and improves the effective length of a pointer in order to improve stack utilization efficiency. The purpose is to provide a complete data processing device having a management mechanism.

Means for Solving the Problems The present invention provides data transfer means for fetching machine language instructions, instruction decoding means for decoding the transferred machine language, and sequence operations defined for each machine language instruction according to the decoding results. , an execution control means that controls the entire data processing device together with the sequence management means based on the instruction decoding results, and an arithmetic unit, general-purpose registers, and dedicated registers that operate as a whole for this control, and is the main body of execution. when managing the effective length of the register holding address information and saving the contents of the register to main memory;
The data processing apparatus is characterized in that information indicating the effective length is simultaneously stored in a main storage area prepared for managing the evacuation and restoration processing along with other information.

According to the above-described configuration, when a machine language instruction in which an operation including an operation of saving or restoring address information to the main memory is defined is transferred to the instruction decoding means by the data transfer means, the instruction decoding means , sends the decoding result to the sequence management means and execution control means. The sequence management means and execution control means execute instructions according to a predetermined procedure and operate general-purpose registers or special-purpose registers and arithmetic units of the data processing device. The information stored in the general-purpose registers and dedicated registers at this time is an address, and when saving this to main memory, the information for determining and displaying the effective length is stored in the main memory prepared for the saving and restoring process. By storing it in the control information storage area of the memory together with other control status information, it is possible to eliminate the waste of saving unnecessary address information to the main memory, speed up the saving and restoration process, and improve the efficiency of use of the main memory. can.

Embodiment FIG. 1 shows a block diagram of a data processing apparatus in an embodiment of the present invention.

In Figure 1, 1 is a data transfer control unit (BTC) that controls data transfer with the main memory, 2 is an instruction cache (IC) that holds machine language instructions to which data has been transferred, and 3 is a converter for converting logical addresses into physical addresses. Conversion buffer 7 (DAT
), 4 is a machine language instruction decoding unit (ID) that decodes the fetched machine language instructions, and 6 is an execution unit (
EU), an execution control unit (MC) that controls the execution unit 6 of
M:%7 is a sequence management unit (MSEQ) that manages the sequence of this execution control unit 6. 8 is a logical address bus, 9 is a physical address bus, 10 is a first data bus, 11 is a second data bus, 12 is a decoding i-report bus, 13
is a sequence information bus, 14 is a control signal,
15 is a Fi external memory bus, and 16 is a main memory.

Further, FIG. 6 is a detailed diagram of the line section 6 shown in FIG. It is a detailed diagram of the instruction decoding unit 4, and 200 is an instruction register;
201 is a decoder for decoding instructions. Also, 202 is
It is a command bus.

Further, FIG. 8 shows an address format indicating the effective size of address information, and in this embodiment, the maximum length is expressed by 32 pits.

When the address is in the range from 0 to 216-1, that is, when bits 16 to 31 are 0, it is assumed to be effective size information Pt-o. Further, if bit 31 is not all 0 from bit 16, it is set as 6p21.

Therefore, when P = o, the effective length of address information is 2 bytes)k,
When P=1, it means the effective length of address information is 4 bytes.

The operation of the data processing apparatus according to the embodiment of the present invention configured as described above will be explained below. The decoding execution processing process will be explained.

FIG. 9 shows a general data structure of a stack frame opened on the stack when a subroutine call instruction according to the present invention is executed), and this is generally called a call frame.

The subroutine call instruction is transferred from the main memory 16 to the external bus 16.
The instruction is then transferred to the instruction decoder 4 by the action of the transfer controller 1. This instruction fetch is transmitted to the transfer control unit 1 and the instruction cache 2 via the logical address bus 8 and the conversion buffer 3, which are output from a program counter defined in a dedicated register 101 in the execution unit 5. If the target instruction is in the instruction cache 2, instruction transfer control by the transfer control unit 1 is inhibited.

The instruction decoding unit 4 decodes the fetched instruction and sends necessary decoding information to the sequence management unit and execution control unit 6. In order to open the call frame shown in FIG. 9 in the stack for the execution control unit 6 by executing the call instruction, the sequence management unit 7 first stores the general-purpose register 100 in the call frame (corresponding to 300 in FIG. 9). .) command is sent. Next, the program counter (P
C), the frame pointer (FP), and the argument pointer (AP) are sequentially stored after determining the valid address range shown in Figure 8 (Figure 9, 3).
Corresponds to 01.302.303. ) command, and finally a command to store in the frame management information (304 in Figure 9) information for displaying the full effective length of address pointers when restoring the contents of this stuff frame (400 in Figure 9). do.

The frame management information 304 in FIG. 9 corresponds to the stored address pointer, and in the case of FIG. □, Pl, P2,
If the value of is equal to the size ν0, a value indicating whether it is 2 bytes or 4 bytes is stored as frame management information.

A new address value is then set for the saved address pointer by executing the call instruction.

Therefore, restoration processing can be executed.

As described above, according to the present invention, when saving and restoring a register used as an address pointer to the main memory in a data processing device, what is the effective size of address information? The instruction execution control unit manages the information and stores it together with other information in a control information area specially prepared for the save and restore processing, thereby speeding up the save and restore operations. In addition, it is possible to improve the stack usage efficiency.

In addition, in the embodiment, the effective size of the address is in two formats, 2 bytes and 4 bytes, as shown in FIG.
It goes without saying that it may be more finely set as 1 byte, 2 bytes, or 4 bytes, or may be a set of 4 bytes or 8 bytes.According to the present invention, it can be used in a data processing device. When saving and restoring various address pointers such as program counters, argument pointers, and frame pointers, the effective size of the stored address information is managed during all instruction execution processes, and the size information is used for saving and restoring processing. By storing the information in the prepared control information area, it is possible to speed up the saving and restoring operations and to make effective use of the main storage area, which has a great practical effect.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a data processing device according to an embodiment of the present invention, Fig. 2 is a structural diagram of an argument list, Fig. 3 is a data structure diagram of a call frame, and Fig. 4 is a program showing the entire operation of a call instruction. An explanatory diagram of an example, FIG. 6 is an explanatory diagram of the argument list and call frame formed on the stack, FIG. 6 is a detailed diagram of the execution unit 6 of FIG. 1, and FIG. 7 is a detailed diagram of the instruction decoding unit 4 of FIG. 1. FIG. 8 is an explanatory diagram of the address effective size format, and FIG. 9 is an explanatory diagram of a call frame formed on a stack by execution of a call instruction in an embodiment of the present invention. 1...Data transfer control unit, 2...Instruction cache, 3...Address exchange buffer, 4
...Instruction decoding section, 6...Execution section, 6.
-... Execution control section, 7... Sequence w science section, s... Logical address bus, 9...
Physical address bus, 1Q...First bus, 11
...Second bus, 12...Medium decoding information bus,
13...Sequence information bus, 14...Mountain control signal, 16...External memory bus, 1
6... Main memory. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4 LISTSIZE: LON62θ - Array Buiz BLKL 2θ □ Distribution 1 Thickness H H INK < Pro 7 Ram Cordon lO Me: F'USHAL LISTSIZE
-Rooster Line 1
ACrELIST - Sequence address): yshFigure 5Figure 7Figure 0, Ward 8ゝFigure 9

Claims (1)

[Claims] A data transfer means for sequentially fetching machine language instructions stored in main memory, an instruction decoding means for decoding the transferred machine language instructions, and a defined execution sequence for each machine language instruction based on this decoding information. a management means, an execution control means that controls the state of the entire data processing device in accordance with this execution sequence, a general-purpose register means that operates under control from the execution control means, a dedicated register and arithmetic means, and the above-mentioned general-purpose register means. Information that manages the effective portion of other address pointers, including program counters defined for registers or dedicated register means, and displays the effective size of the address information when saving the counters and pointers to main memory. and control means for simultaneously storing the counter and pointer together with other management information in another main storage area that manages the evacuation and restoration operation defined in relation to the main storage area that is the target of the evacuation operation. Characteristic data processing device.