JPS6258717A - Receiving circuit for optical binary signal - Google Patents

Abstract

PURPOSE:To reduce the change of a pulse width and a jitter and to increase the degree of operating allowance even when the mark ratio of a signal is not 0.5 by performing a limiter amplification after reducing fewer the rising/ falling time of the signal. CONSTITUTION:When the mark ratio of the signal is smaller than 0.5, the rising/ falling time of the output waveform [figure (a)] of a photoelectric conversion circuit 1 is set as some fixed value. The output signal, the rising/falling time of which is made smaller by a high speed operating circuit 2 as shown in figure (b), is AC-coupled with a limiter amplifier circuit 3. The circuit 3, amplifying an input signal and limiting an amplitude, outputs a signal (c) to a filter 4. The filter 4 eliminates a high frequency component generated by the circuit 2 and performs a band limitation to minimize a code error rate and outputs a signal (d) to an identification circuit 5. In the previous state, the DC operating point of the signal (b) is set below 50% of an amplitude level, however, since the rising/falling time of the signal is so small, the fluctuation of the pulse width in the output waveform from the circuit 3 can be made small.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a receiving circuit that converts an optical signal amplitude-modulated with a binary code into an electrical logic level. The present invention relates to a signal receiving circuit.

(Prior Art) FIG. 8 is a block diagram showing a conventional example of an optical receiving circuit in this building. As shown in FIG. 8, an inebriation conversion circuit 11, a linear amplification circuit 12 to which all the output signals of the 1-electrical conversion circuit 11 are input, and a filter 13 to which all the output signals of the linear amplification circuit 12 are input, It is composed of a limiter amplifier circuit 14 that is AC coupled to the filter 13, and an identification circuit 15 that is DC coupled to the output of the limiter amplifier circuit 14.

The original binary signal is supplied to the opto-electrical conversion circuit 11, where it is converted into an electrical signal and amplified. The signal-to-noise ratio of the receiving circuit is approximately determined by the noise figure of the opto-electric conversion circuit 11.

The output signal of the original 4-ki converter circuit 11 is transmitted to the linear amplifier circuit 12.
The signal is amplified until it reaches a normal amplitude without changing the waveform.

The output signal of the linear amplifier circuit 12 is band-limited by the filter 13 and converted into a waveform that can be easily distinguished.

Generally, the output waveform of the filter 13 is converted into a full cosine roll with a narrow bandwidth and low code amount interference.
-The filter 13 is selected so as to approximate the waveform of the off function.

The output signal of the filter 13 is AC-coupled and input to the limiter amplifier circuit 14, where it is amplified to a general, logic level or 7n level.
The output is clamped to an amplitude close to . The AC coupling between the legs is used to absorb the difference in the DC operating point of each stage.

(Problem to be Solved by the Invention) However, in the above-mentioned optical receiving circuit, the mark rate of the received signal is 0.
．． When the value is 5, it is effective, but when it is not 0.5, the change in pulse width and jitter at the output of the limiter amplifier circuit 14 become large, resulting in a disadvantage that the operating margin becomes small. This will be explained with reference to all the figures.

FIG. 9 is a diagram showing the case where the mark rate of the signal is 0.5, and FIG. Since it is at the 50% point of the sensing width, there is no change in the pulse width of the output waveform of the 'J mitter amplifier circuit 14 shown in FIG. 9(b). However, as shown in FIG. 10, if the mark ratio is not 0.5, as shown in FIG.
Therefore, as shown in FIG. 10(b), the pulse width of the output waveform of the limiter amplifier circuit 14 changes from the normal pulse width.

When the mark rate fluctuates, the output pulse width also fluctuates correspondingly, resulting in increased jitter. Since the band is limited by the filter 13 before the limiter amplifier circuit 14, the waveform is greatly rounded and the jitter is also large.

In this way, the conventional optical receiving circuit has a signal mark rate of 0.
If it is not 5, there is a problem that the change in pulse width and jitter are large and the operating margin is small.

An object of the present invention is to solve the above-mentioned drawbacks, and to provide an original binary signal that can reduce changes in pulse width and jitter even when the mark ratio of the signal is not 0.5, and can provide a large operating margin. The purpose is to provide circuits.

(Means for Solving the Problems) In order to achieve the above object, an optical binary signal receiving circuit according to the present invention converts an optical signal whose amplitude is modulated with a binary code into an electrical logic level. In the receiving circuit,
a photoelectric conversion circuit that converts the optical signal into an electrical signal; a high-speed circuit that reduces the rise time and fall time of the output signal of the photoelectric conversion circuit; and an AC coupling with the high-speed circuit. a limiter amplifier circuit that amplifies the output signal of the speed-up circuit and limits the output amplitude; and a seven-line filter that is DC-coupled to the output of the limiter amplifier circuit and limits the frequency range of the output signal of the limiter amplifier circuit. and an identification circuit which is DC-coupled to the output of the filter and samples the output signal of the filter using a total clock signal and outputs a logic level signal.

(Embodiment) Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an optical binary signal receiving circuit according to the present invention.

The output of the opto-electric conversion circuit 1 is input to a speed-up circuit 2, and the output of the speed-up circuit 2 is AC-coupled to a limiter amplifier circuit 3.

The output of the limiter amplifier circuit 3 is DC coupled to the filter 4.
l The output of the filter 4 is DC coupled to the identification circuit 5.

The original binary signal is input to the opto-electrical conversion circuit 1, where it is converted into an electrical signal and amplified. The output signal of the opto-electrical conversion circuit 1 is reduced in rise/fall time by the high-speed circuit 2 and is AC-coupled with the limiter amplifier circuit 3.

The limiter amplification circuit 3 amplifies the entire input signal, converts it to the logic level or a level close to the logic level, and outputs the signal.

The filter 4 removes high frequency components generated by the speed-up circuit 2, and performs band limiting to minimize the bit error rate. The identification circuit 5 samples the output signal of the filter 4 at an optimal lock timing and outputs all the signals at logic level.

FIG. 2 shows operating waveforms of various parts of one embodiment of the present invention shown in FIG. 1. Consider the case where the mark rate of the signal is smaller than 0.5. The second screen (a) is the output waveform of the i\1L conversion circuit 1, and due to the key range restriction of the optical transmitter or the opto-electrical conversion circuit 1, the rise/fall of the waveform is a finite value for 9 hours. Become. Figure 2(b) shows the limiter circuit 3.
This is an input waveform whose rise/fall time has been reduced by the speed-up circuit 2. The DC operating point is 50% below the signal amplitude level, as shown by the broken line in Figure 2(b), but because the signal rise/fall time is small, the DC operating point is as shown in Figure 2(C). In this way, changes in the pulse width of the output waveform of the limiter amplifier circuit 3 can be reduced.

Now, for the sake of simplicity, assume that the rise/fall of the waveform is a straight line, its slope is kdV/at, and the change in the DC operating point from the 50% point of the amplitude level is ΔV, then the change in the output pulse width Δt is and is inversely proportional to the rise/fall time.

The smaller the rise/fall time is, the smaller the change in pulse width due to change in mark rate can be made.

Generally rising/falling 11. Decreasing i k increases the total high frequency components, which increases noise and ringing.

The whisker-like pulses in FIG. 2(C) show an example of this effect, and the filter 4 in the next stage can completely eliminate the bad shape of the high frequency component.

211N(d) is a waveform which shows the entire output waveform of the filter 4, removes a high frequency portion, and performs a restriction to minimize the code error rate. The cross mark in FIG. 2(d) is the identification circuit 5.
An example of a sampling point is shown in FIG.

21st. i+el indicates the output of the identification circuit 5, that is, the output waveform of logic levels classified by both amplitude and time.

Since there is DC coupling between the limiter amplifier circuit 3 and the filter 4 and between the filter 4 and the identification circuit 5, even if the mark rate changes, the DC operating point will not be affected, so no new changes in the pulse width will occur. .

FIG. 3 is a detailed diagram of the main parts of the photoelectric conversion circuit 1. The anode of the photoelectric conversion element 51 is connected to the bias power supply vBK, the input of the inverting amplifier 53 is connected to the cathode of the photoelectric conversion element 51, and a resistor 52 is inserted between the input and output of the inverting amplifier 53.

Output terminal 54 is connected to the output of inverting amplifier 53. The photoelectric conversion element 51 is an element that converts an input optical signal into a total current, and uses a PIN photodiode or an avalanche photodiode (API). It is a circuit that converts n-wavelength into voltage using an inverting amplifier 53 and a negative feedback resistor 52, and also has a function of amplifying a signal with low noise.

FIG. 4 is a detailed diagram of the main parts of the high-speed circuit 2.

The input terminal 61 is the base terminal of the transistor 65 and the resistor 62.
C. Between the power supply VC and the base of the transistor 65, the resistor 63
is between the base of transistor 65 and ground, resistor 64 is between power supply VC and the collector of transistor 65, resistor 66 is between the emitter of transistor 65 and ground, and capacitor 6
7 is connected in parallel to the resistor 66, and the output terminal 68 is connected to the transistor 6.
5 collectors, respectively. This is an example of a so-called emitter peaking circuit.

The resistor 62 and the resistor 63 are bias resistors for the transistor 65, and the gain is determined by the resistor 64, the resistor 66, and the capacitor 6.
It is determined approximately by the ratio of the parallel impedances of 7. In order to increase the gain at high frequencies, the emitter side impedance is lowered by a capacitor 67. By increasing the gain at high frequencies, rise/fall times can be made faster.

By changing all of the resistors 64, 66, and capacitors 67, the frequency characteristics of the gain can be changed, and the rise/fall times can be changed.

As examples of the speed-up circuit 2, in addition to the above-mentioned circuit, various other circuits including a differential circuit can be considered.

FIG. 5 is a detailed diagram of the main parts of the limiter amplifier circuit 3.

A capacitor 79 is connected between the input terminal 70 and the base of the transistor 74, a resistor 71 is connected between the power supply VC and the base of the transistor 74, a resistor 72 is connected between the base of the transistor 74 and ground, and a resistor 73 is connected between the source VO and the base of the transistor 74. A resistor 7.5 is connected between the collector and the power supply VC and the transistor 7.
6, a constant NR source 77 connects transistors 74 and 7
The emitter of transistor 6 and the base of transistor 76 are connected to the power supply VR.
In addition, output terminal 78 is connected to the collector of transistor 76.
are connected to each other.

A power supply Vk% is a power supply for determining a threshold voltage, a capacitor 79 is an AC coupling capacitor, and a resistor 71 and a resistor 72 are bias resistors for the transistor 74.

When the input signal is small, the voltage difference between the input signal voltage and the power supply VR is amplified, but when the input signal is large, the amplitude of the output is constant, which is the value between the current value of the power supply 77 and the resistor 75. A signal of nl-leg swing 1 is output. Bias voltages and other settings are all set so as not to saturate transistors 74 and 76 when the output is clamped.

If the required gain cannot be obtained with only one stage of the limiter amplifier circuit 3 shown in FIG. 5, a plurality of stages may be connected in series.

FIG. 6 is a detailed diagram of the main parts of the filter circuit 4.

One end of the coil 93 is connected to the input terminal 91 and one end of the capacitor 92, the other end of the capacitor 92 is grounded, the other end of the coil 93 is connected to the output terminal 95 and one end of the capacitor 94, and the other end of the capacitor 94 is grounded. The end is grounded.

This is a commonly used pie-shaped low-pass filter. In general, the band is often set to about 70% of the transmission frequency in order to minimize the code error rate, and the input/output impedance is determined by the connected circuit.

FIG. 7 is a detailed diagram of the main parts of the identification circuit 5.

The signal input terminal 101 is the data input of the flip-flop 103, and the clock input terminal 102 is the data input of the flip-flop 1.
The output terminal 104 is connected to the clock input of 03, and the output terminal 104 is connected to the output of the flip-flop 103, respectively. The flip-flop 103 samples the signal supplied to the data input at the timing when the bit error rate is minimized by the clock signal input to the total clock input, and outputs a signal at a logic level.

(Effects of the Invention) As described above in detail, according to the present invention, the signal mark ratio is not 0.5 because limiter amplification is performed after reducing the rise/fall time of the signal. However, the change in pulse width and jitter can be reduced, and therefore the operating margin can be increased.

Furthermore, even if the mark ratio is 0.5, if the limiter amplifier circuit is a circuit with an input offset voltage, the DC operating point will change. It has the effect of reducing changes in

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the original binary signal receiving circuit according to the present invention, FIG. 2 is a time chart for explaining the operation of the first circuit, and FIGS. The main parts of the circuit shown in the figure are shown. Figure 3 is a circuit diagram of a photoelectric conversion circuit, Figure 4 is a circuit diagram of a high-speed circuit, and Figure 5 is a circuit diagram of a limiter. The circuit diagram of the amplifier circuit, the sixth factor shows the circuit diagram of the filter, and FIG. 7 shows the circuit diagram of the identification circuit. The eighth factor is a block diagram showing a conventional receiving circuit, and the ninth factor and FIG. 10 are time charts for explaining the operation of the conventional receiving circuit. 1.11...TT conversion circuit 2...High speed circuit 3.14...Limiter amplifier circuit 4, engineering 3...Filter 5,15...Identification circuit 1
2... Linear amplifier circuit 51... Photoelectric conversion element 5
3... Inverting amplifier 52, 62, 63, 64.66.71, 72, 73.7
5...Resistor 67.79.92.94...Capacitor 65.74.76...Transistor 77...Urushibara 93...Coil 103.
...Free lag frog 61.70, 91, 101.102...Input terminal 54
．． 68.78,95,104... Output terminal patent applicant Nihon Kameki Co., Ltd. Agent Patent attorney Inoro 4O1 Figure 2 (e) Figure 3, 52 Figure 4 O6 Figure C Age 5 figure Off figure C Age 9 1.1 Age 10 figure

Claims (1)

[Claims] An optical binary signal receiving circuit that converts an optical signal amplitude-modulated with a binary code into an electrical logic level includes a photoelectric conversion circuit that converts the optical signal into an electrical signal, and an output signal of the photoelectric conversion circuit. a speed-up circuit that reduces rise time and fall time; a limiter amplifier circuit that is AC-coupled to the output of the speed-up circuit, amplifies the output signal of the speed-up circuit, and limits the output amplitude; and the limiter a filter that is DC-coupled to the output of the amplifier circuit and limits the band of the output signal of the limiter amplifier circuit; and a filter that is DC-coupled to the output of the filter, samples the output signal of the filter using a clock signal, and outputs a logic level signal. 1. A receiving circuit for an optical binary signal, characterized in that the receiving circuit comprises a discriminating circuit that