JPS6250964A - Video memory - Google Patents

Abstract

PURPOSE:To delay the feed or the frame of a video signal for prescribed time and to have a bit mask function at a video memory by providing a memory cell array, a transferring buffer and the buffer for an input and for an output. CONSTITUTION:A video siganl sampled and quantized by an (n) number of memory cell arrays 1a-1n, in which the memory capacity per sheet is about one field or one frame capacity, is delayed for about one field or one frame period. The outputs of the arrays 1a-1n are added to an (n) number of output buffers 4a-4n through transfer buffers 2a-2n in which the capacity per piece is an (m) bit. The digital signal of an (n) bit from input terminals 8a-9n are added to selecting devices 7a-7n, the outputs from data output terminals 9a-9n are selected by the control signal, added to demultiplexers 5a-5n and the outputs are added through input buffers 3a-3n to the buffers 2a-2n. The outputs of the buffers 4a-4n are outputted through multiplexers 6a-6n to the terminals 9a-9n and added to the selecting devices 7a-7n.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a video memory capable of delaying a video signal for a predetermined period of time and having a bit mask function.

[Background of the invention]

When field or frame memory is applied to video signal processing, the following characteristics are generally required of the memory.

1) Real-time field and frame delay is possible.

2) Has a bit mask function.

3) The total cost including support circuits is low.

Conventionally, as an example of field memory for video signals, see Nikkei Electronics, February 11, 1985, P, 25.
2-234, ``Field Memory Using Careful Dynamic RAM,'' some use multiple general-purpose dynamic RAMs. This is because dynamic RAM has the lowest bit A cost.

However, when a conventional dynamic RAM is used as a memory for video signals, some special features are required in order to satisfy the above-mentioned required characteristics (1).

Furthermore, in order to satisfy 2), the peripheral circuitry becomes complicated. As a result, there is room for improvement as the total cost cannot be expected to decrease much.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a video memory capable of delaying the field or frame of a video signal and having a bit mask function.

[Summary of the invention]

A memory cell array with a memory capacity of approximately 1 field or 1 frame per memory cell, an m-bit input buffer and an output buffer that can input and output data in series, and m-bit data between the input/output buffer and the memory cell array. By providing a means for simultaneously transferring video signal data, it is possible to input/output video signal data at high speed, allowing for field or frame delay. Enables a bit mask function that allows data from the output buffer to be selected using control signals.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIG. 1 and will be described.

In FIG. 1, 1α to 1rL are memory cell arrays, each having a memory capacity of about 1 field or 1 frame. 2a to 2 are transfer buffers each having a capacity of m bits. 3α to 5 are input buffers each having a capacity of m bits. 4α to 4n are output buffers each having a capacity of m bits. 5α to 5rL are demultiplexers having a function of converting serial data into m parallel data. 6α to 6n are multiplexers having a function of converting m parallel data into serial data. 7α to 77L are selectors each having a function of selecting one set of data from 2Ai[i in response to a control signal from a control terminal 1o. 8α to 8 are data input terminals, and 9α to 9n are data output terminals. Here, various pulse timing control circuits and address generation circuits are omitted. Next, the operation will be described, and for convenience of explanation, m-bit partial voltage will be explained. The data sampled at the sampling frequency f and converted is input to the selector 7α from the input terminal 8α. At this time, the other input part of the selector 7a includes the memory cell array 1α, the transfer buffer 2α, and the output buffer 4.
The one-frame delayed data output from the multiplexer 6α is inputted via a. This one frame delayed data is simultaneously output from the output terminal 9a. now,
It is assumed that the selector 7a selects the data from the input terminal 8a based on the control signal (for example, low level) K from the control terminal 1o. In the demultiplexer 5a, the system clock fC of the memory is equal to the sampling frequency f14C.
At L, consecutive m bits of data are latched. m bits of data are latched by the demultiplexer 5a [
1itjK of the period of time, that is, the time of rlL/fcL
, the subsequent m-bit data delayed by one frame is sent from the memory cell array 1α via the transfer buffer 2α to the output buffer JaK&, and the m-bit data in the power buffer 3α is transferred via the transfer buffer 2cL to a predetermined area of the memory cell array 1α. will be forwarded to. The order of transfer to the memory cell array 1α may be such that the data of the input buffer 3α is transferred first, and then the data of the memory cell array 1α is transferred to the output buffer 4α. The data latched by the demultiplexer 5a is transferred to the input buffer 3α until the next data is input. At the same time, the data in the output buffer 44 is sent to the multiplexer 6aIICtux. After this, the above-mentioned operation is repeated.◇With these five operations, it is possible to delay the video signal by one frame. Next, after inputting the data for one frame, the control signal 1j from the control terminal 1o is set to high level so that the selector 7α selects the output data from the multiplexer 6α. image data can be frozen.

By applying a pulse having a pulse width equal to the clock frequency fCL from the control terminal 10 as a control signal, the contents of the frame memory can be rewritten bit by bit.

Capacity doors for input/output packers, etc. are determined based on the following conditions. rn/fcL from the minimum data transfer time between memory cell array 1α, input buffer 3α, and output buffer 4α
Set it to 5 so that it becomes large.

However, in the case of dynamic memory, it is necessary to take into account the time for the flexible S operation.

FIG. 7 shows another embodiment. In this case, the transfer buffer 2 is removed from FIG. 1, and the input buffer 7a 3 and the output buffer 4 are connected to the memory cell array 1, respectively. In this case, although the number of connection lines with the memory cell array 1 increases, the transfer buffer 2 can be eliminated. As an example of a specific value, if the capacity is taken as the capacity for one line of an image, the design of the timing circuit and address circuit can be simplified. As a specific example, the sampling frequency is set to 4 of the TV double signal color subcarrier frequency fsc.
If you select double the number, the NTSC signal will be 910 bits. FIG. 2 shows an example of a video memory system in this case.

Reference numeral 11 designates an a-row address counter, 12 a column address counter, 13 a clock input terminal, 14 a horizontal synchronization pulse input terminal, and 15 a vertical synchronization input terminal. Other blocks with the same symbols as in FIG. 1 have the same functions. In this case, the configuration of one memory cell array 1cL is such that one row is equal to the capacity of the crowd buffers 5α and 6α, and the number of rows is set to approximately the number of frame lines. The aforementioned NTSC
For signals, it is a 910 x 525 configuration. With this configuration, the row address of the memory cell array 1α can be specified by counting horizontal synchronization pulses from the time when the vertical synchronization signal is input from the input terminal 15. Further, by counting clock pulses from the point in time when the horizontal synchronizing signal is input from the input terminal 14, the columns of the demultiplexer 5α and the multiplexer 6α can be specified. At this time, if no signal is input from the horizontal synchronizing signal input terminal 14, the signal output from the column address counter 11 once per horizontal scanning period is counted. As mentioned above, the timing circuit,
The address circuit is simplified.

FIG. 3 shows another embodiment of the present invention. This example is the second
This is the example shown in the figure with one output buffer added. 1
6α to 16rL are output buffers with a capacity equal to 3 input buffers. This is the same as the output buffer 4. 17α to 1 full are multiplexers. In this example, the time of data transfer from the output buffer 16 to the multiplexer 17 and the time of data transfer from the output buffer 4 to the multiplexer 6 are shifted. Due to this operation, the data output from the output terminal 9 is out of phase (time) with respect to the data input from the input terminal 8.

For example, if the capacity of the input and output buffers 5 and 4.16 is for one line, the amount of phase (time) shift is:
It can be set arbitrarily within the range of about 1 horizontal scanning time.

FIG. 4 shows another embodiment. The purpose of this example is to read out the read clock of the multiplexer 17 in the example of FIG. 3 asynchronously with the multiplexer 5 of the input section. 1
Reference numeral 8 designates a column address counter, 19 designates an a-ac input terminal, and 20 designates a horizontal synchronization pulse input terminal.

FIG. 5 shows another embodiment. This example is the same as the example shown in FIG. 1 except that KB delay circuits are provided between the input terminal 8 and the selector 70. The purpose of this delay circuit is to compensate for the delay time when bit masking is performed using the control signal from the control terminal 10 and when the control signal is obtained from the data input from the input terminal 8. Therefore, delay circuit 2
1 can be realized by a shift register of about 1 to 5 bits.

FIG. 6 shows another embodiment. 22A and 22B constitute a 2-bit control signal input terminal, and 23 is a 2-bit decoder. The outputs of the 2304 decoders are each connected to the same selector 7 (A converter 1).This allows rewriting only the data in any memory cell array among the memory cell arrays 1α to 1L. In this example, 2 bits are used, but any number of bits may be used depending on the number of memory cell arrays.

Another embodiment will be described with reference to FIG. 24 is a video memory of the present invention, for example as shown in FIG. 25 is a terminal for supplying data to the data input terminal 8 of the video memory 24, and 26 is a terminal for supplying a control signal to the control signal input terminal 10 of the video memory 240. terminal 2
A dropout compensation function can be realized by inputting a reproduction signal from a T'TR or a video disk player to terminal 5 and supplying the output of a dropout detection circuit to terminal 26VC. In other words, if the configuration is such that when a dog attack occurs, a high level 4f signal can be supplied to the terminal 26, the data from the input terminal 8 will be ignored, the data in the memory cell array will be held, and the TV screen will be displayed. The picture above is compensated with the signal from one frame before. It can also be used for noise reduction when playing a VTR at variable speeds.

In this case, a noise bar detection circuit is provided in place of the dropout production circuit, and its output is supplied to the terminal 26. The operating principle is the same, so the explanation will be omitted.

Further, in the VTR, by inputting a still image playback control signal to the terminal 26 shown in FIG. 8, the still playback of the VTR can be stably performed. As a result, the frame image in the memory cell array is output, so there is no wear on the head or tape as in the conventional case.

Further, for example, it is possible to easily synthesize an image by superimposing a portrait on a landscape or a plain background. That is, this can be done by storing a landscape picture in the video memo IJk, inputting the data of the portrait to the terminal 25, and supplying the output of the portrait orientation detection circuit to the terminal 26.

〔Effect of the invention〕

The present invention can realize a video memory that can delay a video signal for a predetermined period and has a bit-by-bit masking function.

[Brief explanation of drawings]

1 to 7 are block diagrams of embodiments of the present invention, and FIG.
The figure is a block diagram of a circuit utilizing the present invention. 1...Memory cell array 2...Transfer buffer 3...
・Input buffer 4...Output buffer 5...Demultiplexer 6...Multiplexer 7...Selector
8... Data input terminal 9... Data output terminal 10... Control signal input terminal Patent attorney Katsuo Koyo No. l Σ # 2 Figure $ 3 Figure 4 Figure 5 Figure 6 Figure r q Figure (,.

Claims (1)

[Claims] A video memory that delays or holds a sampled and quantized video signal by about 1 field or about 1 frame period, each of which has a memory capacity of about 1 field or 1 frame (n is an integer) ), n input m-bit buffers (m is an integer), n output m-bit buffers, and between the n memory cell arrays and their corresponding input and output m-bit buffers, A transfer means for transferring data of bits in parallel, a first input means for inputting data of m bits in series to each of the n m-bit buffers, and outputting data of m bits in series. and a second input means for selecting one of the two sets of data by a control signal and inputting the m bits of data to the means for serially inputting the m bits of data. is data from an output means that serially outputs the m-bit data.