JPS6234170B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to gain control (AGC) voltage generation circuits, and particularly to AGC voltage generation circuits in FM radio receivers.

In radio receivers, the received signal level is not constant, and sometimes strong signals are received. Therefore, it is necessary to design a radio receiver so that it can receive good reception even when receiving such a strong signal level. That is, if the received signal level is too strong, the high frequency circuit that is the input circuit of the radio receiver becomes saturated, causing interference due to intermodulation, generation of beats and spurious signals, or deterioration of distortion rate.

As a countermeasure for this, the input dynamic range of the high frequency circuit is increased to increase the allowable input level, and a local distance switch is installed to change the gain of the intermediate frequency amplification stage according to the received signal level. In other words, when the input reception level is strong, the gain of the intermediate frequency amplification stage can be lowered to make it appear as if an attenuator has been inserted into the input, or by installing an AGC circuit, it can be automatically activated when the reception signal level becomes strong. The gain of the high frequency circuit is lowered to prevent the high frequency circuit that is the input circuit of the receiver from becoming saturated. In particular, since electronically tuned radio receivers generally use variable capacitance diodes as tuning capacitors, there are severe restrictions on the maximum amplitude of the operating signal of the tuning circuit, making an AGC circuit indispensable.

The level of the received signal at which the AGC circuit operates should be set to an optimal value depending on the input circuit configuration of the receiver and the environment and purpose in which the receiver is used. ,or
It is desirable that the AGC voltage itself be set to an optimal value depending on the input circuit configuration of the receiver.

Figure 1 shows the basic configuration of an FM radio receiver. The signal received by the antenna 1 is selected, amplified, and frequency-converted to an intermediate frequency signal by the front end 2, which includes a tuning stage, a high-frequency amplification stage, and a mixer stage that generates a 10.7MHz signal using the signal from the local oscillator. ing. This signal is applied to the FM-IF stage 4 via the filter 3, where it is amplified and limited in amplitude, and is then subjected to FM detection and the detected output is taken out. This detected output is amplified by a low frequency amplification stage 5 and transmitted to a speaker 6. or,
AGC voltage is applied from FM-IF stage 4 to front end 2.

With this configuration, it is possible to receive the radio signal from antenna 1 and extract the audio output.
Moreover, so that front end 2 does not become saturated
It can also have AGC function. It is clear from this configuration that the FM-IF stage 4 is the front end 2
A circuit that performs FM detection by amplifying and limiting the amplitude of the signal converted to an intermediate frequency, and a signal level detection circuit that detects the strength of the signal applied to the FM-IF stage 4 to extract the AGC voltage. It is equipped with
In addition, circuits for additional functions, such as
It is common to include an AFC circuit, a muting circuit, a circuit for driving a reception tuning display device, and the like. For this reason, the circuit of the FM-IF stage 4 becomes complicated, so in order to make the receiver smaller and lower in cost, the FM-IF stage 4 is often integrated into an integrated circuit.

However, when FM-IF stage 4 is integrated into an integrated circuit to reduce the size and cost of FM radio receivers,
Since the AGC circuit is also included as an attached function in the integrated circuit used, the input signal level at which the AGC circuit operates, and furthermore the output AGC voltage, are uniquely determined for each integrated circuit. For this reason,
There was a drawback that there were restrictions on adjusting the received signal level at which the AGC circuit operates and setting the optimal AGC voltage.

The purpose of the present invention is to develop a circuit configuration suitable for integrated circuits.
The purpose is to provide a gain control voltage generation circuit for AGC circuits, especially FM receivers, and another purpose is to
The input signal level at which the circuit operates and the output
An object of the present invention is to provide a gain control voltage generation circuit in which the AGC voltage can be arbitrarily set externally.
This eliminates the design constraints mentioned above.

Furthermore, the present invention provides a gain control voltage generation circuit that can eliminate the need for an increase in the number of terminals even when integrated circuits are implemented.

According to the present invention, there is provided an amplitude limiting amplifying section in which a plurality of amplitude limiting amplifying stages are connected in cascade, a signal level detecting section that detects the signal level of an input signal using the outputs of the amplitude limiting amplifying stages as input, and a signal level detecting section for detecting the signal level of an input signal. A load resistor inserted in series with the output of the detection section, a comparison circuit that compares the voltage generated at the load resistance with a reference voltage, and a circuit section that changes the AGC voltage with the output of the comparison circuit. Featured AGC
Get the voltage generation circuit.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a block diagram of an integrated circuit FM-IF stage equipped with an AGC circuit according to an embodiment of the present invention. That is, the FM-IF stage 4 is an integrated circuit as shown by the dotted line 22, the input terminal 7 is connected to the input of the amplitude limiter 8, the output of the amplitude limiter 8 is connected to the FM detector 9, The output of the FM detector 9 is connected to a detection output terminal 10. The signal level detector 11 is coupled to the amplitude limiting amplifier 8 , and the output of the signal level detector 11 is connected to a signal level detection output terminal 12 . The signal level detection output terminal 12 is connected to a reference potential (ground potential) through a parallel circuit of a variable resistor 13 and a capacitor 14.
and one input of the comparator 15. The other input of comparator 15 is connected to reference voltage source 16. The output of the comparator 15 is connected to the base of the transistor 17 and is connected to the reference potential via a co-resistor 18. The emitter of the transistor 17 is connected to a reference potential, the collector thereof is connected to an AGC voltage output terminal 19, and the AGC output terminal 19 is connected to a voltage source 21 via a resistor 20.

To explain the operation of the FM-IF stage 4, the signal applied to the input terminal 7 is amplified and amplitude limited by the amplitude limiting amplifier 8. In an integrated circuit FM-IF stage, the amplitude limiting amplifier 8 is generally composed of differential amplifiers connected in cascade in multiple stages.
Alternatively, it is constructed by connecting a differential amplifier and an emitter follower circuit that also performs signal coupling and level shifting in multiple stages, and a DC feedback circuit for stably setting the operating point.

The signal amplified and amplitude limited by the amplitude limiting amplifier 8 is subjected to FM detection by the FM detector 9, and its detection output is taken out from the detection output terminal 10. In an integrated circuit FM-IF stage, the FM detector 9 uses a detection method suitable for integrated circuit implementation, and typical examples include a quadrature detection circuit or a differential peak detection circuit. .

The output of each of the multi-stage connected circuits as described above constituting the amplitude limiting amplifier 8 is
As is known from No. 2561 and Japanese Patent Publication No. 54-28681, a plurality of signal level detection stages for detecting the signal level using these outputs as input are connected, and a circuit means is provided for adding the detected outputs. It is input to the signal level detector 11. The output of the signal level detector 11 is the signal level detection output terminal 1.
taken out from 2. A resistor 13 is connected to the signal level detection terminal 12, and this resistor 13 serves as a load for the signal level detector 11. Therefore, by arbitrarily setting this resistor 13, the voltage at the terminal 12, that is, the voltage at one input end of the comparator 15 can be changed. Note that the capacitor 14 is for removing high frequency components contained in the signal level detection output.

The comparator 15 compares the voltage of the signal level detection output terminal 12, which is determined by the resistance value of the resistor 13, with the reference voltage of the reference voltage source 16, and detects which voltage is higher. When the input signal level is small and the voltage at the signal level detection output terminal 12 is lower than the voltage at the reference voltage source 16, no current is drawn to the output of the comparator 15. Therefore, the transistor 17 is cut off, and the voltage at the AGC voltage output terminal 19 is changed to the voltage source 21.
is equal to the voltage of Therefore, high AGC
A voltage is supplied to the front end 2 and the front end 2 is operating at high gain. The resistor 18 is designed to prevent the current from flowing into the transistor 17 by drawing leakage current between the collector and base of the transistor 17, and to prevent the voltage at the AGC voltage output terminal 19 from dropping. It is something.

When the input signal level is large and the voltage at the signal level detection output terminal 12 is higher than the voltage at the reference voltage source 16, current is extracted from the output of the comparator 16, so the transistor 17 is saturated and current flows. The voltage at the AGC voltage output terminal 19 is approximately at ground potential. Therefore, the AGC voltage supplied to the front end 2 becomes low and the front end 2
will operate at low gain. Furthermore, comparator 15
can be constructed, for example, by a differential comparator.

As explained above, in the AGC circuit of this embodiment, the AGC voltage during weak input can be set by the voltage of the voltage source 21, and can be easily set according to the circuit configuration and circuit constants of the front end 2 used. Become. Further, the AGC operation input signal level at which the AGC voltage is inverted from a high voltage to a low voltage is an input signal level at which the voltage of the signal level detection output terminal 12 is equal to the voltage of the reference voltage source 16, and this input signal level is the signal level. It can be set by the resistance value of the resistor 13 which is the load resistance of the detector 11. That is, the AGC operation input signal level can be set by the value of the resistor 13, and the signal level can be freely adjusted according to the gain distribution of the receiver and the front end used.

FIG. 3 is an example of a circuit configuration showing FIG. 2 more specifically. In FIG. 3, the same reference numerals as in FIG. 2 indicate the same components, and further, components not directly related to the present invention are excluded. The level detector 11 includes a first level detection stage 23, a second level detection stage 24, a third level detection stage 25, and these level detection stages 23, 24 and 2.
A diode 26 whose cathode side receives each output of
It is composed of a PNP transistor 27. As mentioned above, the first, second and third level detection stages 23, 24 and 25 are respectively coupled to the output of the differential amplifier of each stage of the multi-stage connected differential amplifier constituting the limiter amplifier 8. has been done.

The first, second, and third level detection stages 23, 24, and 25 detect the signal amplitudes of the output signals of the differential amplifiers of each stage constituting the coupled limiter amplifier 8, respectively, and The current based on the signal amplitude is detected from the outputs of the first, second and third level detection stages 23, 24 and 25. The currents extracted by detecting these signal amplitudes are commonly led to the diode 26 and are added together. The anode side terminal of the diode 26 is connected to a power supply terminal 28.

When the input signal level is small, only the level detection stage 25 coupled to the output of the differential amplifier at the final stage constituting the limiter amplifier 8 operates, and as the input signal level increases, the differential amplifier at the previous stage is activated. Level detection stages 24 and 23, which are coupled to the output of the filter, also become operative. In addition, since the signal amplitude is limited from the differential amplifier in the succeeding stage, the level detection stage 2 is connected to the output of the differential amplifier in the succeeding stage.
It gradually becomes saturated from 5 onwards. In this way, the range of input signal levels in which the signal level detector 11 operates is expanded by detecting the signal amplitude with a plurality of level detection stages.

The emitter of the transistor 27 is connected to the power supply terminal 28 and also to the anode side of the diode 26, and the base is connected to the diode 26 and the first and second
and third level detection stages 23, 24 and 25
The collector is connected to the signal level detection output terminal 12. Also, since the diode 26 and the transistor 27 are matched, the transistor 27 has the diode 2.
A current proportional to the current flowing through 6 flows. The current flowing through the diode 26 is the first, second and third diode.
A current equal to the sum of the output currents of the level detection stages 23, 24 and 25 flows through the transistor 27, and a current proportional to this current flows through the transistor 27. Therefore,
The voltage of the signal level detection output terminal 12 is
A voltage is generated because the current flowing into the resistor 13 flows through the resistor 13. That is, depending on the value of the resistor 13, the voltage at the signal level detection output terminal 12 can be used for setting the sensitivity to the input signal level. FIG. 4 shows a characteristic diagram of the voltage V ₁₂ of the signal level detection output terminal 12 and the input signal level V _IN when the resistance value of the resistor 13 is changed. Curve B shows the characteristics when a resistor 13 of 47KΩ is used, curve A shows the characteristic when the value of the resistor 13 is increased to, for example, 100KΩ compared to curve B, and curve C shows the characteristic when the value of the resistor 13 is set to, for example, 20KΩ. This shows the case where it is made smaller.

By changing the resistance value of the resistor 13 in this manner, the voltage level of the signal level detection output terminal 12 can be changed to desired characteristics.

The voltage of the signal level detection output terminal 12 is the voltage of the comparator 1.
6, the comparator 16 has two transistors 2 connected to a common emitter.
9, 30 and their common emitter connection point and power supply terminal 2
The two transistors 29 and 30 are of the PNP type, which has a different conductivity type from the transistor 17. The base of the transistor 29 is the comparator 16
The base of the transistor 30 serves as one input terminal of the comparison circuit 16 and is connected to the signal level detection output terminal 12, and the base of the transistor 30 serves as the other input terminal of the comparison circuit 16 and is connected to the signal level detection output terminal 12.
Connected to 6. The collector of the transistor 29 is connected to the ground potential point, and the collector of the transistor 30 is connected to the base of the transistor 17 as the output of the comparator 16, and is also connected to the ground potential point via the resistor 18.

Since the comparator 16 has the above configuration, when the input signal level is small and the voltage V ₁₂ of the signal level detection output terminal 12 is lower than the voltage V REF of the reference voltage source 16, the voltage of the transistor 29 is lower than the voltage V _REF of the reference voltage source 16. Since transistor 30 is in a cut-off state, transistor 17 is also in a cut-off state. Therefore, the voltage at the AGC voltage output terminal 19 becomes the voltage at the voltage source 21. On the other hand, when the input signal level is large and the voltage V ₁₂ of the signal level detection output terminal 12 becomes higher than the voltage V _REF of the reference voltage 16, the transistor 29 becomes cut off and the transistor 30 becomes conductive. Therefore, the current of the current source 31 passes through the transistor 30 to the transistor 1.
7 is supplied to the base of transistor 17, and transistor 17 becomes saturated. Therefore, the voltage at the AGC voltage output terminal 19 is approximately at ground potential.

Here, as described above, the AGC voltage is inverted from a high voltage to a low voltage when the voltage V ₁₂ of the signal level detection output terminal 12 and the voltage V _REF of the reference voltage source 16 become equal. Yes, but the fourth
As shown in the figure, the signal level detection output terminal 1 shows curves A, B and C when the value of the resistor 13 is changed.
The input signal level V _IN at which the voltage V ₁₂ of the reference power supply 16 is equal to the voltage V _REF of the reference power supply 16 is represented by points D, E, and F, respectively, which means that the AGC voltage is changing the input signal level. become.

As explained above, integrated circuit FM
In the IF stage 4, the AGC voltage can be arbitrarily set externally using the voltage source 21, and the AGC voltage
The operational input signal level can be arbitrarily set externally using the resistor 13. Therefore, there is an advantage that the degree of freedom in designing the FM receiver is increased, and the circuit constants and configuration of the front end 2 can be freely adjusted.

Furthermore, the signal level detection output terminal 12 is used as a terminal to connect a signal strength meter to recognize the level of the input signal, and even in the conventional FM-IF stage 4, a terminal for AGC voltage output is provided. Therefore, there is no need for extra terminals for external adjustment, and the same number of terminals as before can be used.

FIG. 5 shows another embodiment of the invention. In the example shown in FIG. 3, the current source 31 is
The base and emitter of transistor 7 are connected to the base and emitter of transistor 7, respectively, the collector is replaced by a transistor 32 connected to the emitter common connection point of transistors 29 and 30, and a tuning indicating device 33 is connected in series with resistor 13. The only difference is that the others are the same.

In the example shown in FIG. 5, the operation of the comparator 15 to saturate the transistor ₁₇ by detecting that the voltage V 12 at the signal level detection output terminal 12 is higher than the voltage V _REF of the reference voltage source 16 is based on the input signal level. Therefore, instead of using the current source 31, the input signal level is detected and the current flowing through the diode 26 is detected by the transistor 32 in the same way as the transistor 27. By supplying this to the base of the transistor 17, the number of elements constituting the integrated circuit can be reduced and costs can be reduced. Furthermore, resistance 1
A tuning indicating device 33 that displays the input signal level of the FM receiver is driven by the current flowing through the input signal level detected. In this case, there is an advantage that the current driving the tuning instruction device 33 does not change even if the value of the resistor 13 is adjusted to set the AGC operation input level. That is, when connecting the tuning instruction device 33, there is no need to provide the AGC operation input level setting terminal and the tuning instruction device connection terminal independently, and the same terminal can be shared, which has the advantage of not leading to an increase in the number of terminals. At this time, the voltage obtained at the terminal 12 is determined approximately by the resistor 13 since the input impedance of the tuning instruction device is very small.

As described above, according to the present invention, the AGC voltage and the input signal level of AGC operation can be freely adjusted according to the external circuit configuration, and even when integrated circuits are implemented, it is not necessary to add terminals for this adjustment. Suitable for integrated circuits with the same number of terminals as before.
Can provide AGC circuit.

It should be noted that the present invention is not limited to the above-mentioned embodiment, and can be similarly applied to, for example, an FM-IF stage that is not integrated. Further, the resistor 13 may be a variable resistor or a fixed resistor whose resistance value is adjusted in advance. Further, although the emitter of the transistor 17 is used as a ground point, it may also be a bias point with an arbitrary voltage. Furthermore, the number of stages of the amplitude limiting amplifier 8 and the signal level detector 11 may be increased or decreased as necessary.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the basic configuration of an FM radio receiver, and Fig. 2 shows an embodiment of the present invention.
A block configuration diagram of an integrated circuit FM-IF stage equipped with an AGC circuit. Figure 3 is a circuit diagram that more specifically shows the block configuration of Figure 2.
Input signal level V _{IN vs.} signal level detection output terminal 12 when the resistance value of resistor 13 shown in the figure is varied
_FIG. 5 is a circuit diagram showing another embodiment of the present invention. 1...Antenna, 2...Front end, 3...Filter, 4...FM-IF stage, 5...Low frequency amplification stage, 6
...Speaker, 7...Input terminal, 8...Amplitude limiting amplifier, 9...FM detector, 10...Detection output terminal, 11
...Signal level detector, 12...Signal level detection output terminal, 13, 18, 20...Resistor, 14...Capacitor, 15...Comparator, 16...Reference voltage source, 17, 2
7, 29, 30, 32...transistor, 19...
AGC voltage output terminal, 21... Voltage source, 22... Integrated circuit, 23, 24, 25... Level detection stage, 26...
Diode, 28...Power terminal, 31...Current source, 3
3... Tuning instruction device.

Claims (1)

[Claims] 1. An amplitude-limiting amplification section that has a plurality of cascade-connected amplification stages and amplifies an input signal and outputs an amplitude-limited output signal; A signal level detection section that is a signal level detection section that synthesizes detected outputs and outputs the synthesized output by forming a current, and a resistor that is connected to this signal level detection section and converts the synthesized output outputted in the current format into a voltage. 1. A gain control voltage generation circuit comprising: a comparison circuit for comparing the converted voltage with a reference voltage; and an output of the comparison circuit is taken out as a gain control voltage.