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JPS6233474A - Thin film transistor - Google Patents

Thin film transistor

Info

Publication number
JPS6233474A
JPS6233474A JP17228485A JP17228485A JPS6233474A JP S6233474 A JPS6233474 A JP S6233474A JP 17228485 A JP17228485 A JP 17228485A JP 17228485 A JP17228485 A JP 17228485A JP S6233474 A JPS6233474 A JP S6233474A
Authority
JP
Japan
Prior art keywords
thin film
film
multilayer
film transistor
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17228485A
Other languages
Japanese (ja)
Inventor
Koichi Haga
浩一 羽賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Original Assignee
Ricoh Research Institute of General Electronics Co Ltd
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Research Institute of General Electronics Co Ltd, Ricoh Co Ltd filed Critical Ricoh Research Institute of General Electronics Co Ltd
Priority to JP17228485A priority Critical patent/JPS6233474A/en
Publication of JPS6233474A publication Critical patent/JPS6233474A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain the thin film transistor of high speed and highly stable by lowering a trapping probability and enabling a high-speed response, and preventing the structure change by laminating the multiple thin film layers of different band gaps. CONSTITUTION:A high frequency power source 115 is closed and is modulated at 20W to cause a discharge in a high-frequency electrode 113. After depositing an a-Si:H film on a substrate 116 to 100Angstrom , the high-frequency power source 115 is turned off to shut valves 107 and 121. This operation is repeated in A room and B room alternately to deposit an a-SixN1-x:H film and an a-Si:H film alternately by 100Angstrom each. The a-SixN1-x:H film of 21 layers and the a-Si:H film of 20 layers are deposited to the whole thickness 4100Angstrom . After forming a multilayer thin film 2, an a-Si:H(B) layer doped with B by glow discharge decomposition is deposited to 1000Angstrom on the multilayer thin film. Subsequently, the a-Si:H(B) layer except the part for forming gate electrodes 6a and 6b is removed and lastly, aluminum is deposited by vacuum vapor deposition, followed by selective etching to form the gate electrodes 6a and 6b and to obtain a thin film transistor.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、薄膜トランジスタに関するものである。[Detailed description of the invention] (Industrial application field) The present invention relates to thin film transistors.

(従来の技術及びその問題点) 第5図(a) 、 (b) 、(c)は、従来一般に知
られた薄膜トランジスタ(TPT)を示したもので、(
a)は再結晶化シリコン、ポリシリコンを、(b)はア
モルファスシリコンを、また(c)はCdSeをそれぞ
れ主材料として構成されている。しかし、これらの薄膜
トランジスタには、それぞれ次のような問題点がある。
(Prior art and its problems) Figures 5 (a), (b), and (c) show thin film transistors (TPT) that are generally known in the past.
The main materials in a) are recrystallized silicon and polysilicon, in (b) amorphous silicon, and in (c) CdSe. However, each of these thin film transistors has the following problems.

(a)再結晶化シリコン、ポリシリコンTPTこの材料
で作製する場合は、まず、低温(400℃以下)での成
膜が難しい。そのため、単結晶シリコン又は石英のよう
な耐熱性の材料からなる高価な基板が必要となる。また
単結晶と同様な構造欠陥の少ないシリコン膜を作る必要
があるが、多数の薄膜トランジスタを同時に作製するた
めに広い面積に成膜しようとすると、電気特性に影響を
与えるようなひずみや欠陥が多く発生してしまう。従っ
て6インチウェハー程度のものしか作製できないのが現
状であり、TPT1個当りのコス1−が高い。
(a) Recrystallized silicon, polysilicon TPT When fabricating with this material, first, it is difficult to form a film at low temperatures (below 400° C.). This requires an expensive substrate made of a heat resistant material such as single crystal silicon or quartz. It is also necessary to create a silicon film with few structural defects similar to single-crystal silicon, but when trying to deposit a film over a large area in order to simultaneously manufacture many thin film transistors, there are many strains and defects that affect the electrical properties. It will happen. Therefore, at present, only 6-inch wafers can be manufactured, and the cost 1- per TPT is high.

(b)アモルファスシリコンTPT アモルファスシリコンは低温成膜、大面積の成膜が可能
で、太陽電池、センサ等に多く応用されている。しかし
薄膜トランジスタとした場合、アモルファスシリコンは
移動度が小さいため、第5図(b)のような構成では高
速応答が難しい。さらに、キャリアがソースからドレイ
ンに移動する際に拡散してしまい、トラップ確率が増加
し特性が経時変化する。また高電界が印加された際、電
極界面及び薄膜中で構造変化が起き、特性が変化してし
まう。
(b) Amorphous silicon TPT Amorphous silicon can be formed into a film at a low temperature and over a large area, and is widely used in solar cells, sensors, etc. However, when used as a thin film transistor, since amorphous silicon has low mobility, it is difficult to achieve high-speed response with the configuration shown in FIG. 5(b). Furthermore, when carriers move from the source to the drain, they are diffused, increasing the probability of trapping and changing the characteristics over time. Furthermore, when a high electric field is applied, structural changes occur at the electrode interface and in the thin film, resulting in changes in characteristics.

(c) CdSe T F T CdSeは低温成膜、大面積の成膜が可能であるが、製
法上CdとSeが分離し易く、さらに酸素と非常に反応
し易いため、プロセス制御が難しい。
(c) CdSe T F T Although CdSe can be formed into a film at a low temperature and over a large area, it is difficult to control the process because Cd and Se are easy to separate due to the manufacturing method, and furthermore, it is very easy to react with oxygen.

また、移動度が小さく、トラップが多いため高速応答、
安定性が問題とされている。
In addition, the mobility is small and there are many traps, so the response is fast.
Stability is an issue.

本発明は、上記従来技術の問題点を解消し、高速で、高
安定な薄膜トランジスタを提供するものである。
The present invention solves the problems of the prior art described above and provides a high-speed, highly stable thin film transistor.

(問題点を解決するための手段) 上記問題点を解決するために、基体上に、禁制帯幅の異
なる少なくとも2種類以上の薄膜を同種の薄膜が互いに
隣合わないようにして少なくとも3層以上の多層に積層
し、その多層薄膜の各層が接続されるようにソース電極
及びドレイン電極をそれぞれ設けるとともに、基体面に
対して略垂直な多層薄膜の断面に、多層薄膜中で最も狭
い禁制帯幅の薄膜と同程度の格子定数を有しかつその簿
膜の伝導型と異なる伝導型を有する薄膜層を介してグー
1−′rti極を設ける。
(Means for solving the problem) In order to solve the above problem, at least three or more layers of at least two types of thin films with different forbidden band widths are formed on the substrate so that the same types of thin films are not adjacent to each other. A source electrode and a drain electrode are provided so that each layer of the multilayer thin film is connected, and the narrowest forbidden band width in the multilayer thin film is formed in the cross section of the multilayer thin film approximately perpendicular to the substrate surface. A Goo 1-'rti electrode is provided through a thin film layer having a lattice constant comparable to that of the thin film and having a conductivity type different from that of the thin film.

(作 用) 禁制帯幅の異なる薄膜層を多層に積層することによりペ
テロ接合のポテンシャル井戸が形成され、その結果キャ
リアは禁制帯幅の狭い層の中を電界に引かれて伝導し、
隣接層方向への拡散がない。
(Function) A Peter junction potential well is formed by laminating multiple thin film layers with different forbidden band widths, and as a result, carriers are attracted by the electric field and conduct in the layer with a narrow forbidden band width.
There is no diffusion towards adjacent layers.

このとき、キャリアの寿命をτ、ドリフト移動度をμと
すると、μτ積が応答速度の重要な因子となるが、前記
作用はτを増加させることになり、高速応答が可能にな
る。さらに印加した高電界は各層に配分されて1層当り
にかかる電界が低下するので高電界による構造変化や結
晶化等は起こらない。
At this time, assuming that the carrier lifetime is τ and the drift mobility is μ, the μτ product becomes an important factor in the response speed, and the above action increases τ, making high-speed response possible. Furthermore, since the applied high electric field is distributed to each layer and the electric field applied to each layer is reduced, structural changes and crystallization due to the high electric field do not occur.

(実施例) 以下図面に基づいて実施例を詳細に説明する。(Example) Embodiments will be described in detail below based on the drawings.

第1図は、本発明の一実施例を示したもので、1は基板
、2は多層薄膜で、禁制帯幅の異なる少なくとも2種類
以上の薄膜を同種の薄膜が互いに隣合わないようにして
少なくとも3層以上の多層に積層する(本実施例ではa
層、b層、a層の2種類3層からなっている)。3及び
4は、それぞれ多層薄膜2の各層が接続されるように対
向して設けられたソース電極及びドレイン電極、5a、
5bは多層薄膜2中で最も狭い禁制帯幅の薄膜と同程度
の格子定数を有しかつその薄膜の伝導型と異なる伝導型
を有する薄膜層で、多層薄膜2の基板1に対して略垂直
な断面に接して設けられている。6a。
FIG. 1 shows an embodiment of the present invention, in which 1 is a substrate and 2 is a multilayer thin film, in which at least two types of thin films with different forbidden band widths are arranged so that the same types of thin films are not adjacent to each other. Laminated in multiple layers of at least three layers (in this example, a
It consists of three layers of two types: layer B, layer A, and layer A). 3 and 4 are a source electrode and a drain electrode, respectively, which are provided facing each other so that each layer of the multilayer thin film 2 is connected; 5a;
5b is a thin film layer having a lattice constant comparable to that of the thin film with the narrowest forbidden band width in the multilayer thin film 2 and having a conductivity type different from that of the thin film, and is approximately perpendicular to the substrate 1 of the multilayer thin film 2. It is provided in contact with a cross section. 6a.

6bは薄膜J’j15a、Sb上にそれぞれ設けられた
ゲート電極である。
6b is a gate electrode provided on the thin films J'j15a and Sb, respectively.

第2図は、本発明の他の実施例を示したもので。FIG. 2 shows another embodiment of the invention.

第1図と同一符号のものは同一のものを示している。第
1図のものと異なる点は、ゲート電極6a。
Components with the same reference numerals as in FIG. 1 indicate the same components. The difference from the one in FIG. 1 is the gate electrode 6a.

6bを形成した後、多層薄膜2に基板1まで達する穴を
穿ち、その穴にソース電極3及びドレイン電極4を形成
した点である。
6b, a hole reaching the substrate 1 was formed in the multilayer thin film 2, and a source electrode 3 and a drain electrode 4 were formed in the hole.

なお、上記2つの実施例で、多層薄膜2とソース電極3
との間、多層薄膜2とドレイン電極4との間にそれぞれ
オーミック性を得るための中間層を挿入してもよい。ま
た、薄膜トランジスタ形成後に、全体を覆うように、湿
気、酸化等を防止するためのパッシベーション膜を塗布
・形成してもよい。
In addition, in the above two embodiments, the multilayer thin film 2 and the source electrode 3
An intermediate layer may be inserted between the multilayer thin film 2 and the drain electrode 4 to obtain ohmic properties. Further, after forming the thin film transistor, a passivation film for preventing moisture, oxidation, etc. may be applied and formed to cover the entire structure.

基板1の材料としては、絶縁材料がよく、無機材料では
ガラス、セラミック、有機材料ではポリイミドなどが用
いられる。また導電性材料に絶縁処理を施したものでも
よい。
The substrate 1 is preferably made of an insulating material, such as inorganic materials such as glass and ceramics, and organic materials such as polyimide. Alternatively, a conductive material subjected to insulation treatment may be used.

多層薄膜2の、禁制帯幅の異なる薄膜としては、結晶で
もアモルファスでもよい。結晶の場合は格子定数が比較
的近似した材料である必要がある。
The thin films of the multilayer thin film 2 having different forbidden band widths may be crystalline or amorphous. In the case of crystals, the materials must have relatively similar lattice constants.

そのため組合せとして、Cd5−Cu2S、 Cd5−
CdTe。
Therefore, as a combination, Cd5-Cu2S, Cd5-
CdTe.

Cd5−InP、 CdTe−Cu2Te、 Cd5−
CuInS2. CdS −CuInSe2. Cd5
−CuInTe2. Cd5−CuGaSe2. Cu
、Te −CdTe、 ’Cd5e−ZnTa、 Cd
5−3iなどがよい。またアモルファスと結晶の組合せ
を用いることによって格子定数をある程度緩和できる。
Cd5-InP, CdTe-Cu2Te, Cd5-
CuInS2. CdS-CuInSe2. Cd5
-CuInTe2. Cd5-CuGaSe2. Cu
, Te-CdTe, 'Cd5e-ZnTa, Cd
5-3i etc. are good. Furthermore, by using a combination of amorphous and crystalline materials, the lattice constant can be relaxed to some extent.

アモルファス(記号としてa−を用いる)材料としては
a−5i : t((F) 。
As an amorphous (a- is used as the symbol) material, a-5i: t((F).

a−5e、 a−Ge : H(F)などがあげられ、
CdS −a−5i : H。
a-5e, a-Ge: H(F), etc.
CdS-a-5i: H.

CuIn5e−a−3e、 CuIn5e−a−3i 
: Hなどの組合せがよい。アモルファス材料どうしの
組合せとしてはa−3e−a−5i : H,a−5i
、C□−、: H−a−3i : II。
CuIn5e-a-3e, CuIn5e-a-3i
: Combinations such as H are good. The combination of amorphous materials is a-3e-a-5i: H, a-5i
, C□-,: H-a-3i: II.

a−3ilIN、II: II−a−3i : H,a
−5i、O,−1l: H−a−3i : Hなどがよ
い。
a-3ilIN, II: II-a-3i: H,a
-5i, O, -1l: H-a-3i: H etc. are preferable.

ソース電極3、ドレイン電極4としては、AC。The source electrode 3 and drain electrode 4 are AC.

Mo、 11. Ni、 Cr、 Au、 Agを用い
ることができる。
Mo, 11. Ni, Cr, Au, and Ag can be used.

多層薄膜とゲート電極との間の薄膜M5a、5bとして
は、例えば多層薄膜2中で最も狭い禁制帯幅の薄膜とし
てa−3i : Hを例にとれば、この薄膜自体はN−
型の伝導型を有しているため、BをドープしてP型のa
−5i : II(B)を用いることができる。このよ
うに、この部分の薄膜層は、多層薄膜中で最も狭い禁制
帯幅の薄膜自体の持っている伝導型にドーピングを施し
て異なる伝導型にして用いてもよい。
As the thin films M5a and 5b between the multilayer thin film and the gate electrode, for example, if we take a-3i:H as a thin film with the narrowest forbidden band width in the multilayer thin film 2, this thin film itself is N-.
Since it has a conductivity type of P type, it is doped with B to make P type a
-5i: II(B) can be used. In this manner, the thin film layer in this portion may be used to have a different conductivity type by doping the conductivity type of the thin film itself having the narrowest forbidden band width among the multilayer thin films.

ゲート電極6a、6bとしては、AI、 Mo、 IJ
、 Ni。
As the gate electrodes 6a and 6b, AI, Mo, IJ
, Ni.

Cr、 Au、 Agを用いることができる。Cr, Au, and Ag can be used.

禁制帯幅の異なる膜を多層に積層したバンドモデルを第
3図に示す。結晶−結晶、アモルファス−結晶、ア干ル
ファスーアモルファスの組合せはともに材料固有の伝導
型を持ち、それらの伝導型はP型、N型、i型に分ける
ことができ、伝導型の組合せとして、P型−N型、P型
−1型、N型−P型。
A band model in which films with different forbidden band widths are laminated in multiple layers is shown in FIG. The combinations of crystal-crystal, amorphous-crystal, and amorphous have their own conductivity types, and these conductivity types can be divided into P-type, N-type, and i-type. P type-N type, P type-1 type, N type-P type.

N型−1型、i型−1型などがあり、各バンドモデルを
第3図(a)〜(e)にそれぞれ示す。この組合せ以外
に、P型−P型、N型−N型があってもよい。Eg、、
□が禁制帯幅の広い層、Eg−zが禁制帯幅の狭い層、
EPはフェルミ−レベル、8層膜厚と5層膜厚は同じで
ある。
There are N-type-1 type, I-type-1 type, etc., and each band model is shown in FIGS. 3(a) to 3(e), respectively. In addition to this combination, P type-P type and N type-N type may be used. Eg...
□ is a layer with a wide forbidden band width, Eg-z is a layer with a narrow forbidden band width,
EP is at the Fermi level, and the 8-layer film thickness and the 5-layer film thickness are the same.

禁制帯幅の異なる膜1層当りの膜厚は100〜1000
0人とし、多層薄膜2の全体の膜厚は0.1〜10μm
、好ましくは0.3〜2μ閣とする。また多層薄膜とゲ
ート電極の間の薄膜層5a 、 5bの厚さは500人
〜1μmまでがよく、好ましくは1000〜5000人
がよい。各電極の膜厚は1000〜5000人が好まし
い。
Film thickness per layer with different forbidden band widths is 100 to 1000
The total thickness of the multilayer thin film 2 is 0.1 to 10 μm.
, preferably 0.3 to 2 μm. The thickness of the thin film layers 5a and 5b between the multilayer thin film and the gate electrode is preferably 500 to 1 μm, preferably 1000 to 5000 μm. The thickness of each electrode is preferably 1000 to 5000.

また、ソース、ドレイン間のチャネル長は1〜20μm
程度、好ましくは2〜10μmがよく、チャネル幅は5
〜500μm、好ましくは10〜200μmがよtl。
In addition, the channel length between the source and drain is 1 to 20 μm.
The channel width is preferably 2 to 10 μm, and the channel width is 5 μm.
~500 μm, preferably 10-200 μm.

次に、製造方法を含む具体例を示す。基板としてパイレ
ックスガラスを用い、禁制帯幅の異なる膜としてa−8
i : It−a−3i、lN、、、 : IIのアモ
ルファス半導体を用いた。a−3i : Hが禁制帯幅
の狭い材料であり、a−3i、N、x: Itが禁制帯
幅の広い材料である。a−3L : Hは格子定数が約
4人、禁制帯幅は1.7eVのN型半導体、a−5i、
Ni−、: )Iは格子定数が約4人、禁制帯幅が2.
3eVのN型半導体で、N型−N型の組合せである。a
−5j: Hg a−5ixNL+II : Hの膜厚
は両者とも100人とした。 a−3i : H及びa
−5L、N、−、: Hはグロー放電分解を用いたプラ
ズマCVD法により堆積した。その多層薄膜の形成方法
を第4図に従って説明する。
Next, a specific example including a manufacturing method will be shown. Pyrex glass was used as the substrate, and a-8 was used as the film with different forbidden band widths.
i: It-a-3i, IN, , : II amorphous semiconductors were used. a-3i: H is a material with a narrow forbidden band width, and a-3i, N, x: It is a material with a wide forbidden band width. a-3L: H is an N-type semiconductor with a lattice constant of about 4 and a forbidden band width of 1.7 eV, a-5i,
Ni-, : )I has a lattice constant of about 4 and a forbidden band width of 2.
It is a 3eV N-type semiconductor, and is a combination of N-type and N-type. a
-5j: Hga a-5ixNL+II: The film thickness of H was 100 in both cases. a-3i: H and a
-5L, N, -,:H was deposited by a plasma CVD method using glow discharge decomposition. A method for forming the multilayer thin film will be explained with reference to FIG.

第4図に示す装置はA室111とB室110の2室を備
えている。まず、バルブ118.121を開けてロータ
リポンプ122.124によってA室111. B室1
10を1O−2Torrの圧力にし、バルブ118.1
21を閉じ1次にバルブ125.119.120を開け
てロータリポンプ126及び拡散ポンプ123によって
A室、B室を1O−6Torrの圧力にする。その後、
バルブ119.120を閉じ、試料116をまずA室1
11の高周波電極112に平行に対向するようにセット
し、バルブ106.108を開け、5i11.のボンベ
100の元栓102及びNi13のボンベ101の元栓
103を開け、フローメータ104を調節してSiH4
の流量を20ccに保ち、またフローメータ105を調
節してNH,の流量を100ccに保ち、バルブ118
を調節してA室111内の圧力をI Torrに保ち、
高周波電源114を20Wに調節して高周波電極112
で放電を起こす。a−8ixNi−x : N膜が基板
116上に100人堆積後、高周波電源114を切り、
バルブ106゜108を閉じる。次に、モータ109を
回転させ、試料をB室110へ移動させ、高周波電極1
13に平行に対向させてセットする。バルブ107を開
けてフローメータ104を20ccに調節し、バルブ1
21を調節してB室110の圧力をI Torrに保ち
、高周波電源115を投入し201i!に調節して高周
波電極113で放電を起こす。a−5i : H膜が基
板116上に100人堆積後、高周波電源115を切り
、バルブ107.121を閉じる。以上の操作をA室と
B室交互に繰り返し、基板上にa−5IJx−x : 
H膜とa−3i : H膜とを100人ずつ交互に堆積
し、a−8xxN1 +Il : H膜を21層、 a
−5i : ll膜を20層、全体の膜厚として410
0人を堆積した。
The apparatus shown in FIG. 4 includes two chambers, an A chamber 111 and a B chamber 110. First, open the valves 118 and 121 and use the rotary pumps 122 and 124 to move the A chamber 111. Room B 1
10 to a pressure of 1 O-2 Torr and valve 118.1
21 is closed, then valves 125, 119, and 120 are opened, and chambers A and B are brought to a pressure of 10-6 Torr by the rotary pump 126 and the diffusion pump 123. after that,
Close the valves 119 and 120 and transfer the sample 116 to chamber A 1.
5i11. set so as to face parallel to the high frequency electrode 112 of 5i11. Open the main stopcock 102 of the cylinder 100 and the main stopcock 103 of the Ni13 cylinder 101, adjust the flow meter 104, and
The flow rate of NH is maintained at 20cc, and the flow rate of NH is maintained at 100cc by adjusting the flow meter 105.
to maintain the pressure in chamber A 111 at I Torr,
The high frequency power source 114 is adjusted to 20W and the high frequency electrode 112
causes a discharge. a-8ixNi-x: After 100 N films are deposited on the substrate 116, turn off the high frequency power supply 114,
Close valves 106 and 108. Next, the motor 109 is rotated, the sample is moved to the B chamber 110, and the high frequency electrode 1
13 in parallel and facing each other. Open valve 107, adjust flow meter 104 to 20cc, and open valve 1.
21 to maintain the pressure in chamber B 110 at I Torr, turn on the high frequency power supply 115, and 201i! The high frequency electrode 113 generates a discharge. a-5i: After 100 H films are deposited on the substrate 116, turn off the high frequency power supply 115 and close the valves 107 and 121. Repeat the above operations alternately in room A and room B, and place a-5IJx-x on the board:
The H film and the a-3i:H film were deposited alternately by 100 people each, and 21 layers of the a-8xxN1 +Il:H film were deposited.
-5i: 20 layers of ll film, total film thickness 410
0 people were deposited.

多層薄膜形成後、グロー放電分解法にてBをドーピング
したa−5i : H(B)層を多層薄膜上の全体に1
000人堆積し、次いでエツチングによりゲート電極形
成部以外のa−3i : It(B)層を除去し、最後
にiを真空蒸着により堆積し選択的にエツチングしてゲ
ート電極を形成し、第1図に示すような構成の薄膜トラ
ンジスタを得た。
After forming the multilayer thin film, a-5i: H (B) layer doped with B using glow discharge decomposition method is applied to the entire multilayer thin film.
000 layers are deposited, and then the a-3i:It(B) layer other than the gate electrode formation portion is removed by etching, and finally i is deposited by vacuum evaporation and selectively etched to form the gate electrode. A thin film transistor having the configuration shown in the figure was obtained.

上記薄膜トランジスタの特性を測定した結果、ゲート電
圧15v、ドレイン電圧15V印加して■。TI= I
 Xl0−’(A)、  I。PP = 2 X 10
−’ (A)で、工。、/I。pp = 10’と、薄
膜トランジスタとしては十分な特性が得られた。
As a result of measuring the characteristics of the above thin film transistor, the result was (2) when a gate voltage of 15V and a drain voltage of 15V were applied. TI=I
Xl0-'(A), I. PP = 2 x 10
-' (A), Eng. ,/I. pp = 10', which is sufficient for a thin film transistor.

(発明の効果) 以上説明したように、本発明によれば、禁制帯幅の異な
る薄膜層を多層に積層することにより、ペテロ接合のキ
ャリア閉、じ込め効果が生じ、その結果トラップ確率が
低下し、高速応答が可能になる。また、多層薄膜に印加
された高電界は各層に配分され、1層当りの電界が低下
するので構造変化が起きるのを防止することができ、高
速で、高安定な薄膜トランジスタを得ることができる。
(Effects of the Invention) As explained above, according to the present invention, by laminating multiple thin film layers with different forbidden band widths, a carrier confinement and confinement effect of the Peter junction occurs, and as a result, the trap probability decreases. This enables high-speed response. In addition, the high electric field applied to the multilayer thin film is distributed to each layer, and the electric field per layer is reduced, so structural changes can be prevented, and a high-speed, highly stable thin film transistor can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は1本発明の一実施例の薄膜トランジスタの構成
図、第2図は1本発明の他の実施例の薄膜トランジスタ
の構成図、第3図(a)〜(e)は、多層薄膜の各種伝
導型の組合せにおけるバンドモデルを示す図、第4図は
、実施例の試料作製に用いた薄膜堆積装置の構成図、第
5図(a)、 (b)、 (c)は、それぞれ従来の薄
膜トランジスタの構成図である。 1 ・・・基板、 2 ・・・多層薄膜、 3 ・・・
ソース電極、 4 ・・・ ドレイン電極、5a、5b
・・・薄膜層、6a 、 6b・・・ゲート電極。 特許出願人  株式会社  リ  コ  −リコ一応用
電子研究所株式会社 第 1 区 (a)        (b)         (c
)第2図 (a)         (b)         (
c)第3図 (a)             (b)(e) (山41゛。町 第5図 (a) ■UART Z (b) (c)
FIG. 1 is a block diagram of a thin film transistor according to an embodiment of the present invention, FIG. 2 is a block diagram of a thin film transistor according to another embodiment of the present invention, and FIGS. Diagrams showing band models for various conduction type combinations; Figure 4 is a configuration diagram of the thin film deposition apparatus used for sample preparation in the example; Figures 5(a), (b), and (c) are respectively conventional FIG. 2 is a configuration diagram of a thin film transistor of FIG. 1...Substrate, 2...Multilayer thin film, 3...
Source electrode, 4... Drain electrode, 5a, 5b
... Thin film layer, 6a, 6b... Gate electrode. Patent applicant Rico Co., Ltd. - Rico Applied Electronics Research Institute Co., Ltd. District 1 (a) (b) (c
) Figure 2 (a) (b) (
c) Figure 3 (a) (b) (e) (Mountain 41゛. Town Figure 5 (a) ■UART Z (b) (c)

Claims (3)

【特許請求の範囲】[Claims] (1)基体上に、禁制帯幅の異なる少なくとも2種類以
上の薄膜を同種の薄膜が互いに隣合わないようにして少
なくとも3層以上の多層に積層し、前記多層薄膜の各層
が接続されるようにソース電極及びドレイン電極をそれ
ぞれ設けるとともに、前記多層薄膜の前記基体に対して
略垂直な断面に、前記多層薄膜中で最も狭い禁制帯幅の
薄膜と同程度の格子定数を有しかつその薄膜の伝導型と
異なる伝導型を有する薄膜層を介してゲート電極を設け
てなることを特徴とする薄膜トランジスタ。
(1) At least two or more types of thin films with different forbidden band widths are laminated in a multilayer of at least three or more layers on a substrate so that thin films of the same type are not adjacent to each other, and each layer of the multilayer thin film is connected. a source electrode and a drain electrode, respectively, and a thin film having a lattice constant comparable to that of the thin film having the narrowest forbidden band width in the multilayer thin film in a cross section substantially perpendicular to the base of the multilayer thin film. A thin film transistor characterized in that a gate electrode is provided through a thin film layer having a conductivity type different from that of the thin film transistor.
(2)前記多層薄膜の少なくとも1種が、水素原子、重
水素原子、ハロゲン原子の少なくとも1種を含むアモル
ファスシリコンであることを特徴とする特許請求の範囲
第(1)項記載の薄膜トランジスタ。
(2) The thin film transistor according to claim (1), wherein at least one kind of the multilayer thin film is amorphous silicon containing at least one kind of hydrogen atoms, deuterium atoms, and halogen atoms.
(3)前記多層薄膜とソース電極間、多層薄膜とドレイ
ン電極間に、前記多層薄膜及び電極とオーミック特性を
示す中間層を設けたことを特徴とする特許請求の範囲第
(1)項記載の薄膜トランジスタ。
(3) An intermediate layer exhibiting ohmic characteristics with the multilayer thin film and the electrode is provided between the multilayer thin film and the source electrode and between the multilayer thin film and the drain electrode. Thin film transistor.
JP17228485A 1985-08-07 1985-08-07 Thin film transistor Pending JPS6233474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17228485A JPS6233474A (en) 1985-08-07 1985-08-07 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17228485A JPS6233474A (en) 1985-08-07 1985-08-07 Thin film transistor

Publications (1)

Publication Number Publication Date
JPS6233474A true JPS6233474A (en) 1987-02-13

Family

ID=15939071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17228485A Pending JPS6233474A (en) 1985-08-07 1985-08-07 Thin film transistor

Country Status (1)

Country Link
JP (1) JPS6233474A (en)

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