JPS6230668B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides that the transfer of error log information from an input/output dedicated processor to the main memory is different from a termination interrupt issued to the main processor upon completion of input/output data transfer. The present invention relates to an input/output control method that performs input/output control at the same timing.

Conventionally, in information processing systems, when an error occurs in the transferred data during data transfer between an input/output device and an input/output control device, a process has been adopted to recover the error. In reality, this is done by an input/output control device called a channel. Data transfer between the input/output control device and the input/output device is performed as follows.

In other words, when input/output transfer is required and an input/output command is sent by a program from the central processing unit to the input/output control unit, the transfer destination main storage address information, number of transferred words, and chain operation required for data transfer control. Control information related to the designation, etc. is set in the channel control information register, and thereafter, the input/output device is activated while updating the data transfer address information and the number of transferred words each time data of a certain number of words is transferred. It is something. On the other hand, the input/output device performs input/output processing such as printing on a line printer based on a transfer instruction, and the results are transferred to the input/output control device. If there is no more data to be transferred while input/output operations are being performed in this way, the series of transfer processes will end. It is designed to issue a termination interrupt to the device.

Assuming that an error occurs during data transfer between the input/output control device and the input/output device, recovery from the error may be possible depending on the type of error. Errors are generally classified into permanent and transient errors. For example, if the power supply to the input/output device is abnormal, the printing paper is not set, or a solid error occurs in the control registers, operator intervention is required, and automatic recovery is difficult without that intervention. Therefore, these errors are classified as equivalent to permanent failures. but,
Errors caused by bit information being reversed due to noise mixed in on the transfer line (parity errors, etc.) and track positioning errors in magnetic disk drives caused by subtle deviations in mechanical accuracy can be recovered by retrying. It is distinguished as a possible error (referred to as a transient failure). Therefore, when a transient failure is detected in the input/output controller, the input/output controller attempts to recover from the error by performing the input/output operation again. This process is generally called retry process, and it plays a very important role in reducing the failure rate of input/output operations and increasing the reliability of the entire system. On the other hand, if retry processing is performed separately, the type of error that caused the retry processing, the type of retry processing, the results, and the number of times the retry processing was executed are stored in an external mass storage device such as a magnetic disk device. Conventionally, it has been common practice to keep records. This means that the details of the error can be known from the saved and recorded data, and later the operation rate of the input/output device can be evaluated and the cause of the error can be investigated to prevent the occurrence of the error. This is because it greatly contributes to the maintainability and reliability of the system.

By the way, for the user program in the central processing unit, the success or failure of the input/output operation is the issue, and there are cases where the error can be recovered as a result of retry processing, and cases where the input/output operation is completed normally without any retry processing. The distinction between cases where it could have been done is not originally necessary and unnecessary. However, in the past, both error log information indicating the error cause and retry processing result for each retry process and error information regarding the success or failure of the final input/output operation were reported to the central processing unit as the above-mentioned end interrupt. This creates a problem in that the central processing unit must also process error log information. In other words, the termination interrupt program that executes termination processing for input/output requests issued by the user program not only processes error information that should be processed, but also processes error log information that is unnecessary for the user program. This is necessary, and the amount of processing increases needlessly.

This drawback will be explained in more detail with reference to FIGS. 1 to 7 as follows.

That is, FIG. 1 shows the system configuration of an example of a multiprocessor system according to the prior art. According to this, this system has data bus 4.
1, address bus 42 and interrupt lines 43, 4
A JOB processor 402 as a central processing unit and an IO processor 404 as an input/output control device are connected to a system bus 401 consisting of 4. It will be accommodated and connected. The JOB processor 402 executes various control programs 200 stored in the program area on the main storage device 400, and
The IO processor 404 takes in the data set in the inter-processor communication area 100, translates it into input/output operation execution commands and transfer data, and then controls input/output operations performed with the input/output device 109. ing. In this example, the input/output device 109 is accommodated in the IO processor 404 via the IO station 407 and the loop bus 406, but it is needless to say that the invention is not limited to this. Note that area 300 on main storage device 400 serves as a logout area for temporarily storing and recording retry error information from IO processor 404. Further, interrupt lines 43 and 44 are interrupt-only signal lines for interrupting each other between the JOB processor 402 and the IO processor 404.

Although the system configuration is as described above, the configurations of the JOB processor 402 and IO processor 404 will be explained in more detail with reference to FIGS. 2 and 3 as follows.

That is, FIG. 2 shows the internal configuration of the IO processor 404, and according to this, the IO processor 404 itself is activated by an interrupt signal from the JOB processor 402. An interrupt signal from the JOB processor 402 via the interrupt line 43 is activated as a set signal by placing the interrupt reception flip-flop 70 in the set state. The fact that the flip-flop 70 has been placed in the set state is reported to the arithmetic processing circuit 350 via the priority determination circuit 340, and the arithmetic processing circuit 35
0 is where the system bus control circuit 310 is activated. At the time when the IO processor 404 is activated, information necessary for the IO processor 404 to perform input/output operations has already been set in the area 100 by the JOB processor 402, so the system bus control circuit 3
10 is internal address bus 302, address bus 4
2 to the main memory control device 500 in order to read out the information. Main memory control device 500 reads data corresponding to the address from area 100 based on the address data, and the read data is stored in buffer 370 via data bus 41, internal data bus 301, and system bus control circuit 310. It's becoming like that. The system bus control circuit 3 indicates that the data has been stored in the buffer 370.
10 to the arithmetic processing circuit 350, which causes the arithmetic processing circuit 350 to
After decoding the input/output operation instruction information stored in the input/output control circuit 360, an input/output command is created that instructs the input/output operation in the input/output control circuit 360, and this input/output command instructs the input/output device 109 to output data. If so, further processing is performed to divide the output data transferred from the main storage device 400 together with the input/output operation instruction information. When the input/output command instructs the input/output device 109 to output data, the arithmetic processing circuit 350 outputs data to the input/output control circuit 360.
The output data is divided into units that can be transferred at once between the loop bus 406 and the loop bus 406. After that, the arithmetic processing circuit 350 sends an input/output command to the input/output control circuit 360 to control the input/output control circuit 3.
60 and the activated input/output control circuit 360
reads the output data from the buffer 370 and transfers the output data along with the input/output command to the loop bus 406 via the bus 390 in accordance with the input/output command.

The above is a case where the input/output command instructs the input/output device 109 to output data, but if the input/output command instructs the input/output device 109 to input data, the arithmetic processing circuit 350 uses the input/output command. Main storage device 4 where input data is to be stored
Address data on 00 is input/output control circuit 360
Send to. When an input/output command is transferred to the loop bus 406 for either output or input, a predetermined input/output device 109 is activated, and data input/output is transferred between the IO processor 404 and the input/output device 109. is carried out. Note that the data from the input/output device 109 is sent to the IO processor 40.
4, and the data transfer control at that time is exactly the same as when data is transferred from the main memory 400 to the IO processor 404, except that the data transfer direction is reversed. It is done.

Now, when the input/output operation in the input/output device 109 is completed, the IO processor 4 is transferred via the loop bus 406.
A report to that effect will be made on 04.
The IO processor processes the completion report. When the termination is reported to the input/output control circuit 360 via the loop bus 406 and the bus 390, the input/output control circuit 360 places the termination flip-flop 80 in the set state. Meanwhile, at the same time, the input/output control circuit 36
0 indicates whether the input/output operation was completed normally if the input/output command for the completion report was an instruction to output, whether retry processing was performed on the loop bus 406 or the IO station 407, etc. , stores the end interrupt status word indicating the cause of the abnormality, etc. in the buffer 380, and also stores the end interrupt status word in the input data from the input/output device 109 if the input/output command is an input instruction. It is additionally stored in the buffer 380, and it can be known from this end interrupt status word whether or not the 5 output operation has ended normally. When the arithmetic processing circuit 350 learns from the set state of the flip-flop 80 that the input/output operation has ended, it determines from the end interrupt status word stored in the buffer 380 whether the input/output operation has ended normally. That's why.

In this judgment, the input/output operation is completed normally,
Moreover, if it is determined that no retry processing has been performed, the arithmetic processing circuit 350
3 to connect the buffer 380 and the system control circuit 310, the JOB processor 402
Information for reporting completion to Batsuhua 380
Create above. Thereafter, the arithmetic processing circuit 350 activates the system bus control circuit 310, and sends information for reporting completion to the JOB processor 402, and input data if there is input data from the system bus control circuit 310 to the JOB processor 402, respectively. , to the main storage device 400, but the system bus control circuit 31 indicates that this transfer has been completed.
By leaving interrupt flip-flop 60 set when received from zero, interrupt line 44 is
This is where a termination interrupt is applied to the JOB processor 402 via. flipflop 60
is returned to the reset state after a sufficient time has elapsed for the JOB processor 402 to accept the termination interrupt, and the reset control for the flip-flops 70 and 80 is also performed by the interrupt priority determining circuit 340 described above. Although the explanation is delayed, this interrupt priority determination circuit 340 consists of flip-flops 70,
If 80 are placed in the set state at the same time, it is determined which one should be accepted first with priority.
When either of the flip-flops 70, 80 is placed in the set state, the arithmetic processing circuit 350 is started, and after this start-up, the flip-flops 70, 80 are returned to the reset state.

The above is the case when the input/output operation is completed normally, but when the input/output operation is not performed normally, the following process is taken. That is, if the arithmetic processing circuit 350 determines that the input/output operation is abnormal based on the end interrupt state word existing in the buffer 380, and that retry processing is not being performed, the data forming the end interrupt state word is also found. Analyze the cause of the abnormality and determine whether the abnormality is due to a permanent failure.
It is determined whether this is due to a transient failure. Specifically, it is sufficient to identify whether a permanent failure flag or a transient failure flag is set at two predetermined bit positions in the end interrupt state word. If this identification determines that there is a permanent failure, there is no point in performing retry processing, so the completion report processing is the same as when the input/output operation has completed normally without any retry processing. will be carried out. However, if it is determined that the failure is due to a transient failure and retry processing has not been performed, the loop bus 4
06, IO station 407, input/output device 10
9 is initialized as necessary, and then the input/output command is sent again, thereby performing retry processing at the IO processor level. The retry process is repeated until a normal end is not reported even after performing the retry process a predetermined number of times, or until a normal end is reported after several retries below the predetermined number of times. When retry processing is performed, retry information such as the number of retry processing and the end interrupt status word of each retry processing reaction is sequentially stored in the error log buffer 320. Gate 303 at the completion report timing in each retry process
The arithmetic processing circuit 350 may control the connection between the buffer 380 and the error log buffer 320, and also activate the error log control circuit 330. Error log control circuit 3
30 functions to manage updating the address of the error log buffer 320 as well as formatting the error log information.

By the way, if retry processing is performed at the loop bus 406 or IO station 407 instead of at the IO processor level, the retry information is stored in the buffer 380 at the timing of the normal completion report, and thereafter is processed by the arithmetic processing circuit 350. I.O.
Judgment processing is performed in the same manner as at the processor level. Therefore, regardless of where retry processing is performed, retry information is stored in error log buffer 320. Next, the arithmetic processing circuit 350 adds a distinction as to whether the retry processing was performed by the IO processor, the loop bus 406, the IO station 407, etc. to the end interrupt status word existing in the buffer 380, and 303 to 38
0 and the system bus control circuit 310, the contents of the buffer 380 are sent to the main storage device 400 in the same manner as if the retry process had not been performed. Finally, the arithmetic processing circuit 350
controls the gate 303 to connect the error log buffer 320 and the system bus control circuit 310, starts the system bus control circuit 310, and transfers the contents of the error log buffer 320 to the main memory 400.
It will be transferred to. When the system bus control circuit 310 reports the end of this transfer, the arithmetic processing circuit 350 interrupts the end interrupt flip-flop 60.
In other words, it is left in the set state. An overview of the processing performed by the IO processor 404 is shown in FIG.

Next, the JOB processor 402 will be explained with reference to FIG.

As shown in the figure, the JOB processor 402 includes a system bus control circuit 210 and an IO request flip-flop 1.
0, hard error flip-flop 20, timer interrupt flip-flop 30, termination interrupt acceptance flip-flop 40, interrupt priority determination circuit 24
0, arithmetic processing circuit 250, program counter 2
20, a general-purpose register 230, etc. Of these, the system bus control circuit 210 and the interrupt priority determination circuit 240 have the same functions as those shown in FIG. 2, but the arithmetic processing circuit 250 is slightly different from that shown in FIG. Various control programs 200 stored in the program area can be executed based on address data in the program counter 220. The instructions executed by the arithmetic processing circuit 250 include data transfer instructions between arbitrary addresses on the main storage device 400 and between the general-purpose registers 230, instructions related to calculations, logic, shifts, comparisons, etc., and instructions that satisfy conditions. There are instructions for rewriting the contents of the program counter 220 to an arbitrary address depending on whether or not the program has been accessed, and instructions for performing input/output operations. IO is one of the instructions for performing input/output operations.
There are instructions that cause the processor 404 to perform input/output processing. When the address and identification number of the IO processor 404 of the information created and stored in the main memory 400 instructing input/output operations are specified, a command is issued to place the IO request flip-flop 10 connected to the interrupt line 43 in the set state. is executed, and as described above, the IO processor 40
4, input/output operations are performed. on the other hand,
The IO processor 404 sends a completion report to the JOB processor 402 via the interrupt line 44, and the report is received by the completion interrupt reception flip-flop 40. When the flip-flop 40 is placed in a set state by accepting the end interrupt, and it is determined that the interrupt has the highest priority, information indicating the interrupt type is processed by the interrupt priority determination circuit 240. sent to circuit 250;
From then on, control is performed by interrupt reception firmware program 2.
60.

FIG. 4 a and b are area 1 on the main storage device 400.
This figure shows the structure of the interprocessor communication table stored and arranged in 00. As a table for inter-processor communication data, there is an interrupt message control table 103 that stores input/output operation instruction information, and manages the program state at the time of interrupt acceptance and the processing queue when interrupts occur consecutively. There is an interrupt level status table 102. The table configuration of the interrupt level status table 102 is as follows.
As shown in FIG. b, the interrupt level status table 102 is arranged at a fixed address on the main storage device 400 for each interrupt factor from each IO processor. When the interrupt reception firmware program is activated by a termination interrupt, the interrupt level status table on the main storage device 400 corresponding to the interrupt cause is accessed, and the address of the control program to be executed next is accessed. The value is obtained as the value stored at the address indicated by the sum of the contents of detailed factor 2 and the contents of pointer 3. After this interrupt processing is completed, the current program status word and the value of the program counter 220 necessary to restart the interrupted program are saved to the areas indicated by 5 and 6, and then a new program status word is saved. is obtained from the area indicated by 4, and the interrupt processing program is executed by jumping to the previously obtained interrupt processing program address. In FIG. 4b, reference numerals 7 and 8 are pointers for managing the interrupt acceptance queue, reference numeral 9 indicates the LOCK flag, and reference numeral 11 indicates the interrupt message control table connected to the queue. This is information indicating the number of 103 pieces.
The inter-processor communication system using tables has already been proposed as a patent application by some of the inventors of the present application.

FIG. 5 shows the processing flow of the above-mentioned interrupt processing program, and according to this, the processing for determining the presence or absence of error log information and the processing for determining the presence or absence of an error are stored in the interrupt message control table 103. This is done by the end interrupt status word.
If there is no error log information, a process is performed to determine the presence or absence of an error, and if it is determined that there is no error, a normal termination report process is performed, and if not, an error process or abnormal termination report process is performed. ing. On the other hand, if error log information exists, processing for starting a program for transferring error log information to a logout file and processing for starting an error log information output program are performed, and then processing for determining the presence or absence of an error is performed. If there is no error, normal termination reporting processing is performed; otherwise, error processing and abnormal termination reporting processing are performed.

As can be seen from Figure 5, the processing is broadly divided into the program startup processing part, which includes starting a program to transfer the error log information to the logout file, which is surrounded by a broken line, and finally the input/output processing ends normally. and a part that reports the results to the user program. Although not shown in FIG. 1, a logout file is connected to the system bus 401 via a file control processor (FCP), and the JOB processor 402 starts and controls the file control processor. There is. JOB processor 4
02, the file control processor first executes the error log information transfer program, which causes the file control processor to move to the logout area 30.
The error log information is read from 0 and is temporarily transferred and stored in the logout file. When the file control processor is then activated again, the file control processor reads out the error log information from the logout file, and the error log information is recorded and displayed by a suitable recording/displaying device. However, from the user program side, there is no change in the subsequent processing between the case where the input/output processing was performed normally as a result of retry processing and the case where the input/output processing was performed normally from the beginning. Therefore, if the interrupt handling program performs the process of transferring and storing error log information to the logout file, it will require waiting time and preprocessing time before the program starts, and this will result in overhead. It is clear that this results in a significant increase in time and poses a major problem in terms of processing performance.

On the other hand, if the memory capacity of the error log buffer 320 is limited from a hardware perspective, a problem arises in that the number of retries and information are also limited. In other words, Figure 6 shows the JOB processor (displayed as JOBP), IO
The relationship between the processor (displayed as IOP), input/output device (displayed as I/O) (and in some cases IO station (displayed as I/OST)) is shown along with error log information, etc., but if the IO processor has a transient failure It is necessary to store retry information in the error log buffer 320 every time it is detected.
Since the error log information is reported to the JOB processor at the end interrupt timing, and therefore the minimum required capacity of the error log buffer 320 is known, the capacity of the error log buffer 320 is kept at the minimum required. It has no choice but to become. If the capacity of the error log buffer 320 is set to the minimum required level, the number of retry processes and the amount of information will be limited, which poses a problem in terms of troubleshooting.

In other words, in the conventional input/output control method, JOB
On the processor side, processing of the termination interrupt program is complicated, and there is a drawback that the overhead time in normal operation from the user program's perspective increases significantly when retry processing is performed. Additionally, the capacity of the error log buffer on the IO processor side is limited, which has the disadvantage of limiting the number of retries.

Therefore, an object of the present invention is to simplify the termination interrupt program and reduce processing overhead time on the JOB processor side, and to provide input/output control that does not limit the number of retry processing on the IO processor side. Here's how to do it.

For this purpose, the present invention considers that the drawback of the conventional method is that error log information is also reported at the time of a termination interrupt, and the present invention increases the capacity of the error log buffer to provide error log information. This is an interrupt that is different from the end interrupt, and is reported at an independent timing that is different from the end interrupt timing.

The present invention will be explained below with reference to FIGS. 8 to 13.

First, an overview of the present invention will be explained with reference to an example of a multiprocessor system according to the present invention shown in FIG. 8 and a time chart shown in FIG. The file control processor (FCP) 403 and logout file 405 as file control devices in FIG. 8 have already been described.

As mentioned above, the IO processor 404 is activated by an input/output request from the JOB processor 402.
The activated IO processor 404 also activates the input/output device 109 according to the activation information.
Data input/output transfer is performed between the PC 9 and the PC 9, but let us assume that some kind of error occurs under such conditions. When an error occurs, the input/output device 109
terminates the input/output operation and executes the IO processor 404.
The occurrence of an abnormality is reported to the IO processor 404, which causes the IO processor 404 to import information related to the abnormality, such as the status of the input/output device 109 and the cause of the error, into the previously described error log buffer. The process up to this point is the same as the conventional case, but the difference is that the error log information in the error log buffer is not based on the timing of the end interrupt as shown in FIG. 9, but everything in the buffer 320 is based on the error log information. When the area is occupied, it is transferred from the error log buffer 320 to the logout area 300, and after that,
An error log interrupt can now be sent to the JOB processor 402. Since the capacity of the error log buffer 320 according to the present invention is at least larger than the minimum capacity required to support the specified number of retries, this allows error log interrupts to occur at a timing different from the end interrupt timing. It is something that will be done. That is,
If the input/output operation completes normally, or if the input/output operation is completed normally by retry processing within the specified number of retry processing, an end interrupt is generated to that effect, and retry processing is performed for the specified number of retry processing. Even if the input/output operation is not completed normally, a termination interrupt to that effect is sent to the JOB processor 40.
2, but these termination interrupts are not accompanied by the transfer of error log information. Error log information generated due to retry processing is captured into the error log buffer 320 until the inside of the error log buffer 320 is completely occupied by the error log information. Now, JOB processor 4
02, when it is learned from the end interrupt that the input/output operation has ended as abnormal, the input/output device 10
Necessary measures will be taken, such as trying the input/output operation again in 9, or performing input/output operation with other input/output devices connected to the same loop bus 406. If retry processing is still performed during input/output processing, the error log buffer 32 will be
It is clear that the interior of 0 will be entirely occupied by error log information. In the present invention, when the inside of the error log buffer 320 is completely occupied by error log information, the error log information is transferred to the logout area 300 and an error log interrupt is generated. Therefore, although the timing of the termination interrupt in the conventional method and that according to the present invention is the same, the contents differ depending on whether or not error log information is included. According to the present invention, the error log information is not accompanied by the error log information, and the error log information is accompanied by the error log interrupt. This error log interrupt is unique to the present invention, and for this purpose, a new interrupt line for this purpose is provided on the system bus 401, which will be described later.

When error log information is transferred to the logout area 300 as described above and an error log interrupt is issued to the JOB processor 402,
The timing of the error log interrupt is generally different from that of the end interrupt, and the amount of error log information transferred per time is larger than that of the conventional method, but due to the transfer rotation and its transfer. The number of error log interruptions is thus reduced compared to the termination interruption in the conventional method. In the conventional method
Since the error log report from the IO processor 404 was limited to the time of completion report, the JOB processor 4
As already mentioned, there is an upper limit to the amount of error log information that can be transferred due to the limit on the response time of one input/output operation from the point of view of 02. Therefore, the time required for error logging including JOB processor 402 and IO processor 404 is
It is given by the following formula.

Time required for error log (T1) = (Error log processing time of IO processor 404 (T _IOP ) + Time for transferring error log information from IO processor 404 to logout area 300 (T _traos ) + Error log processing time of JOB processor 402 (T _JOBP ))×n ...(1) Here, T _IOP and T _JOBP are error log processing 1
It takes a certain amount of time for each time, and T _traos is a processing time that increases in proportion to the capacity of error log information. Further, n is the number of times error log reporting has been performed.

On the other hand, if the error log interrupt method according to the present invention is used, even if the error log information of several times is accumulated in the error log buffer 320, the response time for one input/output operation is reduced. There will be no increase, only a decrease. This is because the error log request interrupt is set at a different timing from the end interrupt, and moreover, at a timing when the error log buffer 320 becomes full. Here, error log information for m termination interrupts using the conventional method is stored in the error log buffer 320.
JOB processor 402
This means that the number of error log reports can be reduced by 1/m compared to the conventional method.
When the conventional method performs error log processing n times using the method of the present invention, the required time is given by the following equation.

Error log processing time (T2) = (T _IOP + T _traos ) × n + T _JOBP × n/m ... (2) Comparing T1 and T2, the error log processing time in the JOB processor 402 is different between the conventional method and the method according to the present invention. It can be seen that it can be reduced to 1/m.
On the other hand, on the JOB processor 402 side, air log information can be transferred to the logout file 405 while the IO processor 404 is performing retry processing, reducing the processing overhead time in the JOB processor 402 and improving overall processing. The time will also be shortened.

Figures 10a and 10b are the JOB processor 40, respectively.
2 shows the flow of processing of the software program for the end interrupt and error log interrupt executed by No. 2. Since the end interrupt and the error log interrupt are reported to the JOB processor 402 at separate timings and in a differentiated state,
The programs for both interrupts can be separate. Now, to explain again the reason why the processing time in the JOB processor can be reduced to 1/m as a whole in relation to equation (2) with reference to FIG. The program and error log information output program are activated, but it is clear that both of these increase in proportion to the number of error log interruptions and do not depend on the amount of error log information. Furthermore, the data transfer process itself between the IO processor and the JOB processor, which is performed by the error log information transfer program and the error log information output program, is performed using the DMA (Direct Memory Access) method, which does not involve the JOB processor. Therefore, the processing time of the JOB processor does not depend on the amount of data transferred,
It is proportional only to the number of transfer processes themselves. From the above, it can be seen that the load on the JOB processor is basically proportional to the number of error log request interruptions, regardless of the amount of error log information. From the basic nature of error log processing performed by this JOB processor, it is recommended that the number of error log request interrupts be reduced to 1/m by the error log interrupt method according to the present invention. This will result in a reduction in processing time. In the case of separate processing, the processing for determining the presence or absence of error log information is not necessary in the interrupt processing, and the program can be simplified as shown in the figure. If the end interrupt processing and error log processing are performed independently, it is possible to expect improved processing performance.

The outline of the present invention is as above.
The configurations of the IO processor and JOB processor according to the present invention will be explained with reference to FIG. 1 and FIG. 12.

FIG. 11 shows the configuration of the IO processor, and the difference in configuration from that shown in FIG. 2 is that an error log request flip-flop 90 is newly provided. For this flip-flop 90, a new error log interrupt line 45 is provided on the system bus 401.

When the arithmetic processing circuit 350 in this figure is activated from the input/output control circuit 360 via the termination flip-flop 80, the input/output operation is completed normally, and the loop bus 406 and IO station 407
If retry processing is not performed, or if the input/output operation is abnormal and the abnormality is due to a permanent failure, the same processing as in the conventional case is performed. However, in other cases, the error log information is reported to the JOB processor 402 not at the end report timing by the end interrupt flip-flop 60, but at a different timing by the error log request flip-flop 90. Specifically, this occurs when the error log buffer 320 is completely occupied by retry information.

That is, according to FIG.
If you explain the processing contents at IO station 1,
When the end interrupt is received by the IO processor 404 from 09 onwards, it is first determined whether the result of the input/output operation is normal. If it is normal, the termination interrupt status word is terminated normally and a termination interrupt is issued to the JOB processor 402. Abnormal termination and IO
If the number of retry processes in the processor 404 exceeds the specified value or if retry processing is not possible due to a permanent failure, the end interrupt status word is set to abnormal termination, and the process is sent to the JOB processor 402 in the same manner as in the case of normal termination. A termination interrupt is applied. On the other hand, if the number of times of retry processing does not reach the specified value and the process ends due to a transient failure, retry processing is performed. If retry processing is enabled in the input/output device, the retry information in the input/output device is transferred to the error log buffer 320, and then the input/output device is restarted. A termination interrupt is issued to the JOB processor 402 in both cases of normal termination and abnormal termination, but from then on, depending on whether or not the IO station 407 or IO processor 404 itself performs retry processing, retry information may be sent to the JOB processor 402. The data is transferred to the error log buffer 320, and one input/output operation is completed.

It should be noted here that the timing of reporting the error log information to the JOB processor 402 is done when it is detected that the error log buffer 320 is completely occupied by retry information. If this is detected by the error log control circuit 330, the error log request flip-flop 90 is placed in the set state.
The arithmetic processing circuit 350 is informed via the priority determination circuit 340 that the flip-flop 90 is in the set state. is connected to the system bus control circuit 310. This connection causes error log information to be transferred to the logout area 300.

That is, the logout area 30 for error log information.
The transfer to 0 is done independently of the end interrupt. It is clear from FIG. 7 that in the past, it was necessary to issue a termination interrupt after transmitting the error log information to the logout area 300, and this increased the complexity and overhead time of the processing in the JOB processor 402. However, these drawbacks can be reduced by the present invention.

Finally, the JOB processor according to the present invention will be explained with reference to FIG. Figure 12 shows its configuration,
With the addition of a new error log interrupt line 45 to the system bus 401, an error log request receiving flip-flop 50 is newly provided. The function performed by flip-flop 50 is similar to that of flip-flop 40 for accepting termination interrupts. However, since the priority determination circuit 240 determines that the interrupts have different priorities, the interrupt processing program to which control is transferred after passing through the interrupt reception firmware 260 is the termination interrupt program and the error log interrupt. It can be separated into a program.

As explained above, the present invention applies an error log interrupt to the JOB processor when the large-capacity error log buffer is completely occupied by retry information, and also sends an error log interrupt to the logout area on the main memory. Error log information is transferred from an error log buffer. Therefore, according to the present invention, the timing of the error log interrupt is made different from that of the end interrupt, which simplifies the interrupt processing program and reduces processing overhead time in the JOB processor. Such,
Various effects can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the system configuration of an example of a multiprocessor system according to the prior art, and FIG.
Figure 3 shows an example of the configuration of the JOB processor and IO processor in this configuration, and Figures 4a and 4b respectively show the configuration of the JOB processor and IO processor stored in the inter-processor communication area on the main memory in the same configuration. 5 is a diagram showing the processing flow of the interrupt processing program executed by the JOB processor, and FIG. 6 is a diagram showing the structure of the communication table for the JOB processor, IO processor, and Figure 7 shows the flow of processing performed between IO
FIG. 8 is a diagram showing an overview of the processing performed by the processor, and FIG. 9 is a diagram showing the system configuration of an example of the multiprocessor system according to the present invention.
Figures 10a and 10b, which are diagrams showing the flow of processing according to the present invention performed between the JOB processor, IO processor, and input/output device, show responses to termination interrupts and error log interrupts executed by the JOB processor. Figures 11 and 12 are diagrams showing the flow of program processing, and Figures 11 and 12 are diagrams showing the configuration of an example of the IO processor and JOB processor in Figure 8. Figure 13 is the process performed by the IO processor according to the present invention. FIG. 400...Main storage device, 300...Logout area, 402...JOB processor, 403...
File control processor, 404...
IO processor, 405...Logout file, 109...I/O device, 45...Error log interrupt line, 90...Error log request flip-flop, 50...Error log request reception flip-flop, 320...Error log buffer.

Claims (1)

[Claims] 1 The input/output data transfer control between the main processor and the input/output device is mainly performed by the input/output control processor, and the input/output data transfer between the input/output control processor and the input/output device is In a multiprocessor system, when a transient error or failure occurs during processing, an input/output control processor retries input/output data transfer within a specified number of times in order to recover from the error or failure. , error log information as retry information that is sequentially accumulated in the input/output control processor each time an input/output data transfer is retried, the amount of error log information corresponds to the specified number of retries. Each time a certain value, which is larger than An input/output control method characterized in that an input/output control processor issues a termination interrupt to a main processor at a different timing.