JPS62295147A - Virtual computer system - Google Patents

Abstract

PURPOSE:To improve a performance by deleting a TLB entry in which the identifier of a designated virtual computer coincides with an identifier field at the time of issuing a nullification instruction for setting the invalid but of a page table entry to 1 by designating the identifier of the virtual computer. CONSTITUTION:The contents of a page table entry are held in a register 110 and a VM-id designated by an instruction is held respectively in a register 111. Both the outputs are inputted to a TLB entry selection mechanism 112. In the mechanism 112, the TLB entry in which the contents of the register 110 coincide with the AA field in a TLB113 and the TLB entry in which the contents of the register coincide with the VM-id field in the TLB113 are selected. To the invalid field of the selected TLB entry, 1 is set by a TLB nullification mechanism 114, the TLB entry is nullified and the TLB entry is deleted.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a virtual computer system having TLBt, and particularly to speeding up the system.

[Conventional technology]

FIG. 4 shows a main configuration diagram of the actual computer system 1000.

100 is a central processing unit CPU, 200 is a main storage device, 3
00 is the input/output processor 10P, and 400 is the input/output side tilting device 10C. 10 is a signal line between the CPU 100 and the main storage device 200, 20 is a signal line between the CPU 100 and 10P
30 is a signal line between l0P300 and main storage device 200, 40 is a signal line between l0P300 and l0C
Uko real computer system 1 which is the signal line between 400
000 operates under the control of the overall system resources (CPU, main memory, input/output device) managed by the operating system (O8) on the main memory 200.

In contrast, FIG. 2 shows a configuration diagram of a virtual computer system (VMS). The actual computer system 1000 is shown in FIG. 1 and has a hardware configuration (CPU.

The main storage device (main storage device, input/output device) remains the same, but the main storage device 2
The difference is that a vMs control program VMCP (or simply referred to as CP) exists on 00.

The hardware simulation function of VMCP allows you to create a physical computer (called a virtual machine, VM).
is realized logically in multiple units. Each VM, i.e. 1000
1 (VMI), 1000 2 (VM2), 1001
000-3 (V is logically realized as having the same hardware configuration as the actual computer system (referred to as host system) 1000.

Each VMO main storage device 200-N (N=1.2.3)
Above there are 08-Ns that control and operate each VMt,
This shows that the plurality of O8s are running simultaneously under one host system. The hardware configuration of each VM in Figure 2 (CPU, main storage, IOP
, 10C) are more logically realized than VMCPIIC, but most of their substance exists on the corresponding hardware configuration of the host system. for example,
The VMO main storage device is the main storage device 20 of the host system.
It is possible to exclusively own a part of 0, and it is also possible to share it. Also, the input/output device of the VM can be shared between the host system's input/output device t and VM. It may also monopolize the input/output devices. Alternatively, there is a case where there is no corresponding input/output device on the host system, and it is realized completely virtually, similar to VMCP. In any case, each VM.

From O8 on the main storage device 200-N (N=1.2.3), the hardware configuration (CPU
, main memory IOP, l0C). It should be noted here that the architecture of each VM (hardware configuration and function from the perspective of O8) may be somewhat different from the architecture of the host system 1000. Similarly, VMs may have different architectures. For example, the host system's machine instruction set and each VM's machine instruction set may not be exactly the same. However, it is completely different (DHj:, VMC
Since the load on P is not heavy and the emulation machine of the host system is also large, VMC in the present invention is
Excluded from P. In Figure 2, only three VMs are defined, but there may be any number of VMs for -1 throw, and the upper limit is determined based on the resource capacity of the host system and the performance of each VM. Ru.

[Problem that the invention seeks to solve]

Here, if the host system issues an instruction to invalidate the page table, the specified host's en)l
In addition to deleting Jk, it is necessary to delete all guest entries related to that host entry. For information on how to achieve this, please refer to the IBM Journal
al of Re5archand l) evelo
pment) Volume 27, No. 6 P, H, Gum (
Virtual Machines (System/370 Exten
ded Architecture;
s for Virtual Machines)”
As discussed in the document entitled K, normally all guest entries in the real TLB must be deleted. According to this method, guest TLB entries that do not need to be deleted are also deleted, which reduces TLB usage efficiency and leads to a decrease in the performance of the virtual computer system.

An object of the present invention is to avoid deleting valid TLB entries in an instruction to invalidate a page table, thereby increasing the efficiency of TLB use and improving the performance of a virtual computer system. There is a particular thing.

[Means for solving problems]

The virtual machine system of the present invention retains a virtual machine identifier field in a TLB, and includes an invalidation instruction that specifies the virtual machine identifier and sets an invalidation bit of a page table entry to 1, and when the invalidation instruction is issued. When the invalidation bit fel of the page table entry is set, the TLB entry whose virtual machine identifier field in the TLB matches the virtual machine identifier specified by the invalidation instruction is deleted.

[Effect]

According to the above-described configuration, by specifying "VMidt" in an invalidation instruction that sets the invalidation bit of a page table entry to 1, it is possible to delete only a specific entry of '['LB.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 and 3.

FIG. 3 is an explanatory diagram showing the format of an invalidation instruction for setting the page table long-term invalidation bit to 1 according to the present invention. Instruction 201 on the storage device specifies Op-Code and registers R1 and R2. Register R, [101
) is the page table origin CPTO) and the location where the virtual machine identifier (VM-id) is stored (202
) address (X) is held. Register R2 (102
) holds the virtual address. When the invalidation instruction 201 is issued, the invalidation bit of the page table entry indicated by the PTO in X (202) indicated by R1 (101) and the page index (PX) of the virtual address in %2 (102) Set to t-1. And R
Q in A (202) indicated by 1 (101):) V M
-id Delete the corresponding entry in the TLB that matches d.

FIG. 1 is a block diagram of an apparatus for deleting TLB entries according to the present invention. The apparatus shown in FIG. 4 includes a register (absolute address holding register) 110 . 1/register (VM-id holding register) 111 that holds the VM-id specified by the instruction. TL
B entry selection mechanism 112. It is composed of a TLB 113 and a TLB invalidation mechanism 114. The absolute address holding register 110 stores the contents of the page table entry indicated by PTO and PX specified by the instruction. V.M.
-id holding register 111 contains the VM specified by the instruction.
ID is stored. TLB113 has a virtual address field (VA), an absolute address field (AA),
It consists of a virtual machine identifier field (VM-id), a segment table start address field (STO), and an invalid field (I).

The operation of FIG. 1 is as follows. The absolute address holding register 110 and the VMid holding register 111 are TLB
This serves as an input to the entry selection mechanism 112. The TLB entry selection mechanism 112 selects a TL whose AA field in the TLB 113 matches the contents of the absolute address holding register 110.
B entry.

and the contents of the vM-id holding register 111 and the TLB 11
3 OVM ta mitsu yield car TLB en)
Select li. The TLB invalidation mechanism 114 is.

The *TL selected by the TLB entry selection mechanism 112
B two-lint reyield 1c1f: Set.

By setting the field of the TLB 113 to 1, the TLB entry becomes invalid and the TLB entry is deleted.

〔Effect of the invention〕

According to the invention, an invalid page table entry
By specifying V M -id in the invalidation instruction set to t-1, it is possible to delete only a certain number of entries in the TLB, increasing the TLB usage efficiency and improving the performance of the VMS. Possible. The system of the present invention is particularly effective when the presence of vM information in the TLB greatly affects the performance of the entire VMS.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a device for deleting TLB entries according to the present invention, Fig. 2 is a block diagram of a virtual machine system (VMS), and Fig. 3 is a configuration diagram of a device for deleting a TLB entry according to the present invention. FIG. 4, which is an explanatory diagram showing the format of the invalidation instruction, is a block diagram of an actual computer system using a normal O8. 1000...actual computer system, 100...CPU
. 100-N...CPUN N=1. 2. 3.・
・,・200...Main storage device, 200-N...VM
-N main memory e (N= 1. 2. 3. ・)
, 300... Kapuro in and out! =Nia? I OF,
300-N...VM-NOI OF (logical)
, 400...Person output control device l0C400-N・VM
-N (N=1.2.3.-) (7) IOC, 10...
・CPU-main storage interface, 20...C
PU-loP interface, 30...10P-main storage interface, 40...10P-IOC
interface, 101... register (FLI),
102...Register (R, 2), 201-...Invalidation instruction, 2Q2/PTOlVM-iid storage area, 1
10...Absolute address holding register% 111...
VM-id holding register, 112...TLB entry selection mechanism, 113...TLB, 114...TLB invalidation mechanism. ￥31 Figure 1/ρ

Claims (1)

[Claims] 1. At least one operating system
A TL that is equipped with a management program that runs simultaneously on two real computers, is equipped with a TLB, and operates under a virtual memory system.
In a virtual machine system having B, each entry of the TLB holds an invalid field, a segment table start address field, a virtual address field, an absolute address field, and a virtual machine identifier field, and the page table start address, A page index part of a virtual address and an invalidation instruction that specifies a virtual machine identifier and sets an invalid bit of a page table entry to 1, and the virtual machine identifier specified by the invalidation instruction and the TLB. The contents of the page table entry indicated by the page index part of the page table start address and virtual address specified by the invalidation instruction and the absolute address in the TLB match.・Equipped with means for selecting a TLB entry whose fields match, and when the invalidation instruction is issued, sets the invalidation bit of the page table entry indicated by the page table start address and virtual address to 1, and ,
A virtual computer system characterized in that the corresponding entry of the TLB selected by the selection means is deleted.