JPS62277066A - Voltage doubler - Google Patents
Voltage doublerInfo
- Publication number
- JPS62277066A JPS62277066A JP11947486A JP11947486A JPS62277066A JP S62277066 A JPS62277066 A JP S62277066A JP 11947486 A JP11947486 A JP 11947486A JP 11947486 A JP11947486 A JP 11947486A JP S62277066 A JPS62277066 A JP S62277066A
- Authority
- JP
- Japan
- Prior art keywords
- input
- signal
- capacitors
- amplified
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009825 accumulation Methods 0.000 claims 1
- 239000003990 capacitor Substances 0.000 abstract description 13
- 230000003321 amplification Effects 0.000 abstract 1
- 238000003199 nucleic acid amplification method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 241000026407 Haya Species 0.000 description 1
Landscapes
- Dc-Dc Converters (AREA)
Abstract
Description
【発明の詳細な説明】 3、発明の詳細な説明 〔並業上の利用分野〕 本発明は、信号の電圧を増幅する倍電圧器に関する。[Detailed description of the invention] 3. Detailed description of the invention [Field of use in the field of work] The present invention relates to a voltage doubler that amplifies the voltage of a signal.
従来、この種の倍電圧器としては、能動素子であるオペ
・アンプに適当な値の抵抗を外付けしたものがあった。Conventionally, this type of voltage doubler has consisted of an operational amplifier, which is an active element, and an external resistor of an appropriate value.
上述した従来のオペ・アンプを用いた倍電圧器は、オペ
・アンプがトランジスタ等を使用した能動素子であるた
め、温度に対して不安定であり、倍率の精度の向上が困
難であるという欠点がある。The conventional voltage doubler using an operational amplifier described above has the disadvantage that because the operational amplifier is an active element using a transistor, etc., it is unstable with respect to temperature and it is difficult to improve the accuracy of the multiplication factor. There is.
〔問題点を4N−決するための手段〕
本発明の倍電圧器は複数の電圧場積部と、第1〜第3の
入出力端と、前記複数の電圧蓄積部を前記第1の入出力
端から切り離して前記第2および第3の入出力端間に直
列にまたは前記第2の入出力端から切り離して前記第1
および第3の入出力端間に並列に切換えて接続可能なス
イッチ+段とを含み、前記第1および第3(または前記
第2および第3)の入出力端間から入力した被M幅信号
を倍圧して前記第2および第3(または前記第1および
第3)の入出力端間から出力することを特徴とする。[Means for resolving the problem] The voltage doubler of the present invention includes a plurality of voltage field product sections, first to third input/output terminals, and a plurality of voltage storage sections connected to the first input/output terminals. the second and third input/output terminals, or the second input/output terminal and the first input/output terminal;
and a switch+stage that can be switched and connected in parallel between the third input and output terminals, and the M-width signal input from between the first and third (or second and third) input and output terminals. The voltage is doubled and output from between the second and third (or first and third) input and output terminals.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は、本考案の一実施例である2倍倍電圧器の回路
図である。1は被・曽幅信号の入力部である。2〜6は
制御信郵に同期して作動するスイッチであり、スイッチ
2.4.6は第1の制御信号に同期して開閉し、スイッ
チ3,5は第2の制御信号に同期して開閉する。FIG. 1 is a circuit diagram of a voltage doubler that is an embodiment of the present invention. Reference numeral 1 denotes an input section for receiving and sub-width signals. 2 to 6 are switches that operate in synchronization with the control signal, switches 2.4.6 open and close in synchronization with the first control signal, and switches 3 and 5 in synchronization with the second control signal. Open and close.
まず、入力部1に被増幅信号を加える。さらに第1の制
御信号を与えてφスイッチ2,4.6を閉じることによ
り、第2図のように2つのコンデンサ7.8は、被増幅
信号の入力に対して並列に接続される。2つのコンデン
サ7.8の容量が等しいとき、被増幅信号の電圧は両コ
ンテンサ7゜8に等しく蓄積される。続いて第1の制御
信号の入力をやめてスイッチ2,4.6’e15Hけ、
かわりに第2の制御信号を与えて、スイッチ3.5を閉
じる。これにより、第3図のように両コンデンサ7.8
は直列に接続され、信号出力部9には被増幅信号の入力
の2倍の信号電圧が出力される。First, an amplified signal is applied to the input section 1. Furthermore, by applying the first control signal to close the φ switches 2, 4.6, the two capacitors 7.8 are connected in parallel to the input of the signal to be amplified, as shown in FIG. When the capacitances of the two capacitors 7.8 are equal, the voltage of the amplified signal is equally stored in both capacitors 7.8. Then, stop inputting the first control signal and turn on switch 2, 4.6'e15H.
Instead, a second control signal is applied to close switch 3.5. As a result, as shown in Figure 3, both capacitors 7.8
are connected in series, and a signal voltage twice as high as that of the input signal to be amplified is outputted to the signal output section 9.
なお、被増幅信号の変化に対してはスイッチ2〜6の開
閉金繰り返すことにより追従できる。Incidentally, changes in the amplified signal can be followed by repeatedly opening and closing the switches 2 to 6.
また第1図の出力部9に被増幅信号を加えれば、被増幅
信号の1/2倍の電圧の信号全入力端1に得ることがで
きる。Furthermore, by adding the amplified signal to the output section 9 in FIG. 1, a signal having a voltage 1/2 times that of the amplified signal can be obtained at all input terminals 1.
また、コンデンサ7.8の容量が等しくなくても本発明
は実施できる。Further, the present invention can be implemented even if the capacitances of the capacitors 7.8 are not equal.
さらに、本発明は3つ以上のコンデンサを並列または直
列に切換えて接続するようにしてもよい。Further, in the present invention, three or more capacitors may be connected in parallel or in series.
以上説1明したように本発明は、受動素子であるコンデ
ンサを用いることにより、能動素子の沖1′幅でみられ
る温度変化による出力の不安定さを解消できる効果があ
る。As explained above, by using a capacitor which is a passive element, the present invention has the effect of eliminating the instability of the output due to temperature changes observed in the 1' width of the active element.
第1図は本発明の一実施例の回路図、第2図及び第3図
は第1シ1に示す実施例の倍圧型動作時の回路図で、そ
れぞれスイッチ2,4.6’を閉じた状態およびスイッ
チ3,5を閉じた状態である。
1・・・・・・被増幅信号の入力部、2〜6・・・・・
・スイッチ、7,8・・・・・・コンデンサ、11・・
・・・・増幅信号の出力部。
代理人 弁理士 内 原 晋 ニー、−
早/ 図
!
粂2図 第3図
!FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams of the embodiment shown in FIG. and the switches 3 and 5 are closed. 1...Input section for amplified signal, 2-6...
・Switch, 7, 8...Capacitor, 11...
...Amplified signal output section. Agent Patent Attorney Susumu Uchihara Ni, - Haya / Figure! Figure 2 Figure 3!
Claims (1)
数の電圧蓄積部を前記第1の入出力端から切り離して前
記第2および第3の入出力端間に直列にまたは前記第2
の入出力端から切り離して前記第1および第3の入出力
端間に並列に切換えて接続可能なスイッチ手段とを含み
、前記第1および第3(または前記第2および第3)の
入出力端間から入力した被増幅信号を倍圧して前記第2
および第3(または前記第1および第3)の入出力端間
から出力することを特徴とする倍電圧器。A plurality of voltage storage units, first to third input/output terminals, and the plurality of voltage accumulation units are separated from the first input/output terminal and connected in series between the second and third input/output terminals, or Said second
switch means that can be connected in parallel between the first and third input/output terminals by being separated from the input/output terminals of the first and third (or second and third) input/output terminals; The amplified signal input from both ends is doubled and the second
and a voltage doubler that outputs from between the third (or the first and third) input and output terminals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11947486A JPS62277066A (en) | 1986-05-23 | 1986-05-23 | Voltage doubler |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11947486A JPS62277066A (en) | 1986-05-23 | 1986-05-23 | Voltage doubler |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62277066A true JPS62277066A (en) | 1987-12-01 |
Family
ID=14762201
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11947486A Pending JPS62277066A (en) | 1986-05-23 | 1986-05-23 | Voltage doubler |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62277066A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100615837B1 (en) * | 1999-03-11 | 2006-08-25 | 세이코 엡슨 가부시키가이샤 | Voltage booster circuit, voltage boosting method, and electronic unit |
-
1986
- 1986-05-23 JP JP11947486A patent/JPS62277066A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100615837B1 (en) * | 1999-03-11 | 2006-08-25 | 세이코 엡슨 가부시키가이샤 | Voltage booster circuit, voltage boosting method, and electronic unit |
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