JPS62276836A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62276836A JPS62276836A JP61119082A JP11908286A JPS62276836A JP S62276836 A JPS62276836 A JP S62276836A JP 61119082 A JP61119082 A JP 61119082A JP 11908286 A JP11908286 A JP 11908286A JP S62276836 A JPS62276836 A JP S62276836A
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- semiconductor element
- semiconductor device
- element mounting
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229920005989 resin Polymers 0.000 claims abstract description 10
- 239000011347 resin Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 3
- 230000005496 eutectics Effects 0.000 abstract description 11
- 239000000463 material Substances 0.000 abstract description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
（産業上の利用分野）
この発明は、プリント配線板などの、導電性配線パター
ンが形成された絶縁性基板に、半導体素子を直接実装し
てなるチップ・オン・ボード型の半導体装置に関するも
のである。[Detailed Description of the Invention] 3. Detailed Description of the Invention (Field of Industrial Application) This invention is a method for directly mounting a semiconductor element on an insulating substrate on which a conductive wiring pattern is formed, such as a printed wiring board. The present invention relates to a chip-on-board type semiconductor device.
（従来の技術）
従来、半導体素子をプリント配線板などの絶縁性基板に
直接実装してなるチップ・オン・ボード型半導体装置は
、その構造上の利点（小型、軽量）により、特に実装密
度の向上が要求される各種電子機器に好んで用いられて
いる。(Prior Art) Conventionally, chip-on-board type semiconductor devices, in which semiconductor elements are directly mounted on an insulating substrate such as a printed wiring board, have been particularly popular in terms of packaging density due to their structural advantages (small size and light weight). It is preferred for use in various electronic devices that require improved performance.
第２図は、そのチップ・オン・ボード型半導体装置の従
来の一構成例を示す断面図である。図において、半導体
素子１は、絶縁性基板２の表面に、接着剤３を用いて接
着固定され、その後、絶縁性基板２の表面に形成された
パターン４にワイヤー５を用いて配線接続される。次い
で素子部と配線部は樹脂６で封止されるものであり、こ
の樹脂６は、周囲の枠７により、流れ出るのが防止され
ている。FIG. 2 is a sectional view showing an example of a conventional structure of the chip-on-board type semiconductor device. In the figure, a semiconductor element 1 is adhesively fixed to the surface of an insulating substrate 2 using an adhesive 3, and then connected to a pattern 4 formed on the surface of the insulating substrate 2 using wires 5. . Next, the element section and the wiring section are sealed with resin 6, and this resin 6 is prevented from flowing out by a surrounding frame 7.
（発明が解決しようとする問題点）
しかしながら、上記構成の従来装置では、発熱の大きい
半導体素子１例えばバイポーラＩＣあるいは２５６ Ｋ
Ｄ ＲＡＭのごときＮ−ＭＯＳの高集積ＬＳＩを搭載す
る場合、熱放散性が悪いという問題点があった。また、
裏面にパックバイアス電圧の印加を必要とする素子１
（Ｎ−ＭＯＳなど）を搭載する場合には、絶縁性基板２
の表面に接続用のパターンを形成し、素子１の裏面とパ
ターンを導電性のある方法で接続する必要があり、しか
も、この接続には、絶縁性基板２を高温にできない点を
考えれば、高温の必要な共晶などのメタリックな接続が
できないため導電性樹脂を用いることになり、そのため
、接触抵抗が増大するなどの問題点があった。(Problems to be Solved by the Invention) However, in the conventional device having the above configuration, the semiconductor element 1 that generates a large amount of heat, such as a bipolar IC or a 256 K
When mounting a highly integrated N-MOS LSI such as a DRAM, there is a problem in that heat dissipation is poor. Also,
Element 1 that requires application of pack bias voltage to the back side
(N-MOS etc.), insulating substrate 2
It is necessary to form a connection pattern on the surface of the element 1, and to connect the back surface of the element 1 and the pattern in a conductive manner.Moreover, considering that the insulating substrate 2 cannot be heated to a high temperature for this connection, Since metallic connections such as eutectic, which require high temperatures, cannot be made, conductive resins have to be used, which poses problems such as increased contact resistance.
この発明は、以上述べた熱放散性と素子裏面の接続の問
題点を除去し、電気的特性の優れたチップ・オン・ボー
ド型の半導体装置を提供することを目的とする。An object of the present invention is to provide a chip-on-board type semiconductor device which eliminates the above-mentioned problems in heat dissipation and connection on the backside of an element and has excellent electrical characteristics.
（問題点を解決するための手段）
この発明では、半導体素子を収容するように形成された
素子搭載用部品内に半導体素子が搭載され、その素子搭
載用部品が絶縁性基板に形成された貫通孔に嵌着される
。(Means for Solving the Problems) In the present invention, a semiconductor element is mounted within an element mounting part formed to accommodate the semiconductor element, and the element mounting part is a through hole formed in an insulating substrate. Fitted into the hole.
（作 用）
このような構成によれば、素子搭載用部品を高温に耐え
得る素材で形成しておけば、該素子搭載用部品が絶縁性
基板の貫通孔に嵌着される前に、該素子搭載用部品内に
共晶で半導体素子を接続（搭載）することができる。ま
た、半導体素子の裏面は、素子搭載用部品を通して絶縁
性基板の表面に電気的に引出されるようになり、さらに
、素子搭載用部品の底部は、絶縁性基板の裏面に露出す
ることとなる。また、半導体素子は、樹脂封止前であれ
ば、素子搭載用部品ごと絶縁性基板の貫通孔から外して
交換できる。(Function) According to such a configuration, if the element mounting part is made of a material that can withstand high temperatures, the element mounting part can be inserted into the through hole of the insulating substrate before the element mounting part is fitted into the through hole of the insulating substrate. A semiconductor element can be connected (mounted) within the element mounting component using eutectic. In addition, the back side of the semiconductor element will be electrically drawn out to the surface of the insulating substrate through the element mounting parts, and the bottom of the element mounting part will be exposed on the back side of the insulating board. . Further, before the semiconductor element is sealed with resin, the semiconductor element can be replaced together with the element mounting parts by being removed from the through hole of the insulating substrate.
（実施例）
以下この発明の一実施例を図面を参照して説明する。第
１図はこの発明の一実施例を示し、（ａ）は一部を取出
して示す側断面図、（ｂ）は全体の側断面図、（ｃ）は
バックバイアス電圧印加の配線法（素子裏面配線）を説
明するための側断面図である。(Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, in which (a) is a side sectional view showing a part thereof, (b) is a side sectional view of the whole, and (c) is a wiring method for applying a back bias voltage (device FIG.
これらの図において、１１は素子搭載用部品で、上面が
開口された箱型に形成されており、上端には７ランジｌ
ｌａを有する。また、この素子搭載用部品１１は、後述
する半導体素子の接続固定に共晶を用いる場合は、高温
（４００〜４５０℃）に耐え得る素材（例えば４２アロ
イなどの金駕質）で形成される。このような素子搭載用
部品１１内には、該部品１１の底部上に共晶などの手段
で接続固定して半導体素子１２が搭載される。In these figures, reference numeral 11 denotes an element mounting component, which is formed into a box shape with an open top surface, and has 7 langes l at the top end.
It has la. In addition, when using eutectic for connecting and fixing semiconductor elements, which will be described later, this element mounting component 11 is made of a material that can withstand high temperatures (400 to 450°C) (for example, a metallic material such as 42 alloy). . In such an element mounting component 11, a semiconductor element 12 is mounted on the bottom of the component 11 by being connected and fixed by means such as eutectic.
１３は絶縁性基板で、主表面上には導電性配線パターン
１４が形成される。また、この絶縁性基板１３の所定位
置には貫通孔１５が形成されるものであり、この貫通孔
１５には前記半導体素子１２を搭載した素子搭載用部品
１１が嵌着される。この際、固定強度に不安のある場合
は、エポキシ樹脂などで素子搭載用部品１１を貫通孔１
５内に接着固定してもよい。そして、この嵌着後、素子
搭載用部品１１内の半導体素子１２の表面の電極は、ワ
イヤー１６（金属細線）を用いて前記絶縁性基板１３上
の配線パターン１４に配線されている。Reference numeral 13 denotes an insulating substrate, on the main surface of which a conductive wiring pattern 14 is formed. Further, a through hole 15 is formed at a predetermined position of the insulating substrate 13, and the element mounting component 11 on which the semiconductor element 12 is mounted is fitted into the through hole 15. At this time, if you are concerned about the fixing strength, attach the element mounting part 11 to the through hole 1 using epoxy resin or the like.
It may also be fixed with adhesive within 5. After this fitting, the electrodes on the surface of the semiconductor element 12 in the element mounting component 11 are wired to the wiring pattern 14 on the insulating substrate 13 using wires 16 (thin metal wires).
この時、同時に、半導体素子１２の裏面にパックバイア
ス電圧（ＶＢＢ 、 ＶＤＤ 、ＧＮＤ ナト） 全印
加するための配線を行う時は、第１図（ｃ）に示すよう
に、素子搭載用部品１１のフランツｌｌａと絶縁性基板
１３上の配線パターン１４とをワイヤー１６ａで接続す
る。すなわち、半導体素子１２の裏面は、例えば共晶接
続部および素子搭載用部品１１（この時、部品１１は金
属など導電体で形成されていることが必、要である）を
通して、該部品１１の基板１３表面に位置する７ランノ
ｌｌａに電気的に引出されている。したがって、このフ
ランジｌｌａと配線パターン１４をワイヤー１６ａで接
続することにより、素子搭載用部品１１を利用してパッ
クバイアス電圧を素子１２裏面に印加できるのである。At this time, when wiring for applying all the pack bias voltages (VBB, VDD, GND) to the back surface of the semiconductor element 12 is performed, as shown in FIG. The Franz lla and the wiring pattern 14 on the insulating substrate 13 are connected with a wire 16a. That is, the back surface of the semiconductor element 12 is connected to the back surface of the component 11 through, for example, the eutectic connection part and the element mounting component 11 (at this time, the component 11 must be made of a conductive material such as metal). It is electrically drawn out to the 7-lanyard located on the surface of the substrate 13. Therefore, by connecting this flange lla and the wiring pattern 14 with the wire 16a, the pack bias voltage can be applied to the back surface of the element 12 using the element mounting component 11.
そして、このような配線を打った上で、該配線部と半導
体素子部は樹脂１７で封止されており、絶縁性基板１３
上には、その樹脂１７の流れ土用の枠１８が取り付けら
れている。After forming such a wiring, the wiring part and the semiconductor element part are sealed with resin 17, and the insulating substrate 13 is sealed.
A frame 18 for the flow of the resin 17 is attached on top.
なお、上記一実施例では素子搭載用部品１１が箱型に形
成されているが、フ字型などでもよく、要は、半導体素
子１２を収容できる形状に形成されていればよい。In the above embodiment, the element mounting component 11 is formed into a box shape, but it may be formed into a box shape or the like, as long as it is formed into a shape that can accommodate the semiconductor element 12.
（発明の効果〕
以上実施例で詳述したように、この発明では、半導体素
子を収容するように形成された素子搭載用部品内に半導
体素子が搭載され、その素子搭載用部品が絶縁性基板に
形成された貫通孔に嵌着されるものであり、したがって
、素子搭載用部品を高温に耐え得る素材で形成しておけ
ば、該素子搭載用部品が絶縁性基板の貫通孔に嵌着され
る前に、該素子搭載用部品内に共晶で半導体素子を接続
（搭載）することができる。また、半導体素子の裏面は
、素子搭載用部品を通して絶縁性基板の表面に電気的に
引出されるようになり、したがってこの素子搭載用部品
を利用してパックバイアス電圧の印加全容易に行うこと
ができる。この時、上述のように半導体素子と素子搭載
用部品と全共晶で接続しておくことにより、相互の接触
抵抗を減少させることができる。また、半導体素子を搭
載した素子搭載用部品の底部は、絶縁性基板の裏面に露
出することになるので、その露出部から半導体素子の熱
放散を良好に行うことができる。この時、上述のように
半導体素子と素子搭載用部品とを共晶で接続しておけば
、相互の熱伝導性が良好であるから、より良く熱放散を
行うことができる。(Effects of the Invention) As described in detail in the embodiments above, in this invention, a semiconductor element is mounted in an element mounting part formed to accommodate a semiconductor element, and the element mounting part is mounted on an insulating substrate. Therefore, if the element mounting parts are made of a material that can withstand high temperatures, the element mounting parts can be fitted into the through holes of the insulating substrate. The semiconductor element can be connected (mounted) with eutectic in the element mounting component before the semiconductor element is mounted.Also, the back side of the semiconductor element is electrically drawn out to the surface of the insulating substrate through the element mounting component. Therefore, it is possible to easily apply the pack bias voltage using this device mounting component.At this time, as mentioned above, the semiconductor device and the device mounting component are connected with all eutectic. In addition, since the bottom of the element mounting component on which the semiconductor element is mounted is exposed on the back surface of the insulating substrate, the semiconductor element can be seen from the exposed part. Good heat dissipation can be achieved.At this time, if the semiconductor element and the element mounting parts are connected with eutectic as described above, mutual thermal conductivity is good, so heat dissipation is better. It can be performed.
これらの結果、発熱の大きな半導体素子の搭載が可能と
なる。また、半導体素子は、樹脂封止前であれば、素子
搭載用部品ごと絶縁性基板の貫通孔から外して交換でき
る。したがって、複数個の半導体素子を搭載する場合や
、高価な基板を使用する場合などに非常に有利である。As a result, it becomes possible to mount semiconductor elements that generate a large amount of heat. Further, before the semiconductor element is sealed with resin, the semiconductor element can be replaced together with the element mounting parts by being removed from the through hole of the insulating substrate. Therefore, it is very advantageous when mounting a plurality of semiconductor elements or when using an expensive substrate.
第１図はこの発明の半導体装置の一実施例を示し、（ａ
）は一部を取出して示す側断面図、ら）は全体の側断面
図、（ｃ）はパックバイアス電圧印加の配線法を説明す
るための側断面図、第２図は従来の半導体装置の側断面
図である。
１１・・・素子搭載用部品、１２・・・半導体素子、１
３・・・絶縁性基板、１４・・・導電性配線パターン、
１５・・・貫通孔、１６・・・ワイヤー、１７・・・樹
脂。
第１図FIG. 1 shows an embodiment of the semiconductor device of the present invention, (a
) is a side cross-sectional view showing a part taken out, la) is a side cross-sectional view of the whole, (c) is a side cross-sectional view for explaining the wiring method for applying pack bias voltage, and Fig. 2 is a side cross-sectional view of a conventional semiconductor device. FIG. 11... Element mounting component, 12... Semiconductor element, 1
3... Insulating substrate, 14... Conductive wiring pattern,
15...Through hole, 16...Wire, 17...Resin. Figure 1
Claims (1)
用部品内に半導体素子が搭載され、 （ｂ）その素子搭載用部品が絶縁性基板に形成された貫
通孔に嵌着され、 （ｃ）その嵌着された素子搭載用部品内の半導体素子の
表面の電極が絶縁性基板主表面上の導電性配線パターン
に金属細線により配線され、 （ｄ）その配線部と半導体素子部が樹脂で封止されてな
る半導体装置。[Claims] (a) A semiconductor element is mounted in an element mounting part formed to accommodate the semiconductor element, and (b) The element mounting part is mounted in a through hole formed in an insulating substrate. (c) the electrodes on the surface of the semiconductor element in the fitted element mounting component are wired with thin metal wires to the conductive wiring pattern on the main surface of the insulating substrate; (d) the wiring portion and A semiconductor device whose semiconductor element portion is sealed with resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61119082A JPS62276836A (en) | 1986-05-26 | 1986-05-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61119082A JPS62276836A (en) | 1986-05-26 | 1986-05-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62276836A true JPS62276836A (en) | 1987-12-01 |
Family
ID=14752433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61119082A Pending JPS62276836A (en) | 1986-05-26 | 1986-05-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62276836A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02119253A (en) * | 1988-10-28 | 1990-05-07 | Nec Corp | Hybrid integrated circuit device |
| US6833520B1 (en) | 2003-06-16 | 2004-12-21 | Agilent Technologies, Inc. | Suspended thin-film resistor |
-
1986
- 1986-05-26 JP JP61119082A patent/JPS62276836A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02119253A (en) * | 1988-10-28 | 1990-05-07 | Nec Corp | Hybrid integrated circuit device |
| US6833520B1 (en) | 2003-06-16 | 2004-12-21 | Agilent Technologies, Inc. | Suspended thin-film resistor |
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