JPS6227404B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a programmable logic controller,
In particular, the controller has a built-in storage device and a readout device for stored data, the storage device stores command words and 1-bit data words representing sample results, intermediate calculation results, or similar data, and the readout device stores these. This relates to a controller that reads and reproduces memory words for the next calculation. In the selected embodiment, a programmable logic controller constructed using a semiconductor IC circuit includes a memory device that stores multi-bit instruction words and 1-bit data words, and performs data processing on data according to the instruction words. and a processor selectively coupled to the storage device for processing. A one-bit word pushdown stack is selectively coupled to the processor for storing partial answers to the processor's calculations. Partial answers are read out from the bar switch circuit in the reverse order of input once the other parts have been calculated.
The other part's answer is combined with the partial answer reproduced from the push-down bar switch circuit. Although otherwise useful alone or in combination with the embodiments described above, a programmable logic controller is a sample for detecting the state of each of multiple conductors in a ladder relay network. has an input element. The output elements of the circuit network connect and disconnect power to equipment that uses power according to programmed commands stored in the controller's storage device to meet the operating conditions required for the ladder-type circuit network. satisfy. The sample device is sequentially 1
Generate Bitto language. This 1-bit word represents the state of each input element. A set of one bit is generated for each output element depending on the state of the input element, indicating one state of the output control state. A timing device operating on each half-cycle of the supply voltage initiates the generation and storage of a one-bit input word and output control status word in a semiconductor read/write image register. Additionally, the timing device includes a controller for sequentially setting a serial input/output (I/O) mode in which input elements are sampled and output states are read from registers. The mode applied to the output element is followed by a run mode in which a new set of control states is set and stored in a register. Viewed from one aspect, the present invention provides a programmable circuit that allows each conductor of a circuit corresponding to a ladder relay network, that is, a circuit corresponding to a rung of a ladder, to have a practically unlimited number of parallel circuits. It is related to the controller. Viewed from this particular aspect, the present invention relates to addressless, single-bit, push-down bar switch circuits and circuits connected thereto, which temporarily store intermediate results of calculations. This memory is retrieved for combination with the next calculation. Viewed from another aspect, the present invention provides a multi-element, multi-branch conductor of a ladder relay network that samples the state of input elements in such conductor and generates control status signals for output elements in the conductor. and in the process, a programmable logic control that stores a 1-bit flag code in a read/write image register built into the controller, thereby eliminating the need to store the flag code in the output device. It's about machines. Conventionally, multiple relay equipment has been used to set conditions for controlling machines powered by AC power. This installation is carried out in accordance with instructions provided by electrical wiring diagrams in the form commonly known as ladder networks. Several methods for solving problems that simplify the work of this equipment are described in Control Engineering (Control Engineering).
Engineering), September 1972 issue, pages 45 et seq. The present invention is in the field generally known as programmable logic controllers. Traditionally, programmable logic controllers have been used to control machines, processes, solenoid magnets, electric motors, etc. Such controllers typically had multiple output storage devices associated therewith. In the process of generating control status signals from a machine by a logic controller, it is necessary to temporarily store intermediate results of calculations. Traditionally, such intermediate results have been stored in output storage, but this mode of storage is wasteful and reduces the capacity of a given set of equipment. The reason is that in this mode a large number of available output storage devices are used. When the output temporary calculation result is written to the output storage device,
Unless significant amounts of electronics and wiring are provided to read out such outputs,
The results cannot be used for further calculations. Currently existing programmable controllers also tend to constrain the program to use only a small number of parallel circuits for each conductor of the ladder logic, ie, the circuit corresponding to the rung of the ladder. Because of the complexities typically encountered in such logical systems, this previously existing constraint imposed an unreasonable restriction. It was desired to be able to apply an unlimited number of parallel circuits to each conductor of a ladder relay network. The present invention overcomes this constraint in conventional systems.
This is done by using an addressless storage device in the form of a one-bit word wide push-down bar switch. This allows intermediate results of calculations to be temporarily stored. This intermediate result can then be retrieved for combination with other calculations. This operation works equally well for Boolean expressions that can be decomposed into groups of subexpressions. Each expression in the group of sub-expressions is computed and the result stored separately in a push-down bar switch circuit which is then retrieved and combined to obtain the final result of the Boolean expression. What is important in the present invention is the fact that the word length is only one bit. It is also important to note that the length of the push-down bar switch circuit, and therefore the number of bits that it can store, is virtually unlimited. More particularly, this aspect of the invention provides a storage device for storing multi-bit instruction words and one-bit data words, and selectively providing the storage device for processing the data words in accordance with the instruction words. A programmable logic controller constructed using a semiconductor IC (integrated circuit) unit including a processor unit coupled to a controller. In accordance with the present invention, a one-bit word wide push-down bar switch circuit is selectively coupled to the processor for storing intermediate results of Boolean type calculations. Next, a device is provided for reading out partial calculation results from the push-down rod-shaped switch circuit in the reverse order of input in response to completion of calculation of other portions. Next, a device is provided for combining the partial calculation results taken from the push-down bar switch circuit with other partial calculation results. In another aspect of the invention, relatively inexpensive storage is provided for temporary storage of intermediate calculation results in random access memory (RAM) present within the electronic architecture of the device. ing. Intermediate results of many calculations can be stored in such storage and not in the otherwise required output storage. By using RAM in parallel with output storage to store all output data, these output data are available for use in subsequent calculations. More particularly, this aspect of the invention provides a semiconductor read/write system in a programmable logic controller having input elements sampled to detect the state of each of multiple conductors of a ladder relay network. An image register is provided for the The controller also has output elements in the network that follow programmed commands stored in a memory within the controller to meet the operating conditions required by the ladder network. to connect or disconnect the power supply voltage to the power-using equipment. The system includes a sample device that sequentially generates one-bit long words each representing the state of each of the input elements. The system also includes a device for generating a 1-bit output control status word. One state word corresponds to each state of the output element determined by the state of the input element. The timing device operates every half cycle of the supply voltage to
Starts the operation of generating a bit configuration word and an output control status word and storing them in a register. In a further particular aspect, apparatus is provided for generating a flag code in the process of detecting an output control condition. A device is then provided to store this flag code in an image register and read it out on demand. The drawings will be explained in more detail below. The present invention will be described with respect to one embodiment of a programmable logic controller system, in which there are three separate units. The first unit is a controller, which is a programmable sequencer and has a set of command words stored in a memory device;
and a device for sequentially detecting input devices that serves to display the status of various input elements associated with the controlled device. The second unit is a programming device that first stores the desired command words in the sequencer and then causes the sequencer to operate unattended to control the desired set of operations in response to changing conditions. It is a device. Therefore, the programming keyboard is used for the start-up or initial programming of a given controller, and is then removed from the system and used only when the controller subsequently needs to change its operation. do not have. The third unit consists of a set of input and output equipment connected at various desired locations along a cable leading from the sequencer. Generally, 1
The output device or devices serve to connect the AC power source to electric motors, indicator light bulbs, solenoid magnets, and other similar power-using devices. The operation of the system is as follows. That is, the input equipment along the cable is probed for its condition at least once every half cycle of the supply voltage. The state of the input equipment is stored within the sequencer. Thereafter, the control state word preset by the operation of the sequencer is read out from the memory in the sequencer and sent via the cable to the memory of the output device, and if necessary changes the state of the output device, e.g. It is used to connect or disconnect the power to the motor. The set of command words stored in the sequencer's memory is then tracked and used to perform data processing on the input data obtained from the input unit and generate new output state words. By this means, the conditions of the output system are selectively changed at time intervals not longer than one cycle of the supply voltage. Applications of the invention are directed to improvements for implementing the part of a sequencer's operation in which flag codes are generated. In a more particular aspect, the invention provides a read/write system in which the intermediate results of sequencer operations are in the form of image registers.
It is intended for operation such that it is stored in write memory and thus can be utilized on demand at any time during the generation of an output status word. FIG. 1 shows a programmable logic controller 10 that includes a plug 398 and a multi-conductor cable 3.
99 to the I/O basic unit 400, and from there to the I/O basic unit 401 via a cable 399a, and from the unit 401, a cable 399b extends in the direction of arrow 402 and can be moved to an arbitrary position. It shows a state where it is connected to an additional I/O unit to be installed. The programmable controller 10 has a plug-in input unit 600.
A hard-wired, independent process sequencer and controller that is programmed from I/O base unit 400 has a plurality of connectors, shown as connector 409, to accommodate various circuit elements. I/O base unit 401 also has a plurality of connectors, shown as connectors 411 and 414. The connector is used, for example, to control the X/Y table 404. The electric motor 405 is connected to the table 4
04 in the direction of one axis, and the electric motor 406 drives the table 404 in the direction of the other axis. Limit switch 407 is arranged to operate upon physical contact with table 404. Motor 406 is connected by conductor 408 to output connector 409 on I/O base unit 400. switch 40
7 is connected to the I/O basic unit 401 by a conductor 410.
It is connected to the upper input connector 411. Push button switch 412 is connected to input connector 414 on unit 401 by conductor 413. Programmable controller 10 is used, for example, to energize motor 406 when switches 407 and 412 are both connected. Such operations are performed in response to control conditions stored in a storage device within unit 10. A storage device within unit 10 is loaded with the desired control state by input unit 600. In this embodiment, the I/O basic unit 400 has eight input connectors 400a and eight output connectors 4.
00b. Similarly, the I/O basic unit 401 has eight input connectors 401a and 8
The output connector 401b is provided with output connectors 401b. FIG. 2 This system operates in response to a command voltage state loaded in a command word consisting of a ladder type circuitry commonly used for wiring power control systems. For example, FIG. 2 shows a typical ladder network in which a limit switch 407 and a pushbutton switch 412 are connected in series between a motor 406 and power lines 415 and 416, which are Power cable 3 entering unit 400
Included in 97. Similarly, electric motor 405 is connected in series with similar control elements to power lines 415 and 4.
Connected between 16 and 16. The third circuit connected between power lines 415 and 416 is a series circuit of three parallel switches, a timer 417, and a control relay 418, and the timer is activated when any one switch is connected. In the embodiment of the invention described herein, element 409
256 output elements like , and elements 411 and 41
It is equipped with 256 input elements such as 4.
The system shown in FIG. 1 serves to store instructions for forming a number of paths in a ladder network. This embodiment can be expanded to include more elements in the system represented by the ladder network. This is accomplished through the unique use of a push-button switch circuit, which eliminates the need for addressing devices, to temporarily store intermediate results of programmed operations. This push-down switch circuit also works well for Boolean expressions, in which case the Boolean expression is decomposed into several sub-expressions, each of which is stored in the push-down switch circuit. and then combined to obtain the final result of the Boolean expression. Although only a simple ladder-type element is shown in Figure 2,
The system shown in Figure 1 allows the ladder network to have an almost unlimited number of ladder bars, and allows any one bar to contain an unlimited number of elements. It is flexible in what it can do. Next, the controller 10, the I/O basic unit 400,
401 and the structure used for the control module 600 will be described. In operation, plug 600b connects the desired ladder network to controller 60.
Used only when setting to 0. Thereafter, plug 600b is removed and unit 600 is available for use in programming additional controllers located elsewhere. Programmable Controller 10 - Figures 3-6 The programmable controller 10 shown in Figures 3-6 has the following notable operating parts. Counter Data Register - Figures 3 and 4 Units 12 and 15 serve as serial I/O counters when operating in serial I/O mode, and store instructions when operating in run mode. serve as a word. They operate in conjunction with image register 20 as explained in a later section. BIT AND INSTRUCTION WORD COUNTERS FIGS. 3-4 Units 36-38 serve as bit and instruction word counters for synchronizing and controlling the program order of operation of the units. Scan Cycle Counter - FIG. 3 Counter 35 serves to count the number of scan cycles completed to assist in timing operations necessary when a timing unit such as unit 417 of FIG. 2 is used. Processor - Figure 3 Units 61, 62, and 63 act as primary processor units. Unit 61 is a main decoder and processor ROM. unit 62
is the ROM for the timer, counter, and processor. Unit 63 is a timer counter status signal storage unit. Synchronization Latch - FIG. 3 Via the synchronization latch 11, a start pulse is transmitted to begin each cycle of the controller. Controller 10 typically operates in conjunction with equipment powered by 110 volts on power lines 415 and 416 in FIG. Controller 10
operates to complete one cycle of operation within the time limits of each half-cycle of the supply voltage. Synchronous latch 11
The input synchronizing pulse applied to the terminal 11e of the power supply voltage is generated at the peak value of each half-wave of the power supply voltage. Each time a synchronization pulse occurs, 407,
Signals indicating the status of all control elements of the ladder network, such as switches such as 412, are read into the controller via data input AND gate 17 and stored in image register 20. After data loading, newly generated control status signals are sent out from controller 10 via cable 399.
One circuit of cable 399 is connected to NAND gate 18 for data output. After that, storage devices 25 to 28 or 30 to 3 in FIG.
All three instruction words are examined and new output data is created. In this way, one synchronization is completed, and the controller waits for the power supply voltage to reach the next peak value and starts the next control cycle. The output data from gate 18 is stored in shift registers in units 400, 401, etc. of FIG. This shift register storage device, which is in the form of a dual output register, stores output data that sets the control conditions for a given period of time, as will be explained with reference to FIGS. 13 and 14. Remember. During such time, new output data is stored in other parts of the dual output register. Control is transferred from one half of the output register to the other each time the power supply voltage waveform crosses zero. Push-Down Bar Switch Circuit - FIG. 3 Unit 80 is a push-down bar switch circuit with a word width of 1 bit. The results of logic calculations performed in other parts of the controller are stored in this push-down bar switch circuit. The results can be retrieved at will in the opposite order in which they were stored. The length of the push-down bar switch circuit is practically unlimited, and no matter how large the number of calculation results becomes, as long as it is common sense, it is possible to cascade appropriate units. Therefore, it is possible to deal with this. Intermediate results during sequential operations can be retrieved from the push-down bar switch circuit for combination with the results of other sequential calculations. Memory Circuit Section - FIG. 5 The memory circuit section includes a RAM consisting of four RAM units 25-28 and a programmable ROM consisting of PROM units 30-33. Each RAM or 28 RAM unit has a capacity of 1024 bits and 10 input control lines, so only one bit is read at a time. PROM30
33 have 8 input control lines and can output 4 bits in parallel at 1 o'clock. Therefore, RAM units 25 to 28 store 256 16-bit instruction words.
can be memorized. The command word is the unit 600 when the NAND gate 24 is in a conductive state.
can be stored in the RAM units 25 to 28 using . Conductor 23 is a storage data input line and must be conductive for data flow to RAM units 25-28. Alternatively, the 256-word imperative is
It can be stored in PROM units 30-33. In Figure 5, RAM units 25 to 28
Both PROM units 30-33 are shown. RAM 25 and PROM 30 are actually connected for parallel operation and therefore occupy the same location in the system. One or the other is used, never both together. RAM26 and PROM3
1. RAM27 and PROM32, and RAM28 and
The same applies to PROM33. in this way,
Although FIG. 5 actually shows redundant devices, the embodiment described here uses only four storage units, which may be configured in any desired combination of RAM and ROM. Instructions stored in RAM units 25-28 are stored in RAM units 25-28 during the normal operation of inserting new instructions or modifying existing instructions.
This can be changed using unit 600.
In contrast, PROM units 30-33 are fixed and cannot be changed using unit 600. In the case of RAM units 25 to 28 and PROM units 30 to 33,
The instruction word is read out as 16 1-bit control states and read out serially through gate 34. Before describing the system in further detail, a brief general description of the desired operation will be provided. This system operates through three modes in sequence. That is, (a) standby mode, (b) serial input/output mode, and (c) operating mode. Standby mode: The system waits in a dormant state until the next peak of the 60Hz supply voltage occurs. When a peak occurs, a synchronization pulse is generated to begin the operation, and each cycle of operation is completed before the next peak occurs. Serial I/O mode: This mode is initiated by the appearance of a sync pulse. The serial input/output mode includes three separate stages. In the first stage, the states of all input units 407, 412 on units 400, 401 of FIG. 1 are read and stored in image register 20. In the particular embodiment described herein, image register 2
0 has a storage capacity of 1025 bits. image·
The input portion of register 20 is limited to 256 bits. Therefore, up to 256 types of input units can be provided, the states of which are read into the image register 20. In the second stage, a serial output operation is performed, whereby the image register 20
A serial output operation of 512 bits stored in the center of the memory occurs. The 512 central storage locations are used to store flags for internal use within the system and are available for use by external equipment requiring the use of such flags. Although the specific usage is not discussed here, storing such a flag is part of the operation, and reading it is part of the operation of the second stage. They are included in the serial input/output mode as intermediate stages. In the third stage, the last 256 bits of the image register 20 are read out and the cable 3 of FIG.
99 and stored in units 400, 401, etc. The information stored in the last 256 bits of register 20 is information that occurred during the previous cycle of operation, and more specifically, information that occurred during the previous mode of operation. Operating mode: In the operating mode, the command words stored in storage devices 25 to 28 and/or 30 to 33 are applied to input data stored in the first 256 bits of image register 20. Executed by the system. At this point, we note that each unit 400, 401, etc. contains one parallel-in serial-out shift register, with one bit for each input connection 411 associated with that unit. It is useful to understand this. A serial-in parallel-out shift register is also included and has one bit for the output connector 409 associated with that unit. Basic unit 40
The shift registers 0, 401, etc. are cascaded and during the serial input section of the serial input/output mode, the states of all input units 407, 412 are serially read into the image register 20 via cable 399. . In this way, image register 2
The bits stored in the first 256 positions in 0 represent the state of the control elements, such as switches 407 and 412 of FIG. 2, at the moment the serial input/output portion of the scan period occurs. At the end of the series input/output mode, the states assumed to be assumed by output units such as motors 405 and 406 are read into registers of the series input/parallel output type and transferred to the registers for application to the output units via the control device. is stored in Based on the above understanding, the details of the configuration of the system shown in FIGS. 3 to 6 and the operation thereof will be described below. CONTROLLER - FIGS. 3-4 NAND gate 11a of latch 11 is connected via conductor 81 to the clear input terminal of each of units 13-15 and to the input of "run" flip-flop 21. The pulses on conductor 81 are periodic enable pulses that initiate operation of the system at each peak of the supply voltage. The Q output of flip-flop 21 is connected via conductor 82 to each load input terminal of units 12-15 and to the control terminal of AND gate 17.
The Q output of unit 21 is connected via conductor 83 to the control terminal of AND gate 17a. Gates 17 and 17a are connected to the inputs of NOR gate 17b, whose output is connected to inverter 17c and
It is connected to the data input terminal of image register 20 via gate 17d. The data output terminal of the register 20 is connected to the input terminal A of the main decoder and processor ROM 61 via a conductor 84, and the output on the conductor 85 is fed back via the data input of the AND gate 17a, and at the same time is used as an operation instruction device here. That is, it is connected to the D input terminal of a D-type flip-flop 86 called AI. The Q output terminal of the AI flip-flop 86 is connected by a conductor 87 to the data input terminal of the push-down bar switch circuit 80 and to the input terminal B of the ROM 61. Regarding the "running" flip-flop 21, the Q output terminal is connected to the counter 36,
It is connected to the respective enable input terminals and clear input terminals of 37 and 38. The carry output terminal of counter 36 is connected to a second enable terminal of counter 37 via an AND gate 88, and its carry output is connected to a second enable terminal of counter 38 by conductor 89. Ru.
The carry output terminal of the counter 39 is connected to the NAND gate 9 via the exclusive OR gate 91.
0 second input. The exclusive OR gate 91 has a control line 92 from the flip-flop 93 in FIG.
It is a time gate for the length of time that any one of units 25-28 is written to. Nando
Gate 90 has a third input line 94 to which a control voltage from flip-flop 95 of FIG. 6 is applied to provide a "series input" gate pulse. NAND gate 90 is connected to the load terminal of counter 39. A NAND gate 21a is connected to the clear terminal of the counter 39 and the flip-flop 21.
A signal is given from Output lines K2, KQD, K3 or K14 are connected to RAM units 25 to 28 and PROM units 30 to 3.
This is a conductor included in the cable 40 that is led to the location No. 3. Output line K14 from counter 38
is connected to the clock input terminal of counter 35 via inverter 96. The output of inverter 96 is connected by parallel conductor 98 through inverter 97 to the two inputs of NAND gate 11d.
The output of NAND gate 11d is a "scan complete" signal which is provided to NAND gate 11b to reset latch 11 to receive the next synchronization pulse applied to input terminal 11e. Oscillator 50 is connected via conductor 51 to the clock input terminal of counter 39. Oscillator 50 is approximately 8mHz
It works. This is shown in more detail in FIG. Counter register units 12 to 15
The output lines from are shown as conductors B0 through B15 and are for 16-bit output. Conductors B0 through B7 are connected to the A0 through A7 inputs of image register 20 via exclusive OR gates 100 through 107, respectively. Exclusive
The second inputs of the OR gates 100-107 are connected to a conductor 108 which, when at a high potential, reverses the polarity of the address to the register 20. Each input terminal of units 12-15 receives a signal from a NAND gate 109. The state of conductors B8-B11 from register 13 is used for control timing operations as described below in connection with FIG. 11A. Conductors B12-B15 are connected to four input terminals E-H of ROM 61, respectively, to provide processor 61 with the desired "operation" code. ROM
61 has two terminals XX, which are enable terminals. Upper terminal X is NAND gate 120
The output is also connected to the enable terminal S/L (shift/load) of the 4-bit counter 63, and is connected by a conductor 121 to an inverter 122, which inverts the NAND gate 123. The clock input terminal of the push-down bar switch circuit 80 is connected to the clock input terminal of the push-down bar switch circuit 80.
A second enable terminal X12 of the ROM 61 is supplied with a signal from a "0" bit conductor 124. The data input terminal of ROM 61 is connected to the output of image register 20 via conductor 84.
Input conductor D receives a signal from counter 35 via carry line (CRY) 125. The B input terminal is the Q of the operation instruction device flip-flop 86.
It is connected to a conducting wire 87 led from the terminal. The C input terminal is connected to a conductor 127 from the output terminal of the push-down bar switch circuit 80. The processor ROM 61 has four output terminals Y1 to Y4: (i) the terminal Y1 is connected to the D input terminal of the operation indicator 86 and the AND gate 17a via the conductor 85; (ii) the terminal Y2 is connected to the D input terminal of the operation indicator 86 and the AND gate 17a; It is connected via conductor 128 to one input of each of NAND gates 123 and 129, and the output of NAND gate 129 is connected to the clock input terminal of operation indicator 86. NAND gates 123 and 129 are input from the output of NAND gate 131, and
A write pulse conductor 13 is connected to the input of the gate 131.
2 and “0” bit conductors 124; (iii) terminal Y3 is connected to AIQ (MCR or JUMP) conductor 133; (iv) terminal Y4 is connected to 4-bit counter 63 through increment line 134; is connected to input pin 6 of . ROM 62 has four output terminals Y1 through Y4: (i) terminal Y1 is connected to conductor 85 and thus in parallel with the Y1 output terminal of ROM 61;
(ii) Terminal Y2 of ROM 62 is connected to the data input terminal of register 12 via conductor 135; (iii) ROM
Terminal Y3 of 62 is the storage device write data conductor 2.
(iv) The terminal Y4 of the ROM 62 is connected to the D input terminal of the flip-flop 137, and the flip-flop 137 serves as a carry flip-flop for the processor 62. The Q output terminal of flip-flop 137 is ROM
It is connected to the D input terminal of 62. ROM62 A
A signal is applied to the input terminal from a conductor 138.
A signal is applied to the B input terminal of the ROM 62 from the BO output terminal of the register 15 as described above. ROM
A signal is given to the C input terminal of 62 from the WAF conductor 139. Input terminals H, G and E of ROM 62 are connected to output terminals A, B and C of counter 63, respectively. The counter outputs K4, K5 and K6 are connected to the F input terminal of the ROM62.
A signal resulting from the NAND logic performed by gate 136 is provided on EF conductor 140. counter 63
The D output terminal appears on D output conductor 141 and is led to the circuit of FIG. A signal is supplied to the enable terminal P of the counter 63 via a NAND gate 142, and one terminal of the NAND gate 142 is supplied with a signal from a ROM load conductor 143. The other input of NAND gate 142 is provided with a signal from external load conductor 144. External load conductor 144 is also connected to the enable terminal (CE) of image register 20. Gated clock conductor 110 is connected to register 1.
2-15, the clock input terminal of carry register 137, and the clock input terminal of counters 36-38. Write pulse conductor 132 is NAND gate 1
Connected to one of the three inputs of 09 and conductor 1
10. Storage devices 25 to 28 and/or 30
The data read from 33 to 33 is
Appears on storage read data conductor 146 which is connected to gate 147. The output of AND gate 147 is connected to NOR gate 148 and conductor 1.
49 to the input of AND gate 150. A second input of the AND gate 150 is given a signal from a NAND gate 151, and one input of the NAND gate 151 is given from the B output terminal of the counter 63. The other input of NAND gate 151 is provided from the A output terminal of counter 63 via inverter 152. The output of AND gate 150 is given to NOR gate 153,
The output of the NOR gate 153 is connected to the conductor 1 which is led to the A input terminal of the ROM 62 via the inverter 154.
38. The output of NAND gate 151 is also connected to one input of AND gate 156 via inverter 155. A second input to AND gate 156 is provided from output line 127 to push-down bar switch circuit 80. The output of AND gate 156 is connected to the second input of NOR gate 153. The delay line 157 of bit “0” is connected to counter 6.
Connected to terminal 2 of 3. Low supply voltage line 158 is NAND gate 18
NAND gate 18 is placed in the flow path of the data output of image register 20. A third input of NAND gate 18 is provided with a signal via start start conductor 159. Conductors A8 and A9 are connected to inputs 9 and 10 of image register 20. An image register gated write pulse (IRGWP) conductor 160 is connected to the R/W (read/write) input terminal of the image register 20. Serial data output conductor 165 is NAND gate 1
8 through an inverter 166. Counter output leads K3 to K14 are routed to the circuit of FIG. Register output conductor B0 to B1
1 is led into the circuit of FIG. 6 along with conductors K2 and (KQD). Conductors K0 and K1 are not used. NAND gate 166 provides a 1/0 clock signal on lead 167. The input of the NAND gate 166 is the Q output of the flip-flop 21 and the NAND gate 166.
A gated clock signal on lead 110 leading from gate 109. The output of flip-flop 21 is connected to inverter 1.
68 to a "run" lead 169 to program panel 600. The output of NAND gate 11b is inverter 17
0 to period enable conductor 171. As previously discussed, external load conductor 144 is connected to NAND gate 147. Conductor 144 is also connected to AND gate 17 via inverter 172.
Connected to 1 input of 3. and gate 173
The output of is connected to NOR gate 148. The second input of AND gate 173 has a program input.
A signal is provided from panel data input lead 174. FIG. 5 FIG. 5 shows the main memory of this system. It is the RAM unit 25 to 28 mentioned earlier.
It includes PROM units 30-33. Note again that only four units are used in this embodiment. The four are units 25 and 30,
Any combination of units 36 and 31, units 27 and 32, and units 28 and 33 may be used.
In some sets there are 4 units, units 25 to 28, in others 25 to 27 and 3 units.
3, and in other sets 25, 26, 3
2, 33 is fine, etc. Counter output leads K4-K14 are connected to address input terminals of storage units 25-28 and 30-33. Conductors K3 to K12 are connected to A0 to A of units 25 to 28.
Connected to 9 inputs. Conductors K5-K12 are connected to the A0-A7 address inputs of units 30-33. Conductors K13 and K14 are connected to the A and B inputs of data selector 175.
The selector 175 selects output lines 180 to 183.
The data selector 177 has an output line 185 for driving the PROM units 25 to 28, respectively.
It has 188 to 188. Units 175 and 177 form a single unit known as a demultiplexer. Multiplexer unit 190 connects conductors K3 and K4.
has inputs A and B respectively connected to. Units 30 to 33 each have four output conductors Y
1 to Y4. The output conductors Y1 through Y4 are connected to the inputs ICO through IC3 of multiplexer 190.
It is connected in parallel to four output busbars 191 guided by. A single output lead 192 leads to a flip-flop 193. The clock input terminal of flip-flop 193 receives a signal from conductor K2.
Output lead 194 of flip-flop 193 is connected to output gate 34, and the output of gate 34 is led to storage read data lead 146 via inverter 196 to storage read data lead 1.
Guided by 97. The data on lead 146 is used by sequential controller 10. The data on lead 197 is used by program panel 600. Data output lines 198 leading from all data output terminals of units 25 to 28 are NAND
Connected to a second input of gate 34. FIG. 6 FIG. 6 illustrates the logic elements used to create the control state signals and timing state signals for the operation of sequential controller 10, as previously described. The main control relay and jump unit 210 are 4
It includes bit counters 211 and 212. Conductors B0 through B3 (FIG. 4) from register 15 are connected to counter 211. Conductor B4 to B7
is connected as an input to counter 212. Counters 211 and 212 are reversible counters. The output of counter 211 is connected to the subtraction input terminal of counter 212. The output of counter 212 is connected to the clear input terminal of flip-flop 213 and the preset input terminal of flip-flop 214. The Q output terminal of flip-flop 213 is connected to the clock input terminal of flip-flop 214, one input terminal of NAND gate 215, and the load terminals of counters 211 and 212. The output terminal of flip-flop 213 is connected to one input of NAND gate 216;
Connected to the input terminal. flipflop 213
The output terminal of is also the counting output conductor 217. Conductor B14 is connected to the D input terminal of flip-flop 214. Cycle drive conductor 171 is connected to the clear terminals of counters 211 and 212. A sequencer output line 128 led from the Y2 terminal of the ROM 61 is connected to one input of a NAND gate 215 and one input of a NAND gate 218.
The second input of NAND gate 218 is provided from the Q output terminal of flip-flop 95. The Q output terminal of flip-flop 95 is connected to series input conductor 94.
give a signal to The clear input terminal of flip-flop 95 is provided with the end cycle signal on conductor 163, which is the output of NAND gate 21a in FIG. The MCR+JUMP (main control relay and jump) unit 210 connects the Q terminal of a flip-flop 213 that controls whether the system is operating in jump or MCR (main control relay) mode. It serves to provide an output signal. Flip-flop 213 indicates MCR or JMP (jump) mode, but flip-flop 214 indicates only JMP mode. When the Q output of flip-flop 214 is low, then the system is operating in jump mode. The Q output of flip-flop 214 is connected to one input of NAND gate 220, the output of gate 220 appearing on conductor 160. The clock input terminal of flip-flop 95 receives a signal from conductor B8. In this way, the MCR+JUMP unit 210 has counters 211 and 212, flip-flops 213 and 214, and flip-flop 9.
5 and gate 220 as its principal components to generate signals on conductors 160 and 217. Input conductor B8 is connected to one input of NAND gate 222 via inverter 221. The output of NAND gate 222 is NAND gate 223
gate 223 provides a second input of exclusive-or gate 203. Both NAND gates 222 and 223 and the second input of exclusive-or gate 202 are provided via conductor B11. A signal is applied to the third input terminal of the NAND gate 222 via the conductor B10, and the exclusive or
A second input to gate 203 is provided via conductor B9. Running conductor 82 is connected to one input of NAND gate 200. The output of NAND gate 200 is connected to "invert one" conductor 108 via inverter 201. A second input of NAND gate 200 is provided via conductor B8, which is connected to NAND gate 200 via an exclusive-or gate 202. Exclusive
The output of OR gate 202 appears on conductor A8. The signal on conductor A9 is exclusive or
It is made at the output point of gate 203 and is also connected as the third input of NAND gate 200. The circuit leading to WAF conductor 139 is and or
Invert gate 224, inverter 225,
Flip-flop 226 and inverter 227
including. This circuit serves to multiplex together the AIQ signal on lead 37 and the signal on lead B15. Conductor B15 is connected to the D input of flip-flop 226. Bit "0" pulse lead 126 is connected to the clock terminal of flip-flop 226. The D lead from counter 63 is connected to the input of inverter 227 and thence to the preset terminal of flip-flop 226. The Q output terminal of flip-flop 226 is connected to unit 22.
Connected to one AND gate of 4. The B output terminal from the counter 63 is connected to the inverter 225, and the output of the inverter 225 is connected to the unit 22.
4 and the second terminal of the first AND gate of unit 224.
AIQ conductor 87 is connected to the second AND
connected to the gate. The write pulse on conductor 145 is created using flip-flop 230, whose D input terminal is connected to the KQD conductor from counter 39, and whose clock terminal is connected to counter 39.
The K2 conductor from 9 is connected. The Q output terminal of flip-flop 230 is connected to write pulse conductor 145. The output terminal of flip-flop 230 is connected to a third input of NAND gate 220 and one input of NAND gate 231. nand gate 2
The output of 31 is a three-conductor wire 232 and is used in unit 600 of FIG. A conductor 233 leading from the carry output of counter 36 is connected to the D input terminal of flip-flop 237. A clock input terminal of flip-flop 237 receives a signal from gated clock output lead 110. The Q output of flip-flop 237 is NAND
It is connected to the second input terminal of gate 231. The inverter 23 is connected to the third input terminal of the gate 231.
The KQD output of the gate 39 is applied through the gate 8. Outputs A and B of unit 63 are used in conjunction with external load conductor 144 to generate the "RITED" signal on conductor 239 and the "ROM load" signal on conductor 143. Conductors A and B are exclusive or gate 240 and inverter 24
1 to a conducting wire 143. The output of inverter 241 is also connected to one input terminal of NAND gate 242, the second input of which is external load conductor 144. nand gate 24
The output of 2 is connected to 1 input of NAND gate 243, and the output of gate 243 is connected to “RITED” conductor 2.
It is 39. The output of NAND gate 243 is connected to the D input terminal of flip-flop 93 via conductor 239a. A signal from the Q output terminal of flip-flop 237 is applied to the clock input terminal of flip-flop 93. Flip Flop 93 Q
The output is conductor 92 and is connected to the second input of NAND gate 243. The output terminal of flip-flop 93 is the complement of the signal on conductor 92a. The Q output of flip-flop 237 appears on output lead 124. The signal on lead 124 is transferred to lead 15 using flip-flop 244.
7 as a delayed signal with bit "0". The D input terminal of flip-flop 244 is connected to the Q output terminal of flip-flop 237.
The clock input terminal of flip-flop 244 receives the signal on conductor K2 from counter 39. The Q output terminal of flip-flop 244 is connected to output conductor 157 and to the clock input terminal of flip-flop 213 via conductor 157a. In this system, this system and unit 10
Countermeasures have been taken in the event that the power supply to the operating elements controlled by the controller fails. The problem is block 2
Reference numeral 51 relates to a battery 250 which supplies power to the RAM storage power supply circuitry.
The RAM storage device is shown in Figure 5 as unit 25 or 2.
8. In the circuit shown in FIG. 6, the battery 250 is charged with a power source that obtains its voltage from an AC power source. The resulting charging current is supplied to terminal 252 and passes through transistor 253 to battery 250.
reach. This circuit means that if the AC power supply fails and the voltage of battery 250 is below a predetermined level, gate 18 in FIG. 4 will be blocked and data will not be read into units 400, 401, etc. All output elements such as units 400, 401 etc. are operated to be forced into a protected state until AC power is restored. The voltage of battery 250 is applied to conductor 25 within amplifier 254.
5 is compared with the reference voltage above. If the power supply fails, the voltage on conductor 255 will be zero. If the voltage on battery 250 is not above a predetermined level as indicated by the voltage on lead 255, then
The output on 55a is at a high potential, causing light emitting diode 256 to emit light and providing a low battery voltage signal. Conductor 255 is connected to one input of NAND gate 257, which together with gate 258 forms a latch. Output conductor 2 of latch 257, 258
59 connects the battery low conductor 158 through the gate 260.
connected to. The clear circuit power supply 261 is a Schmitt trigger.
It includes a NAND gate 262 , which is connected to a second input of NAND gate 258 via an inverter 263 . Schmitt Trigger 2
62 inputs are provided from terminal 264. Capacitor 265 is slowly charged when the failed power supply is restored. The charging current flows through resistor 266. The power supply 261 of the clear circuit sets the output terminal of the gate 258 to a high potential and turns off the transistor 253 to prevent the battery 250 from being temporarily charged or to determine whether the battery 250 has become useless. prevents the battery from charging at least long enough for the comparison to take place. If the battery fails, the system will not be allowed to operate automatically and unattended after system power is restored. The starting switch 270 is configured to ground the input of the inverter 271 or the input of the inverter 272 depending on its position. Inverter 2
When the input to 71 is grounded, the start start conductor 159
is also grounded. This will prevent data from passing through gate 18. switch 27
0 is in the other position, grounding the input to inverter 272, conductor 159 is at a high potential and serves to drive gate 18. Output lead 273 is a gated clock signal.
PPGC is provided to transmit the PPGC to unit 600 in FIG. Clock signal PPGC is obtained at the output of NAND gate 274, one input of gate 274 is connected to a terminal of flip-flop 93, and a second input terminal is connected to gated clock conductor 110 through inverter 275. .
The third input is the running lead 82. In this embodiment, the processor 61 is a ROM
It was explained as follows. The specific unit actually used was the H PROM 1-1024-5B, the characteristics of which are further shown below in Table 7. ROM 61 was programmed according to the table below.

【table】

【table】

【table】

【table】

【table】

【table】

【table】

【table】

[Table] The timer controller 62 is also a ROM. Later, the characteristics of H are further shown in Table 7.
PROM 1-1024-5B. ROM 62 was programmed as shown in Table 2.

【table】

【table】

【table】

【table】

【table】

【table】

【table】

[Table] In the above description, FIGS. 3 to 6 relate to the contents of the controller 10 of FIG. 1. Controller 10
are constructed to control output devices, such as electric motors 405, 406, in response to input devices, such as switches 407, 412 of FIG. Controller 1
The special requirements to be met by using 0 are solved by general purpose devices such as the ladder diagram of FIG. When the appropriate preset conditions are connected as shown in FIG.
0 to the memory of the controller 10. Programmer - Figure 1, Figure 1A, Figure 1B, Figure 7
FIGS. 10-10 Unit 600 of FIG. 1 is a small, portable keyboard input unit that includes four sets of keys. The first set 600c is numbers 0-9 and CLR
It is an 11 key set with a (clear) button. Also, the second set 600d is INS (insertion),
WRT (write), INC (increment) and
This is a set of four keys shown as READ buttons. The third set 600e is a four key set, three of which are IN-X, OUT-Y and
Used as a CR (control relay) button. The fourth set 600f is ST (start or accumulation period), CTR (counter), TMR (timer), MCR (master control relay), OUT (output), INV (inversion or negation), OR and AVD.
It is a set of 8 keys including buttons. In combination with this keyboard is used an array 600g of Ksegment, which is commonly used in portable computers and has neon numeric displays. A light emitting diode (LED) 600h is used as an indicator for each key in the fourth set 600f. Further, one light emitting diode (LED) 600j is used for each of the keys X, Y, and CR, and one light emitting diode (LED) 600j is used for a place where there is no key. 1st
The programmer 600 shown is adapted to operate in a mode arbitrarily selected from five different modes. This mode is the second set 600
The selection is made by pressing down on any one of the four buttons d or the CLR (clear) button of the first set 600c. 1st set 600c
When the CLR button is pressed down, it clears the registers and storage unit and then the second set 6
Indicates that one of the functions of 00d is ready to be executed. In the read mode, the instructions in the memory of FIG. 5 are read. This operation is first performed by entering via the keyboard the address in memory of the instruction to be read, ie 0 to 255. After this, when the READ key is pressed down, this instruction will appear on the display,
Appropriate LED elements of sets 600h and 600j emit light. In incremental mode, addresses entered into unit 600 by the keyboard and not cleared are incremented by one fumactor by depressing the INC button.
For example, if the button of the first set 600c is pressed down and then the INC button of the second set 600d is pressed down, the address that will act on the machine at this time will be address No. 1. However, if the address displayed on the display 600g is 250
251 by pressing down the INC button.
Increment to . The memory address that operates at a given time is shown in the right four digits of the display 600g. In write mode, the desired new instructions are written to memory. The new instruction is written over the previous instruction if the previous instruction has been written to the desired location in memory. In the insert function, a new instruction is inserted at any point in memory.
When the INS button is pressed down, the next instruction stored in memory is shifted to a higher memory location. For example, in the ladder diagram section of Fig. 2, if the electric motor 405
A ladder rung containing memory occupies memory locations 100, 101, 102 and includes motor 40.
If it is desired to insert a rung containing 6 at the beginning of memory at memory location 100, the following operations are performed using programmer 600. Step 1: Press down on the CLR (clear) button. Step 2: Enter the address, ie press down on button 100. Step 3: ST (Start-Store) and X
Press down the (in) button. Step 4: Switch 407 sets I/O address No.
Since the number "9" is occupied, the button (key 9) corresponding to the number "9" of the first set 600c is pressed down. This places switch 407 in memory location 100. Step 6: Press down on the INC button. Step 7: Press down the AND button on Set 600f. Step 8: Press down key X of set 600e. Step 9: Switch 412 sets I/O address 16
, so press down on keys 1 and 6 of the first set. Step 10: Press down the key INS of the second set 600d. This sets switch 407 at storage location 100. Step 11: Press down the INC button on the second set 600d. Step 12: Press down the OUT button on the set 600f. Step 13: Press down the Y button on the set 600e. Step 14: Since the electric motor 406 occupies I/O address 8, press down the number "8" button (key 8) of the first set 600c. Step 15: Press down the INS button on the second set 600d. This brings motor 406 into memory location 102 in conjunction with switches 407 and 412. The elements of the second rung are at memory address 100,1
01,102 is already occupied. When the switch 407 is turned on in the memory, all the elements in the memory are set to 1.
Shift only the memory address. switch 412
and each time the motor 406 is inserted into the memory. This causes the rung elements including motor 405 to move to new memory locations 103, 104, 105.
to occupy. The push button shown in FIG. 1 actuates a switch connected to the circuit shown in FIGS. 1A and 1B. In Figure 1A, 8
Lines 0-7 of the book are guided by the keyboard. 4
Book lines KBD2, KBD3, KBD6 and KBD7 are derived from the keyboard. A pushbutton switch is connected to the matrix and provides a coded output on four lines led from the keyboard. All switches in the first set 600c (excluding switch CLR), set 600e and set 600f are included in the X-Y matrix of FIG. 1A as shown by legend. 1st
When the number "0" button (switch 0) on the keyboard 600c in the figure is pressed down, a connection is established between line MO and line KBD2 in FIG. 1A.
Note that switch MCR and switch INV have the same functions. That is, when these switches are closed, input line M4 and output line KBD7 are connected. In FIG. 7, unit 600 has lines 0-7 led to the keyboard as shown in FIG. 1A.
has. Lines KBD2, KBD3 in FIG. 6 and lines KBD6, KBD7 in FIG. 9 are derived from the keyboard. The circuit shown in FIGS. 7-10 has two main data loops that are responsive to commands entered by the keyboard. These two data loops will first be described generally before discussing the use of the keyboard of FIGS. 1, 1A, and 1B. The first data loop is derived from sequencer 10 of FIGS. 3 and 4 via Schmitt trigger 601 of FIG. 9 and includes shift registers 602-606 of FIGS. 9 and 10. As shift registers 604 to 606 operate, binary up/down occurs.
Down counters 607 to 609 are each operating. The output of the first data loop is routed via inverter 610 to line 174 and then to sequencer 10. Signal or data type information sent from unit 600 to sequencer 10 must be sent to line 174 via shift registers 604-606. The second data loop is a binary coded decimal (BCD) loop and is a numeric data loop that accommodates 32 bits. The first 16 bits are then stored in shift registers 612 and 613 in FIG. second 16
The bits are in shift registers 614 to 61 in Figure 10.
7 is stored. The loop through which the data flows has input lines connected to the A and B (NAND) input terminals of shift register 612. The data bits are clocked in sequence through registers 612-617 and returned to line 618 by output line 619, NAND gate 620 and NAND gate 621. The numerical data input from the keyboard of the unit 600 is passed through the loop 612 to 612 by the shift register 622.
621. Four lines 623 are led to shift register 622. The state of line 623 is low speed clock (LSC) oscillator 626.
It is controlled by counters 624 and 625 driven by. A clock (oscillator) 626 is free running in proportion to the clock 50 of the sequencer 10. A second oscillator is provided with oscillator 626, which is a high speed clock (HSC) oscillator 626a. These oscillators operate at frequencies of approximately 180KHz and 1.8MHz, respectively. Oscillator (LSC) output line 627 is routed to the clock input terminal of counter 624. The QD output terminal of counter 624 is led by line 628 to the clock input terminal of counter 625. Counters 624 and 625 are decoder 630,
631 and thus decoder 6
The output of 30 scans the switches on the keyboard. The output state on line 633 derived from decoder 631 strobes display 600g and outputs the keyboard, i.e. output line W2,
Strobe W3, W6 and W7. Lines 0-7 of FIG. 1A correspond to line 632 of FIG. 7. Line KBD2 from the keyboard is NOR gate 6
The second input of this NOR gate 634 is connected to the conductor W2 from set 633. Similarly, keyboard line KBD3 is routed to NOR gate 635, whose second input is connected to line W6. Line KBD7 is also led to NOR gate 637, the second input of which is connected to line W7. Gates 634 and 635 provide inputs to NOR gate 638. Gates 636 and 637 also provide inputs to NOR gate 639. NOR gate 63
The output of 8 is provided to a monopulse circuit 640 to produce a -digit pulse on output line 641. This digit pulse is applied to the clock input terminal of register 622, which is connected to line 6.
23 Enter the code above. This code represents the number of keys pressed down on the keyboard. Decoder 6
Pulses from clock oscillator 626 provided by counter 624 via 30 provide the keyboard strobe sequence. Line M0
is initially at a low level, then lines M1...M7 sequentially go low, line M0 goes low again, and the cycle repeats. Gating the code on line 623 into register 622 is controlled by pressing down on a key on the keyboard. The special code on line 623 is one that appears at the moment a special pulse occurs in response to pressing down a given key.
The keyboard described above operates on the TI2500, manufactured and sold by Texas Instruments, Inc. of Dallas, Texas.
It is essentially the same as a pocket calculator. Therefore, keys 0-9 of the first set 600c
Activation of either causes register 622 to contain a binary code representing the selected digit "0" through "9". At this time, the selected number entered in register 622 is inserted into the BCD loop, and eventually register 604
~606. Except for some cases described below, the data placed in registers 604-606 is the I/O address of a given connector element located along cable 399. Recall that in the embodiment described above there are 256 input addresses and 256 output addresses along cable 399. In the unit 400, the first
The first eight units 400a are input units, and the second eight units 400b are output units.
As mentioned above, the I/O address is
6. Indicates the address of the connector unit used to connect to switch 407, switch 412, etc., respectively. Also, the programmer unit 600 has a set 600.
The selected item can be turned on by operating the f switch.
The OP code is now encoded.
Unit 600 also makes a request by actuating one of the keys in set 600e. Indicates an I/O address modifier. This circuit operates to store the OP code in register 602 and the I/O address modifier in register 603. Also registers 602, 6
The circuit combined with the 03 can be used to manually insert the desired OP code or multiple codes, or when entering a given set data representing a ladder network or set data already entered into the system. Inserted to give operators elasticity when changing
One or all of the OP codes can be removed. Specifically, upon actuation of a key to energize either line KBD6 or KBD7, the data on line 650 is decoded into registers 602 and 603. Logic circuitry within dotted line 651 decodes the data from line 650 into binary form for storing the data in registers 602 and 603. The codes stored in such registers are shown in FIGS. 1, 1A and 1B and associated with lines KBD6, KBD7.
Represents a code. The state appearing at the output of the gate of unit 651 is shown in the table.

【table】

[Table] The output status of the table is as follows. Set 6
Line W7 led from 33 is NAND gate 65
It is connected to one input terminal of AND gate 651b. Line W6 led from set 633 is connected to one input terminal of AND gate 651c and one input terminal of AND gate 651e. At this time, the three least significant bit lines of line 623 are connected to circuit 651.
Further, the QA output terminal of the counter 625 is connected to a second input terminal of a NAND gate 651a and a second input terminal of an AND gate 651c via an inverter 651h. The QD output terminal of the counter 624 is
It is connected to a second input terminal of AND gate 651d and one input terminal of AND gate 651f.
The output terminal of the NAND gate 651a is the AND gate 6
51d, and further connected to AND gates 651f and 65 via an inverter 651j.
It is connected to each input terminal of 1g. counter 62
The QC output terminal of No. 4 is connected to the second input terminal of AND gate 651e and the second input terminal of AND gate 651g. The output terminals of AND gates 651b to 651g are connected to one input terminal of exclusive OR gates 651m to 651s, respectively. QA to QD outputs of shift register 602 are exclusive
It is supplied to the second input terminals of OR gates 651m to 651q, respectively. Also, the shift register 60
The QA and QB outputs of No. 3 are supplied to the second input terminals of exclusive OR gates 651r and 651s. The data stored in the shift register 602 is
This is an OP code. There are 16 OP codes used in this example, and these are shown in the table.

【table】

[Table] The data accumulated in the shift register 603 is
It is an O address change electron. The three variable electrons used here are shown in the table. Table Keys 651r 651s X 0 1 Y 1 0 CR 1 1 All OP codes shown in the table can be selected by actuating the set 600f key in FIG. As you may have noticed, some of the OP codes include entries made by depressing two of the SET 600f keys, and some include entries made by depressing three of the SET 600f keys. Exclusive OR Gate 651m~651
Examination of the circuit containing q shows that if register 602 is cleared, any OP code appearing at the output of unit 651 will be placed in register 602. However, if the same OP code button is pressed down a second time, the OP code previously placed in register 602 is erased by feedback through channel 602a. The circuit therefore loads the selected bits into the register 602 or erases them bit by bit without modifying the operation of the program unit 600 in any case. For example, in Figure 1,
The operator turns on switch 412 and AND
Suppose you accidentally try to press the OR button instead of the OR button at step 7 of the sequence mentioned in the example given earlier. If at this time the operator realizes that he has made a mistake and wants to correct it, he can easily do so by depressing the OR button again and then depressing the AND button. This sequence operation changes the code in register 602 from 1010 to 1000. This circuit therefore allows single bits to be selectively inserted or removed to change the code. The exclusive OR gates 651m to 651q insert or erase the code given from the register by repeating this special sequence operation, that is, the insertion of the same input command. The same goes for unit 651's Kate 651f,
The same can be said of the three lines leading to 651g. These are exclusive OR gates 651
r, 651s to control the LED display 600j. At the same time, line 603a connects exclusive OR gates 651f and 651 to selectively control the data in register 603.
Feedback is provided to s. The output of the shift register 602 is returned to the exclusive OR gates 651m to 651q.
Used to control the LED display 600h. When a given button of set 600f from the circuit shown is pressed down, the corresponding light emitting diode (LED) in the display will illuminate. The diode in set 600h in Figure 9 is the first
Similarly, the light emitting diodes X, Y, CR of display 600j shown in FIG. Logic circuit 652 includes registers 602 and 60
It operates similarly to the circuit 640 that controls input to 3. Note that the DIGIT CLOCK line appears as one of the outputs from circuit 640. This means that the digit code is in register 6.
22, and are stored in registers 612 to 617.
indicates that it should be inserted into a data loop that is clocked via This operation is initiated by providing a signal to the load input terminal of state counter 653 and to the clock input terminal of counter 653 via AND gate 654. The counter 653 outputs 5 pulses.
Output lines QA to QD of this counter 653 are connected to terminals A, B, C, STRB of a data selector unit 655 and an input line of a decoder 656. Since the output from counter 653 is preset to 5, data selector 655 selects the signal on line 657 leading from NOR gate 658 via inverter 659. The 32-bit word is cycled through a second loop comprising shift registers 612-617, which is accomplished by being successively shifted by clock pulses. This clock pulse is applied to the clock inputs of shift registers 612 and 613, and is further applied by NOR gate 660 to the clock inputs of shift registers 614-617. When a 4-bit word is stored in shift register 622, the purpose is to insert it into the correct location of the 32-bit words already circulating in shift registers 612-617. decoder 656
The operation of bit counter 653 and data selector 655 connected to is delayed until the correct time for insertion occurs. It is determined by the delay interval when the time data selector 655 is in state "5". When the state of data selector 656 becomes "6", NAND gate 661 is driven to open the gate and insert the word stored in register 622 into the input of storage register 612 via output line QD from register 622. The data on line 619 then passes through register 622 with the word from register 622 being inserted into the loop. Register 622 is therefore included in the 16-bit second data loop. NOR gate 66 while state "6" is issued from decoder 656
3 is opening the gate. For this signal MOW4
is present, which indicates a load condition on line 665 via NOR gate 664. This line 665 is connected to load input terminals of binary coded decimal up/down counters 666-669. These counters 666~
669 are shift registers 617 to 614, respectively.
are connected to each. In addition, line 665 is connected to binary counters 607 to 607 by inverter 655a.
It extends to the CLEAR terminal of 609. The 16-bit data word is therefore input to shift registers 666-669 and counters 609-6.
It is converted into a corresponding binary signal generated at 07. When the state of decoder 656 becomes "7", the high speed clock HSC provided by NAND gate 670 in conjunction with this state causes AND gate 671 to be
is driven to open the gate. This AND gate 6
71 works in OR Humanity, at this time
A HSC pulse is generated on the clock line. Also, at this time, line 672 is connected to the down input terminal of counter 666 and the up input terminal of counter 609. and counters 666-669
counts down to zero. During the same time, counters 609-607 count map. The moment counter 669 counts zero, a borrow signal appears on line 673 and is sent to NOR gate 674. This NOR
Gate 674 effectively performs an AND operation in state "7" and registers 604-6 by line 675.
A load pulse is supplied to each load terminal of 06. Also, at the moment when a borrow pulse occurs, the counters 607 to 60
The contents of 9 are immediately stored in storage registers 604-606 and used to read out via line 611 to the sequencer. During operation, the sequencer shown in FIGS. 3 to 6, once set during operation, enters the wait-serial I/O operation mode (wait-) according to each peak of the AC power supply.
serial I/O-run modes). When programmer 600 is connected and used in a system, sequencer operation is normally continuous; however, when the programmer of FIGS.
66-669. At this time, these counters count down to zero. Once at zero, the channels from NAND gate 601 and in particular the drive terminals of registers 602, 603, 604, 605 and 606 are energized and counter 66
The word stored in memory at the address location originally designated 6-669 is fetched and stored in shift registers 602-606. and soon
LED displays 600h and 600j are energized to display the contents of registers 602 and 603. The contents of registers 604-606 consist of I/O addresses stored in main memory locations specified by the user. Therefore these registers 6
The I/O addresses included in 04-606 are then entered into counters 607-609. Counters 607-609 count down to zero when counters 666-669 count up. When counters 607-609 reach zero, counters 666-669 stop counting. At this time, the output of the counter is the shift register 614~
617 and this output is displayed. In particular, the I/O address consists of 16 of the 32 bits that circulate through the BCD loop. 4 out of 16 bits
Each set of bits is latched by a latch 690, the output of which is provided to a decoder 691. At this time, decoder 691 is selectively connected to energize the segment driver. One of these segment drivers is illustrated by circuit 692. The 16 bits are used to display the left four digits of the 600g display. The remaining 16 bits are decoded to display the memory address in the right four digits. In insert mode, the operator enters the desired data as shown above. The OP code can be stored in register 602. Modification data is in shift register 603
is memorized. The I/O address is put into a BCD loop. At this time, the data is transferred to shift registers 604-606. In run mode, once the selected address is obtained, data from memory begins to flow to register 602 as data from register 606 begins to flow to memory. Data in memory is passed through registers 602-606 in serial form until all memory addresses have been read and rewritten to memory shifted one memory address. The numerical data entry, OP code entry, and I/O address modifier have been explained. Next are the five programmer mode commands.
CLEAR, READ, WRITE, INSERT,
Explain the behavior including INCREMENT entries. First, when the CLEAR pushbutton in Figure 1 is pressed down, the CLEAR PB line in Figure 9 is grounded. This line is connected to an AND gate 900, and the output of this AND gate 900 becomes a signal. Also, this output terminal is connected to AND gate 901 and registers 612 and 613.
Connected to the CLEAR terminal. The output of this AND gate 901 is the output of registers 602 to 606.
CLEAR terminal and registers 614 to 617
Connected to the CLEAR terminal. When the read button is pressed down, line 9
02 is grounded. Line 902 is led to a NAND gate 903, the output of which is connected to a multivibrator 904, which prevents a single entry from having too many entries. Especially when the push button is pressed down, the switch is closed several times. The circuit including the flip-flop 904 is a NOR gate 9
This results in a debouncing circuit with an output of 0.05. Line 906 delays the signal and this signal passes through gate 905 gate not before multivibrator 904 has completed its cycle. At this time gate 9
The output of NAND gate 907 is supplied to one input terminal of NAND gate 907, and the output terminal of NAND gate 907 is connected to input terminal "0" of multiplexer 655. The second input of gate 907 is AND gate 9
08, this AND gate has as its inputs the MIWO line from FIG. 7 and the OEN signal. The INSERT pushbutton and the WRITE pushbutton are connected to gate 903 and gate 90
7 further leads to the input terminal “0” of the multiplexer 655. In addition to being connected to gate 903, the WRITE pushbutton is also connected by line 911 to gate 909 and the CLEAR input of D-type flip-flop 910. WRITE button is gate 90
3 and gate 909. The three lines RUN, PPGC and CPU3 are the third
The sequencer shown in FIGS. 6 to 6 is connected to a program panel 600. The RUN line is connected by inverter 913 to the clock input terminal of D flip-flop 910 and to gate 914. The Q output of flip-flop 910 is connected by an inverter 915 to the clock input terminal of B flip-flop 916. Also, the output of gate 909 is the output of flip-flop 916.
It is connected to the CLEAR terminal and one input terminal of NAND gate 917. The output terminal of the NAND gate 917 is an external load line 918 led to the sequencer.
It is connected to the. Also this NAND gate 917
The output terminal of is connected to a NAND gate 919, and further connected to a NAND gate 920 via this NAND gate.
It is connected to the. The PPGC line led from the sequencer 10 is connected to one input terminal of a gate 920 by an inverter 921. As previously mentioned, 3 is connected by line 232 to input "3" of multiplexer 655. Further, this 3 is connected to a NAND gate 922 and a NOR gate 923. The output terminal of flip-flop 916 is NAND gate 9
The second input to NAND gate 917 is connected to the input terminal of NAND gate 917. flipflop 910
The Q output of is connected to the input terminal of NAND gate 917 as the third input to NAND gate 917. The output of NAND gate 917 is a key signal communicating between sequencer 10 and programmer 600. In particular, the state of line 918 controls whether sequencer 10 receives data from programmer 600 appearing on line 174. In READ mode, line 918 is always high. In WRITE mode, the state of line 918 is 16
It is low only during the time that a single word of bits is being read from registers 602-606 to sequencer 10 via line 174. In the INSERT mode, line 918 remains high until counters 666-669 count one and a START signal corresponding to three addresses of memory occurs when it is desired to insert a new instruction. At that moment, line 918 goes low and the data from registers 602-607 is read out until the end of the cycle, i.e., the entire remainder of the instruction from memory is read through registers 602-606 and back into memory. sequencer 10 via line 174 until
flows to When the WRITE button is depressed, the CLEAR line to flip-flop 910 goes low and the CLEAR line to flip-flop 916 goes high. Each time the sequencer enters RUN mode, an input is provided to the clock terminal of flip-flop 910 and the Q output is clocked the same as the D input or is driven low.
Therefore, when the WRITE button is pressed down,
The output of flip 910 is output to multiplexer 656.
It remains low until the 2Y3 output goes low. This resets flip-flop 910. That is, the Q output is set to a high level. When the preset pulse is removed, the Q
The output will be at a low level. At this moment flip-flop 916 is clocked via inverter 915 and the output goes to the zero state. The output of gate 917 will be low if all inputs are only high. Therefore, in WRITE mode, the output of gate 917 is output from flip-flop 91.
Preset input to 0 or multiplexer 6
It goes low only during the time that the 2Y3 output of 56 goes low. The circuit including flip-flops 910, 916, NAND gate 909, and demultiplexer 656 is stuck in NSERT mode and the 2Y3 output of demultiplexer 656 goes low, keeping line 918 low until the end of the run cycle. Line 918 is connected to the CLEAR terminal of counter 653 through NOR gate 930 and NOR gate 931. The second input of gate 930 is the 2Y3 output of multiplexer 656. A second input of NOR gate 931 is provided by NAND gate 932. One input of gate 932 is the 1Y3 output of demultiplexer 656. A circuit containing a NAND gate resets counter 653 at the end of the 2Y3 state in INSERT mode and at the end of the 1Y0 state in READ or WRITE mode. At the end of the number entry mode, counter 653 is reset in response to the 1Y3 condition. When the INC button is pressed down, the input end of the Schmitt trigger 940 is grounded. This starts the operation of incrementing any addresses circulating in the BCD loop. The output terminal of the Schmitt trigger 940 is connected to a NAND gate 941 and a second NAND gate 942, and further connected to the CLEAR terminals of D flip-flops 943 and 944. The output terminal of gate 941 is connected to the clock input terminal of flip-flop 943. The Q output of flip-flop 943 is connected by gate 945 to the clock input terminal of flip-flop 944. gate 94
The output terminal of 1 is connected to the input terminal of the AND gate by an inverter 946 and a NAND gate 947. The output terminal of flip-flop 943 is
It is connected to one input terminal of OR gate 949 and a second input terminal of NAND gate 947. gate 9
The Q output of 44 is connected to the second input of NOR gate 949. Output end is NAND gate 94
2 is connected to the second input terminal of . The output terminal of NOR gate 949 is connected to one input terminal of NOR gate 950, and the second input terminal of this NOR gate 950 is connected to multiplexer 656 by inverter 952.
is supplied by a NAND gate 951 driven by the 2Y0 output of . The timing signal MOWO output line from FIG. 7 is connected to the second input to the gates 945, 951. The address given during operation is BCD loop 6
I would like you to remember that it circulates between 12 and 617. If it is desired to increment the address by one fmactor, then the INC button is depressed. This removes the CLEAR signal from flip-flops 943 and 944. OEN via gate 942
The (zero evable) signal is turned off and has no effect on gate 908. Gate 941 is also driven. This gate 941 has one of its inputs fed by a gate 955 whose input is fed by an inverter 956 having the 2Y0 state of multiplexer 656 and the MOW4 state from FIG. If the operations including multiplexer 655, counter 653 and multiplexer 656 are in the ZERO state and the MOW4 condition occurs, the output of gate 941 will go low and go high in response to and in accordance with MZOW4. This causes the flip-flop 943 to set the Q output to a high level and the level to a low level. Therefore, gate 945 is driven and gate 947 is not driven. The output of gate 945 then clocks the flip-flop when condition MOW4 from FIG. 7 occurs. The first signal sent out from gate 941
The pulse causes the output of gate 947 to go low and AND gate 948 causes counter 6 to
66 and is incremented at the moment it matches the address stored in registers 666 to 669. At the same time, this signal
Registers 614 to 6 using AND gate 901
Clear 17. Before the INC button was pressed, gate 942 was enabled to output, allowing the counter system to continue its cycle through 908. Then, when the INC button is pressed, gate 9
42 is disabled and the counter system does not continue to function until the increment operation is complete. When the MOWO signal is applied to flip-flop 944, the output of gate 942 is re-enabled, allowing counter 653 to perform its operation. Timing (FIGS. 11A-C) FIG. 11A shows certain timing functions used in the system described above. The functions shown in FIG. 11A are numbered similarly to those found in FIGS. 2-6. As mentioned above, the sequencer 10 operates in three modes: (a) wait, (b) serial I/O
(serial I/O) and (c) run (ruu). In FIG. 11A, waveform 80
0 is the sync applied to line 11e in FIG.
This shows the pulse. sync pulse waveform 80
0 is characterized by step 800a appearing at the peak of the ac voltage cycle. In accordance with step 800a, the sequencer 10
serial I/O mode is started. The enabling waveform 801 for this cycle is generated at the output of NAND gate 11a and appears on line 81, as seen in FIG. Waveform k2 is one of the outputs of counter 39 and is a pulse train with a pulse rate of 1 megacycle. In the embodiment described herein, the oscillator 50 shown in FIG. 4 was of a frequency of 8 megacycles. counter 39
The frequency of the output K0 was 4 megacycles.
The frequency of output K1 is 2 megacycles, but outputs K0 and K1 are labeled in the drawing.
is not used in the operation of the system, but merely in counter 39. In this way, waveform 802 becomes a 1 megacycle main control pulse K2. Waveform 803 is the KQD signal that appears at the final output of counter 39. During the sequencer's serial I/O mode, this signal is half the frequency of K2,
That is, it occurs at a pulse rate of 1/2 megacycle. After that, this signal is 16 of K2
one pulse for every 803 pulses.
output pulses such as a, 803b, etc. appear. Thus, waveform 803 is at a rate of 1/2 megacycle during I/O mode and 1/1 of 1/2 megacycle during the beginning of run mode.
6 and reverts to a 1/2 megacycle pulse rate during writes to main memory in run mode. In FIG. 11A, the serial I/O condition begins when waveform 801 goes high. Serial I/O status is interval 8
It ends at the end of 04. Run mode begins at the end of interval 804 and extends to the end of interval 805. Waveform 806 is the image register write pulse and is applied to the R/W terminal of image register 20 in FIG. Waveform 807 is NAND gate 1 in FIG.
This is the gate output signal appearing at the output of 09.
Thus, data registers 13-15 are
During the O mode, counting is performed continuously. While waveform 806 is valid, cable 39
The states of the 256 input units on 9 are 0,
Image register 2 in the order of 1, 2...254, 255
Reads to 0. At the end of a serial input operation in I/O mode, 512 flag states are read from image register 20. These include signal K2 shown in waveform 802.
Read at a higher clock rate. These are read out in the order of 0, 1, 2...510, 511. Thereafter, the state of line 108 in FIG. 3 is reversed so that the output data stored in image register 20 is read in the opposite direction. Thus, at the end of the serial I/O cycle, the states imposed on the 256 output units on cable 399 will be read out in reverse order. That is, in cable 399, the state of the output unit that is far away is first read out. These are at high clock rates, such as signal K2 shown in waveform 802.
255, 254... are read out in the order of 1 and 0. At this point, the I/O state ends and the system transitions to Run mode of operation. The first part of the run mode, interval 810, is
A main signal such as signal K2 shown in waveform 802
It is used to read instructions from memory into data registers 12-15 at the clock rate. At the same time, a corresponding train of K2 rate PPGC, represented by waveform 811, is generated, which is a program panel gated clock pulse train. Thus, the program panel in FIG. 1 is the only element in the system that uses waveform 811. During interval 810, one memory word containing 16 digits is read from main memory into the data register. During interval 812, instructions are executed by sequencer 10. Waveform 813 corresponds to (+),
This appears at terminal Y3 of processor 61. Waveform 814 corresponds to signal +, which appears at terminal Y2 of processor 61. At interval 815, the next word is read from memory and at interval 816
In , the next word is executed. Thus, words 0 and 1 are read from memory and an operation is performed on them. If all goes well, the sequencer will continue to read and execute all instructions in memory. In the example given in FIG. 11, the memory,
A single stop in the sequence is shown.
Specifically, after word 2 has been executed, step waveform 820 is generated and data register 1 is
2-15 is an external memory, that is, a programming memory.
Loaded from memory within unit 600. Waveform 820 appears on line 144 in FIG. If this waveform is present, the next word read into data registers 12-15 is retrieved from the programming panel and read during interval 821. interval 82
At the end of 1, a waveform 82 representing
2 is made low level. This terminates or inhibits the validity of programming terminal 600 waveform 811 representing PPGC, and the sequencer then writes data register 1
It acts to write the contents of 2-15 into the word 3 location in memory. The word location is the same location read from memory during interval 821. Thus, memory write interval 823 is used for this purpose. At the end of interval 823, waveform 8
22 goes high and the waveform 811 representing the PPGC pulse appears on the programming panel 600.
begins to flow, as at interval 824,
Continue reading word 4 from memory. The operations described above continue until the last instruction word in memory is read and the desired execution is performed. Here, a waveform 82 representing a signal
5 is generated. This signal is
Appears at the output of NAND gate 11.
Waveform 825 representing the complete signal forces cycle enable waveform 801 low;
At the end of interval 805, sequencer 1
0 will begin waiting for the next successive peak in voltage to repeat a similar cycle. By the waveform 826 representing
The operation is placed in a halt state. sequencer 10 until the next peak occurs.
remains in this state. A waveform 825 representing , is applied to the clear input terminal of flip-flop 93, and a waveform 826 representing , is applied to this terminal of flip-flop 93 to produce waveform 822, which is a negative polarity pulse.
Pulse 822a ensures that the last word from memory is read and completely executed before run mode interval 805 ends. Intervals 821, 823 and 824
In each of the steps, an instruction word is read to or from memory. That is, at the beginning of such an interval, a set of control pulses 830 are generated. These include the following pulses: 1 microsecond long KQD negative polarity pulse. When this becomes true, as in interval 821,
Indicates the beginning of a memory cycle; pulse. A 1 1/2 microsecond long positive pedestal signal that exists 1 microsecond longer than the KQD pulse; AID pulse. This means AID=1 or AID=
Either 0. The means for indicating activation is flip-flop 86 in FIG.
The AID signal is applied to the D input of flip-flop 86. If the Q output of the active indicating means 86 is true as a result of the previous memory cycle, the signal applied to the D input terminal will be AID=1. This signal is a negative polarity pulse, and KQD
It becomes true 1/2 microsecond after the end of the signal. If the Q output of activation means 86 is false, the signal applied to the D input of flip-flop 86 will be AID=0. This signal is 2 microseconds long, and after the dotted line 831,
It has been true for 1/2 microsecond. Dotted line 831
coincides in time with the end of AICK and PDSCK, which are negative pulses. The pulses are the clock pulses applied to flip-flop 86 and the clock pulses applied to push-down stack shift register 80. The means 86 for indicating activation shifts the state on the dotted line 831. The means 86 for indicating activation retains the results of the execution of the instructions;
It acts as a 1-bit width accumulator. Based on the total stored words, new data are loaded into the means for indicating activation. The pushdown stack shifts data down for 2 opcodes, shifts up for 4 opcodes, and does nothing for 10 opcodes. Neither. In particular, the pushdown stack has 16
React as shown in the table containing the OP code. Table OP Codes The Push Down Stack table contains the OP codes that appear on lines B15-B12 from register 12 in FIG. Specifically, for the OP code ST, on lines B15-B12, the 4-bit word
0001 is applied to the processor 61. Timing - Figure 11D Figure 11D shows waveforms 800, 841 and 84.
2 is shown. The waveform that enables the cycle is the one that appears on line 81 at the output of NAND gate 11a. The peak of each half cycle a, c, occurs at point 800a on waveform 800. The output K14 of the counter 38 includes pulses of positive polarity that occur every half cycle of a, c, and voltage. The K14 signal, represented by waveform 841, is applied to the clock input terminal of timer counter 35 via inverter 96. The timer enables the signal represented by waveform 842 to produce one output pulse for every 12 pulses in waveform 841. This means that the pulses on the timer are waveform 8 at intervals of 1/10 seconds.
42. The output of timer counter 35 is the CRY output. It is applied via line 125 to the D input terminal of processor 61 to generate sequence 10.
Used for timing operations when using Such a timer is illustrated by unit 417 in FIG. Timing instructions are loaded into main memory and are read from memory to take effect during sequencer operation control. Controls for such timing operations are included in the tables and programs shown in Table 1 for processors 61 and 63, respectively. Timing - Figure 11E Figure 11E shows (1) Waveform 8 representing the KQD signal.
03, (2) Waveform 813, (3) appearing at the output of the processor 61, representing the (+) signal.
The count output of flip-flop 213 in FIG. 6, as represented by waveform 843, and
The relationship between (4)+signal 814 is shown. Waveform 803 representing the KQD signal is a 1 microsecond wide negative polarity pulse that occurs every 17 microseconds. flip flop 211,
212, 213 and 214 are signals B0-B7 and
A waveform 84 representing a count output is generated in response to AIQ (MCR+JMP). During the waveform 843 representing the count output of the positive polarity pedestal, 3
+ pulses are generated. Waveform 8
43 is extendable for 256 + pulses. The length of waveform 843 representing the count output is the length of the input in FIG. 6 when the pulse representing the (+) signal occurs.
It depends on the value of B0−B7. I/O Unit - FIGS. 13 and 14 In FIG.
and 401 are shown coupled via cable 399 to an I/O unit mounted on. Output unit 409 is base 4
It is mounted on 00. Input unit 41
1 is mounted on a base 401. Bases 400 and 401 are coupled to each other via cable 399a. As already mentioned, since all 256 output units, such as unit 409, can be used with all 256 input units, such as input unit 411,
Base 401 is coupled to an additional base via cable 399b. 13 and 14, power cables 397 and 398 connect bases 400 and 40.
The manner in which the power sent to 1 is used is shown. In the case of electric motor 406, cable 397
Output unit 409 is used to control the power applied to motor 406 through line 408. An interface for accomplishing this is shown in FIGS. 13 and 14. Cable 397 includes one conductor, which is coupled to one terminal of triac 701. The other terminal of triax 701 is coupled to one terminal of motor 406 via line 408a. The other terminal of motor 406 is coupled to a second conductor in cable 397 via common line 408b. Circuitry associated with controller 10 is operative to turn on triax 701 in response to a given output state from controller 10. The control for triax 701 includes an output logic line 702, which is
Light emitting diode (LED) 70 in line 704
3 to the positive power supply. line 70
When the state above 2 is false, tryack 701 is turned on. This is light detection
This is done by detecting light from diode 703 within SCR 705. SCR705 is
Coupled to RC filter circuit 706. This also includes a full wave rectifier diode bridge 707
It is coupled to triax 701 via.
In particular, line 708 is coupled to the gate of triax 701 and is also coupled through capacitor 709 to line 408a. Bridge 70
The top terminal of 7 is coupled via line 710 to a connection point between filter capacitor 711 and filter resistor 712. The top terminal of resistor 712 is coupled to the top electrode of triac 701 and is also coupled to power cable 397 via line 713. Transient clipper unit 714 is coupled to filters 711 and 712 in parallel. A single output circuit is shown in FIG. 14 for use in driving or otherwise controlling motor 406. Similar circuitry is provided to control the application of a, c power to seven additional output channels 720. The control circuits therefor are similar to those described for channel 702, so they will not be described here. Referring again to FIG. 1, switch 40
7 is opened or closed depending on the position of the XY table 404. The switch 407 communicates via a cable 410 to an input unit 411 on the base 401. The state of switch 407 is used to use power from cable 398 in base 401 to signal the state of the switch via cable 399a. FIG. 14 shows the input circuit for one base. In this circuit, the power source is cable 398
is connected to the system via. switch 4
07 connects cable 398 via line 410a
is connected to one of the power conductors inside. The other terminal of switch 407 is connected via line 410b through a voltage divider including resistors 730 and 731.
It is coupled back to the other terminal of line 398. Capacitor 732 is coupled in parallel with resistor 731 to form a filter network. The voltage is dropped by resistors 730 and 731 to approximately 12V when applied to full wave rectifier diode bridge 733. The bridge is coupled via line 734 to trigger unit 735 and then via resistor 736.
Coupled to LED 737. The second terminal of LED 737 is connected to bridge 7 via line 738.
33.
LED 737 is turned on when switch 407 is closed. When LED 737 is turned on, the light from it is transferred to phototransistor 739.
Detected by. Photo transistor 73
When 9 is conducting, it will cause its state on output line 740 to be false. The other line 741 from photo transistor 739 is grounded. Thus, the circuit in FIG. 14 operates to control the state on line 740 to be at a low level when switch 407 is closed. In FIG. 14, seven additional input lines 750 are provided with control circuitry similar to that described for controlling the state of output line 740. It can be seen that base 400 acts as a mounting means for output unit 409. Base 401 acts as a mounting means for the input unit. In the circuits shown in FIGS. 13 and 14, a single unit is used to accommodate both output units such as output unit 409 and input units such as input unit 411 on the same base. The arrangement is such that logic means within the base are used. In the system of FIG. 13, cable 399 is coupled to base 400 by multi-terminal plug 399c. plug 3
99d serves to terminate cable 399a at base 400. A similar plug 399e is coupled to base 401, and cable 399d is coupled to base 401 by plug 399f. In FIG. 13, a line 702 and a line 721 co-located with this line are two 4-bit parallel input/parallel output type shift registers 76.
It is coupled to eight inputs, 0 and 761. Registers 760 and 761 are connected via line 762 to an 8-bit serial input/parallel output shift register.
Coupled to the output of register 763. Controller 1
The output data line from 0 is connected to plug 399c.
through line 764 and further to inverter 76
5 to the data input terminal of register 763. Qh output line 766 is then coupled via inverter 767 to an output data line leading to plug 399d. Thus,
A series of output data will be issued by the controller 10 during each half cycle of the power supply.
It enters unit 400 under the control of a series of clock pulses and shifts to shift register 7.
63 is passed. Also, one new bit is inserted for each clock pulse. line 7
68 is applied to the clock input terminal of shift register 763 via inverter gate 769. This line also plugs 399
Connected to the terminal in d. Thus, when controller 10 reads data on cable 399, 256 bits will be read during each half cycle of voltage. The first bit read is stored in a register, such as register 763, at the end of the set of base units located at the bottom of the cable, starting at location 399d. The last of the 256 output bits is stored in the first bit position in register 763. When the signal is inhibited, the output data is latched into a register such as register 763. During the zero crossing of the voltages a and c in the controller 10, the state signal is
Inverter 77 via O latch line 770
1 and through line 772, shift register 7
60 and 761 clock terminals. This causes the data in register 763 to be shifted into shift registers 760 and 761. Thus, control of the output states on lines 702 and 721 is provided to enable or disable lines 408a and 720, as the case may be. Input logic line 740 and co-located line 750 are coupled to an 8-bit parallel-in, serial-out shift register 775.
The states on line 770 are:
Changes from input mode to output mode. Via inverter 780, the voltage state signals on lines 740 and 750 are read out serially on line 776, and inverter 7
77 to the input data terminal on plug 399c. The input data terminal of plug 399d is connected to register 7 via inverter 778 and line 779.
75 series input terminals. This results in
When the system is in input mode, line 740
and 750, plus state signals on additional 248 similar lines in the co-located base, all of which can be processed in the system, via line 779. Passed through shift register 775. The cable leading to plug 399c includes input data lines, lines,
clock line, output data line, +7.5V line, LED power line, a set of logic ground lines, and thermal
Contains thermal fault lines. In the embodiments described above, various integrated components were used in the manner indicated. Logic units are shown with regular symbols. Other elements used are as shown in the table.

【table】

[Table] Although the invention has been described in connection with specific embodiments, those skilled in the art will appreciate the following:
It is to be understood that further modifications may be suggested, and such modifications are intended to be within the scope of the appended claims.

[Brief explanation of the drawing]

FIG. 1 shows the installation of a programmable controller. 1A and 1B illustrate the switch circuit matrix of the keyboard of FIG. 1. FIG.
FIG. 2 shows a typical ladder network representing the system of FIG. 3 and 4 show the main parts of the sequencer. FIG. 5 shows the memory portion of the sequencer. FIG. 6 shows some of the control elements of the system of FIGS. 3-5. Figures 7 through 10 show details of the program unit used in the present invention. Figures 11A to 11E are timing diagrams. Figure 12 shows Figures 3 and 4.
Between the figures, figures 7 to 10 and figures 11A to 11
The relationship between Figure C and between Figures 13 and 14 is shown. 13 and 14 show an I/O (input/output) unit used in the present invention. Explanation of symbols, 12-15...Units, 61-
63... Processing device, 80... Push-down stack (push-down type rod-shaped switch circuit), 20...
Image register, 25-28...RAM (random access memory), 30-33...ROM
(Read-only memory).

Claims (1)

Claims: 1. Relay ladder diagram logic implemented in a semiconductor integrated circuit for generating signals to control one or more binary output devices as a logical function of the state of one or more binary input devices. A programmable logic controller is used, comprising: a means for controlling the operating sequence of said logic controller; b memory means for storing multi-bit instructions corresponding to said logic function; and c said memory means. Boolean processor means coupled, having first and second input means and an output means, responsive to said instructions, said first and second input means being responsive to said instructions; d Boolean processor means for logically combining single bit data applied simultaneously to the first and second input means to produce a single bit logical result; and d for storing the state of the at least one binary input device. a first storage means having a plurality of single bit storage locations for e. a single bit accumulator register having a second input coupled to storage means for inputting the state of said at least one binary input device, and an output coupled to said first input means of said Boolean processor means; , f means for selecting a state of the at least one binary input device to be transmitted to the Boolean processor means in response to the instructions coupled to and stored in the memory means; g. means for coupling said first storage means to said second input means of said Boolean processor means for transmitting said selected state to processor means; h said logic result being a partial result of said logic function; an input coupled to said accumulator register for inputting and storing a plurality of single-bit logic results that are transmitted in a predetermined order to said accumulator register by said Boolean processor means; an output coupled to the second input means of the Boolean processor means for transmitting the stored plurality of partial results to the Boolean processor means in an order opposite to the predetermined order, thereby Boolean processor means logically combine said partial results to generate a final single bit for controlling said output device according to said state of said input device; i. receiving the single bit logic result when the single bit logic result is the final single bit of the logic function; second storage means having a plurality of single bit storage locations for storing; j in response to said instruction said single bit logic result stored in said accumulator register is a partial result; when the final single bit is transmitted to the reversible serial storage means and when the final single bit is
means for transmitting to a storage means; k coupling said output device to said second storage means, said output device being controlled according to the state of said single bit logic result stored in said second storage means; coupling means for: l initial input every half cycle of the AC power signal in response to the AC power signal being selectively connected to each of the output devices in response to the on/off state of the output devices; timing means for generating an output control signal; m connected to said timing means for writing a single bit word to said first storage means and writing said single bit word to said second storage means in response to said initial input/output control signal; means for reading from the means, when the initial input/output control signal is input, sampling the on/off state of the input device and generating a single bit binary parameter corresponding to the on/off state of the input device; sampling means for sequentially writing the single-bit binary parameter generated by the sampling means to the first storage means; a readout means having said coupling means for continuously reading out a single bit indicating an on/off state for transmission to said output device.