JPS62262458A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS62262458A JPS62262458A JP10596286A JP10596286A JPS62262458A JP S62262458 A JPS62262458 A JP S62262458A JP 10596286 A JP10596286 A JP 10596286A JP 10596286 A JP10596286 A JP 10596286A JP S62262458 A JPS62262458 A JP S62262458A
- Authority
- JP
- Japan
- Prior art keywords
- type semiconductor
- melting point
- thin film
- high melting
- semiconductor region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000010409 thin film Substances 0.000 claims abstract description 16
- 238000002844 melting Methods 0.000 claims abstract description 15
- 230000008018 melting Effects 0.000 claims abstract description 13
- 239000010408 film Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 9
- 239000011229 interlayer Substances 0.000 description 7
- 238000009413 insulation Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
大器B旧叶皐ミtl矛未峨H)冊鴎防訝のナーミ、l々
コンタクト部に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a contact part.
本発明は半導体集積回路装置において、異なる導電型の
半導体の間に高融点金属の硅化物を設けることにより、
異なる4j電型の半2重体を高融点金属の硅化物でオー
ミック コンタクトさせて、異なる導電型の半導体を回
路的に接続したものである。The present invention provides a semiconductor integrated circuit device in which high melting point metal silicide is provided between semiconductors of different conductivity types.
Semiconductors of different conductivity types are connected in a circuit by making ohmic contact between half-duplexes of different 4J conductivity types using high melting point metal silicide.
異なる導電型の半導体を結線させる従来技術の一手段と
してアルミニウムを用いる方法があった例えば、第2図
α、bに示す方法である。1はP型半導体基板、2はN
型半導体領域、3はフィールド酸化朦、5はP型半導体
薄膜、4はN型半導体領域2とP型半導体簿膜5との層
間絶縁瞑、7はアルミニウム、6はP型半導体簿膜5と
アルミニウム7とのm間絶縁民、8はN開路縁膜4゜6
を選択的にエツチングして形成したコンタクト開孔部で
あり、9は層間絶縁膜6を選択的にエツチングして形成
したコンタクト開孔部である。One of the conventional methods for connecting semiconductors of different conductivity types is a method using aluminum, for example, the method shown in FIGS. 2a and 2b. 1 is a P-type semiconductor substrate, 2 is an N
3 is a field oxidation film, 5 is a P-type semiconductor thin film, 4 is an interlayer insulation between the N-type semiconductor region 2 and the P-type semiconductor film 5, 7 is aluminum, and 6 is the P-type semiconductor film 5. Insulation between m and aluminum 7, 8 is N open circuit membrane 4゜6
A contact hole 9 is formed by selectively etching the interlayer insulating film 6. Reference numeral 9 denotes a contact hole formed by selectively etching the interlayer insulating film 6.
N型半導体領域2とP型半導体薄膜5とを回路的に接続
させる目的でダイレクト コンタクトさせると接合形ダ
イオードが形成されてしまうため、コンタクト開孔部8
でN型半導体領vc2とアルミニウム7とをオーミック
コンタクトさせ、コンタクト開孔部9でP型半導体簿
膜5とアルミニウム7とをオーミック コンタクトさせ
ることによりN型半導体領域2とP型半導体薄膜5とを
回路的に接続させていた。If the N-type semiconductor region 2 and the P-type semiconductor thin film 5 are brought into direct contact for the purpose of circuit connection, a junction diode will be formed.
The N-type semiconductor region 2 and the P-type semiconductor thin film 5 are brought into ohmic contact by bringing the N-type semiconductor region VC2 into ohmic contact with the aluminum 7, and by bringing the P-type semiconductor film 5 into ohmic contact with the aluminum 7 through the contact opening 9. It was connected in a circuit.
しかし、前述の従来技術ではアルミニウムとのオーミッ
ク コンタクトによってのみ異なる導電型の半導体を回
路的に接続させることしかできないという問題点を有す
る。However, the above-mentioned conventional technology has a problem in that semiconductors of different conductivity types can only be connected in a circuit manner through ohmic contact with aluminum.
そこで、本発明はこのような問題点を解決するものであ
り、その目的とするところはアルミニウムを用いずに異
なる導電型の半導体を回路的に接続させる方法を提供す
るところにある。The present invention is intended to solve these problems, and its purpose is to provide a method for connecting semiconductors of different conductivity types in a circuit without using aluminum.
本発明の半導体集積回路装置は、第1の半導体基板と、
上記第1の半導体基板の一部表面に形成された第1導T
iL型の第2の半導体領域と、上記第1の半導体基板の
一部表面に絶縁膜を介して形成された上記第1導電型に
対して反対の導電型を示す第2導電型の第3の半導体薄
膜とを含む半導体集積回路装置であって、上記第2の半
導体領域の一部表面に形成された高融点金属の硅化物を
介して上記第2の半導体領域と上記第3の半導体薄膜と
を接合させたことを特徴とする。A semiconductor integrated circuit device of the present invention includes a first semiconductor substrate;
A first conductor T formed on a part of the surface of the first semiconductor substrate
a second semiconductor region of iL type, and a third semiconductor region of a second conductivity type having a conductivity type opposite to the first conductivity type formed on a part of the surface of the first semiconductor substrate via an insulating film. a semiconductor thin film, the second semiconductor region and the third semiconductor thin film are interposed between the second semiconductor region and the third semiconductor thin film through a silicide of a high melting point metal formed on a part of the surface of the second semiconductor region. It is characterized by joining.
本発明の半導体集積回路装置は、基本的には、第1図α
、bに示す構造をしている。1はP型半導体基板、2は
N型半導体領域、3はフィールド酸化膜、5はP型半導
体薄膜、4はN型半導体領域2とP型半導体薄膜5との
層間絶縁膜、10は層間絶縁膜4を選択的にエツチング
して形成したコンタクト開孔部であり、11は高融点金
属の硅化物である。Basically, the semiconductor integrated circuit device of the present invention is shown in FIG.
, has the structure shown in b. 1 is a P-type semiconductor substrate, 2 is an N-type semiconductor region, 3 is a field oxide film, 5 is a P-type semiconductor thin film, 4 is an interlayer insulation film between the N-type semiconductor region 2 and the P-type semiconductor thin film 5, and 10 is an interlayer insulation A contact hole is formed by selectively etching the film 4, and 11 is a high melting point metal silicide.
N型半導体領域2とP型半導体簿膜5との間に高融照会
14の硅化物11との接合を形成することでN型半導体
領域2と高融点金属の硅化物11をオーミック コンタ
クトさせるとともにP型半導体薄膜5と高融点金属の硅
化物11をオーミックコンタクトさせることができるの
で、高融点金属の硅化物11を介してN型半導体領域2
とP型半導体薄膜5とを回路的に接続させることができ
る〔発明の効果〕
本発明の効果は、異なる導電型の半導体を回路的に接続
させるのに異なる導電型の半導体の間に高融点金属の硅
化物との接合を形成することによって、従来のコンタク
ト開孔1@S2箇所を1箇所にすることができた。すな
わち、コンタクト開孔部を半分にすることができ集積度
を向上させるとともに歩留り向上にも寄与した。また、
アルミニウム等の金属配線材料を使用しないために信頼
性が向上した。By forming a junction with the high melting point metal silicide 11 between the N type semiconductor region 2 and the P type semiconductor layer 5, the N type semiconductor region 2 and the high melting point metal silicide 11 are brought into ohmic contact. Since the P-type semiconductor thin film 5 and the high-melting point metal silicide 11 can be brought into ohmic contact, the N-type semiconductor region 2 can be connected via the high-melting point metal silicide 11.
and the P-type semiconductor thin film 5 can be connected in a circuit manner. [Effects of the Invention] An advantage of the present invention is that in order to connect semiconductors of different conductivity types in a circuit manner, it is possible to connect semiconductors of different conductivity types to each other in a circuit manner. By forming a bond between the metal and the silicide, it was possible to reduce the number of conventional contact holes 1@S from 2 to 1. In other words, the contact opening can be halved, improving the degree of integration and contributing to an improvement in yield. Also,
Reliability is improved because metal wiring materials such as aluminum are not used.
第1図(α)は、本発明の半導体集積回路装置の一実施
例を示す平面図であり、(b)はその主要断面図である
。
第2図(α)は、従来の半導体集積回路装置を示す平面
図であり、(b)はその主要断面図である。
1・・・・・・P型半導体基板
2・・・・・・N型半導体領域
3・・・・・・フィールド酸化膜
4・・・・・・層間絶縁膜
5・・・・・・P型半導体薄膜
6・・・・・・層間絶縁膜
7・・・・−・アルミニウム
8.9.10・・・・・・コンタクト開孔部11・・・
・・・高融点金属の硅化物
賦1邑(a)
富11!lb)
第21¥1 (1))FIG. 1(α) is a plan view showing an embodiment of the semiconductor integrated circuit device of the present invention, and FIG. 1(b) is a main sectional view thereof. FIG. 2(α) is a plan view showing a conventional semiconductor integrated circuit device, and FIG. 2(b) is a main sectional view thereof. 1...P type semiconductor substrate 2...N type semiconductor region 3...Field oxide film 4...Interlayer insulating film 5...P type semiconductor thin film 6... Interlayer insulating film 7... Aluminum 8.9.10... Contact opening portion 11...
...High melting point metal silicide 1 eup (a) wealth 11! lb) No. 21 ¥1 (1))
Claims (1)
部表面に形成された第1導電型の第2の半導体領域と、
上記第1の半導体基板の一部表面に絶縁膜を介して形成
された上記第1導電型に対して反対の導電型を示す第2
導電型の第3の半導体薄膜とを含む半導体集積回路装置
であつて、上記第2の半導体領域の一部表面に形成され
た高融点金属の硅化物を介して上記第2の半導体領域と
上記第3の半導体薄膜とを接合させたことを特徴とする
半導体集積回路装置。(1) a first semiconductor substrate; a second semiconductor region of a first conductivity type formed on a partial surface of the first semiconductor substrate;
A second semiconductor substrate having a conductivity type opposite to the first conductivity type formed on a part of the surface of the first semiconductor substrate via an insulating film.
A semiconductor integrated circuit device including a third conductive type semiconductor thin film, wherein the second semiconductor region and the above are connected to each other through a silicide of a high melting point metal formed on a part of the surface of the second semiconductor region. A semiconductor integrated circuit device, characterized in that it is bonded to a third semiconductor thin film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10596286A JPS62262458A (en) | 1986-05-09 | 1986-05-09 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10596286A JPS62262458A (en) | 1986-05-09 | 1986-05-09 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62262458A true JPS62262458A (en) | 1987-11-14 |
Family
ID=14421421
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10596286A Pending JPS62262458A (en) | 1986-05-09 | 1986-05-09 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62262458A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63124551A (en) * | 1986-11-14 | 1988-05-28 | Nec Corp | Semiconductor integrated circuit device |
JPH03120828A (en) * | 1989-10-04 | 1991-05-23 | Nec Corp | Semiconductor device and manufacture thereof |
-
1986
- 1986-05-09 JP JP10596286A patent/JPS62262458A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63124551A (en) * | 1986-11-14 | 1988-05-28 | Nec Corp | Semiconductor integrated circuit device |
JPH03120828A (en) * | 1989-10-04 | 1991-05-23 | Nec Corp | Semiconductor device and manufacture thereof |
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