JPS62262158A - Memory managing system - Google Patents

Abstract

PURPOSE:To execute a unified memory management by a logical address, by using a multi-dimensional logical address, in case of allocating a logically multi- dimensional data array to a physical memory. CONSTITUTION:In case a data structure of a software, etc. is considered by an n-dimensional array, an n-dimensional logical address is outputted from a processor 11. In accordance with a speed for executing an access to a memory 14 of the processor, and the number of pins of a chip, the n-dimensional address is outputted in parallel simultaneously, or outputted by a time division. It is inputted to a one-dimensional address converting circuit which is contained in a memory managing unit 15, and converted to a one-dimensional physical address which can execute an access to the memory. In such a way, information is not lost, and a unified and ideal memory management can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a memory management system that performs memory management using logical addresses.

(Prior Art) As the performance of combinators improves and their application fields expand, the role of "memory" in information processing systems has become significantly larger, both in terms of hardware and software. Management units that follow this effective philosophy are required to meet even more stringent specifications than ever before.

By the way, the interface between the memory that controls the above-mentioned "1 memory" and devices that refer to this memory, that is, processors and input/output devices, is usually a linear address (-dimensional address). An example of a multi-processing system is shown in 3. 41, 42.4 in both figures.
3 is a processor, and 44 is a memory.

(Problems to be Solved by the Invention) As described above, the interface between the memory 44 and a device that can directly access the memory 44, such as the processor 41, is
It is a linear address (one-dimensional address). Therefore, if the software that controls the processor 41 is multi-dimensional in terms of logic, there is a drawback that the amount of information is lost when converted to a linear address. Also,
As shown in FIG. 5, a plurality of processors 4J, 42
．． 43 access the same memory 44, each processor 41, 42, 43 independently outputs a physical address, which has the disadvantage that unified memory management is not possible.

The present invention was made based on the above-mentioned circumstances (:
The purpose of this invention is to provide a memory management method that outputs multidimensional logical addresses from a die that directly accesses memory, and performs unified memory management using logical addresses.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention uses a multidimensional logical address to perform memory mapping when a logically multidimensional data array is allocated to a physical memory. ,
Safe! (write protection), clipping, etc., and also converts the memory determined by mapping into a physical address that can be directly referenced and specifies the memory address. In order to realize this memory referencing method, we provided a device that can output not only physical addresses that can directly refer to memory, but also the above-mentioned multidimensional logical addresses.

(Function) If the data structure of software etc. is considered as an n-dimensional array, an n-dimensional logical address is output from the processor. Depending on the speed of accessing the memory of the processor or the number of pins of the chip, the n-dimensional addresses are output in parallel or simultaneously or in a time-division manner. This is input to a one-dimensional address conversion circuit and converted into a one-dimensional physical address that can access the memory. This makes it possible to realize unified memory management without losing the amount of information.

(Example) Examples of the present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 11 is a device that directly accesses memory, such as a processor (CPU), and unlike the conventional device, generates n-dimensional logical addresses.

1g is a memory management unit (MCU), and the above CP
This is a circuit that converts the n-dimensional logical address generated by the UI 1 into a linear address so that the memory (MMU) 14 can be accessed.

The operation will be explained below. When the data structure of software or the like is considered as an n-dimensional array, the processor 11 outputs an n-dimensional logical address. Depending on the speed at which the memory 14 of the processor 1 is accessed and the number of pins of the step, the n-dimensional addresses are output simultaneously to the walls or in a time-sharing manner. This is input to a one-dimensional address conversion circuit built into the memory management unit 15, and the memory is converted into a one-dimensional address that can be accessed.

Translated to a physical address.

FIG. 2 is a diagram showing an embodiment of the present invention in which a plurality of processors access the same memory. In the figure, 21 to 23 are processors, 25 is a management unit, and 24 is a memory. The n-dimensional logical addresses output from each of the processors 21 to 23 are managed by the memory management unit 25 in a unified manner as logical addresses.
Converted to a one-dimensional physical address.

FIG. 3 is a diagram showing an example of application of the present invention to two-dimensional image control. In the figure, numeral 31 is an LSI chip that executes raster operation.
(bit boundary block transfer
32 is a drawing processor that writes information such as graphics to the bitmap memory 34 at high speed. 4th raster with bttb+t function
A two-dimensional mail address is output from the storage chip 31 and the drawing processor 32 which displays figures and the like. Here, the address management unit 35 performs memory management such as conversion into one-dimensional physical addresses and clipping, and controls the bitmap memory 34.

〔Effect of the invention〕

As explained above, when a device whose data structure is logically configured in multiple dimensions accesses memory, it outputs a multidimensional logical address, so it outputs a conventional one-dimensional address. The amount of information does not decrease as would be the case if the memory was accessed directly. (
Although n dimensions can be converted into one dimension, one dimension cannot be converted into n dimensions. ) Furthermore, when multiple devices access the same memory, the use of logical addresses allows unified and ideal memory management, which was not possible with physical addresses.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention (uniprocessing). FIG. 2 is a block diagram showing another embodiment of the invention (multiprocessing).
FIGS. 4 and 5, which are block diagrams showing an example of application to dimensional image display, are conventional examples corresponding to FIGS. 1 and 2, respectively. IJ, 21, 22, 2 j-...Processor, 14°24...Memory, 15, 25, 35-...
・Memory management unit, j 1-... Raster operation Sonotech, 32... Drawing processor, j 4-...
・Pit map memory. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] A memory management method characterized by using a multidimensional logical address when allocating a logically multidimensional data array to memory, converting the memory determined by this allocation into a physical address that is directly referenced, and specifying the memory address. .