JPS62260263A - Program control system by multiprocessor - Google Patents

Abstract

PURPOSE:To increase the processing speed of a multiprocessor by actuating effectively a subprocessor for control. CONSTITUTION:A main processor 1 drives a halt control circuit 12 to stop temporarily the working of a subprocessor 10 and shifts a program needed for the next processing of the subprocessor 10 to a memory 16 from a memory 6 via an information transmission circuit 13. Then the processor 1 shifts the data needed for the next processing of the subprocessor to a memory 15 from a memory 5 and controls a reset control circuit 11 to start the subprocessor 10. The subprocessor 10 uses the data stored in the memory 15 to perform its own processing in accordance with a program stored in the memory 16. Then the subprocessor 10 stores the result of its own processing and delivers an end signal to a gate circuit 14. Thus the processor 1 knows the end of the processing via the circuit 14 and sends the result of the processing to the corresponding input/output control parts 2a-2e from the memory 15 via the circuit 13.

Description

[Detailed Description of the Invention] [Summary] A halt control circuit that stops the sub-processor from the main processor and a reset control circuit that starts the sub-processor from the main processor are provided, and programs and data are exchanged between the memories of both processor systems. An information transmission circuit is provided as a path for performing this process, and a gate circuit is provided to notify the main processor of the completion of processing in the sub-processor system.

[Industrial application field]

The present invention includes a line control section, a medium evacuation control section, an MSIJ-do/
The present invention relates to an improvement in a passbook printer that employs a multiprocessor system having input/output control units such as a write control unit, a print control unit, and an image recognition control unit.

[Conventional technology]

FIG. 3 is a diagram showing an example of the equipment configuration of a conventional passbook printer.

In the figure, ζ1 is the main processor, 2a is the line control unit, 2A
is a subprocessor, 2b is a medium evacuation control unit, and 2c is an MS
I, I-read/write control unit, 2C is a subprocessor, 2
d is a print control unit, 2D is a sub-processor, 2e is an image recognition control unit, 2E is a sub-processor, 3 is a mechanical unit, 4
(boo) ROM, and 5.6 are memories, respectively. Note that the same symbols represent the same objects throughout the following discussion.

A passbook printer conventionally used in banks/securities companies, etc. has a device configuration shown in FIG.

In the so-called passbook printer, the media are slips, forms,
Various things such as bankbooks and certificates are used, and since it is a device with various functions, in order to realize these various functions,
Normally, a subprocessor is provided for each function to perform control.

For example, a subprocessor record is provided for controlling the line control unit 2a that exchanges data with an external device, and a subprocessor record is provided to read/write the magnetic stripe MS.
A sub-processor 2C is provided to control the read/write control section 2c, a sub-processor 2D is provided to control the print control section 2d, and a sub-processor 2E is provided to control the image recognition control section 2e. The main processor 1 performs comprehensive control of the system.

Note that the ROM 4 is used for initial loading, the memory 5 is used as a work area, and the memory 6 is used to store programs.

[Problem that the invention seeks to solve]

As is clear from the above explanation, conventional passbook printers use a large number of sub-processors, each of which performs a designated task, but each sub-processor is not always operating and is therefore not used efficiently. There were drawbacks.

[Means for solving problems]

As shown in the principle diagram of FIG. 1, the above problem is caused by the main processor 1 to which the memory 6 in which the processing program is stored is connected via the bus 1a, and the memory 16 to which the processing program is transferred and stored is connected to the main processor 1 via the bus 10a. The connected sub-processor 10 is provided to connect between the main processor 1 and the sub-processor 10, and the main processor 1 starts the sub-processor 10 and the set control circuit 11, and the main processor 1 stops the sub-processor 10. Holt control circuit 12, information transmission circuit 13 between main processor I system and sub-processor 10 system, sub-processor 10
This problem can be solved by providing a gate circuit 14 that notifies the completion of processing.

[Effect]

According to the invention, the main processor 1 includes a halt control circuit 1
2 and stop the operation of the sub-processor 10, the program stored in the memory 6 is transferred to the memo 6 via the information transmission circuit 13, and the reset control circuit 1 is activated.
1 activates the sub-processor IO, the sub-processor 10 performs processing according to the program stored in the memory I6, and after the program is finished, activates the gate circuit 14 to notify the main processor 1 and stores it in the memory 15. The main processor 1
It becomes possible to simultaneously process 1 setter 10 and 1 setter 10.

〔Example〕

FIG. 2 is a diagram showing an embodiment of a program control system using a multiprocessor according to the present invention.

In the figure, 10 is a sub-processor according to the present invention, 11 is a reset control circuit, 12 is a halt control circuit, 13 is an information transmission circuit, 14 is a gate circuit, 15 is a memory, and 16 is a memory.

In the present invention, unlike the conventional system, one sub-processor 10 is provided for controlling the line control section 2a, MS read/write control section 2C1, print control section 2d, image recognition control section 2e, etc., and the sub-processor 10 is effectively used. For operation, reset control circuit 11, halt control circuit 12, information transmission circuit 13, gate circuit 14, memo IJ 15, memory 1
6 was added.

The reset control circuit 11 is a circuit that sends a reset signal to the sub-processor 10 in response to a command from the main processor 1 to restart the sub-processor 10.

The halt control circuit 12 is a circuit that issues a halt signal 3 to the sub-processor 10 in response to a command from the main processor 1 to stop the operation of the sub-processor 10.

The information transmission circuit 13 is a circuit that allows the main processor 1 to access the memory 15 and the memo 6 when the sub-processor 10 is in a halt state.

The gate circuit 14 is a circuit that is notified of the completion of processing by the sub-processor 10 and registers it, making it possible to detect the bus open state of the sub-processor 10 and the point at which the processing ends.

Therefore, the gate circuit 14 eliminates memory contention between both processors, and the processing speed of the sub-processor IO is effectively improved.

The memory 15 is from the main processor 1 to the sub processor 1.
This is a memory area where data/parameters are transferred to the sub-processor 10 and a work area in program processing by the sub-processor 10.

The memory 16 is connected to the main processor 1 to the sub processor 1.
0, and the sub-processor 10 executes the program stored in this area.

In this system, the main processor 1 drives the halt control circuit 12 to temporarily stop the operation of the sub-processor 10, and stores the program necessary for the next process to be performed by the sub-processor 10 into the memory via the information transmission circuit 13. 6 to the memory 16, and then from the memory 5 to the memory 15, the data necessary for the processing to be performed by the sub-processor 10 is transferred from the memory 5 to the memory 15, respectively, and the reset control circuit II is controlled to start the sub-processor 10.

The sub-processor 10 performs processing using the data stored in the memory 15 according to the program stored in the memory 16, stores the result in the memo 5, and issues an end signal to the gate circuit 14. .

As a result, the main processor 1 learns of the completion of processing through the gate circuit 14, and transmits the processing results to the corresponding input/output control units 28 to 2e from the memo January 5 through the information transmission circuit 13.

In the explanation above, an example was given in which the sub-processor 10 processes only one input/output control unit from when the reset signal is issued until when the end signal is issued. Of course, it is also possible to transfer programs and data to the input/output control section and have the subprocessor 10 perform these processes in parallel.

〔Effect of the invention〕

As explained in detail above, according to the present invention, compared to the conventional method in which a sub-processor is provided for each specific I10, (1) the sub-processor side is more versatile, the processing speed of other I10 controls is improved, and (2) It is also possible to use multiple sub-processors; in this case, the processing speed increases in proportion to the number of sub-processors used; ■ Since the sub-processors operate independently of the main processor, bus timing It has the great effect of not having any restrictions.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a diagram showing an embodiment of a program control method in a multiprocessor system according to the present invention. FIG. 3 is a diagram showing an example of the equipment configuration of a conventional passbook printer. In the figure, 1 is the main processor, 2a is the line control unit, 2A
is a subprocessor, 2b is a medium evacuation control unit, and 2c is M
S IJ-read/write control unit, 2C is a sub-processor,
2d is a print control unit, 2D is a sub-processor, 2e is an image recognition control unit, 2E is a sub-processor, 3 is a mechanical unit,
4 is a boot 1-ROM, 5 and 6 are memories respectively, 10
11 is a reset control circuit, 12 is a halt control circuit, 13 is an information transmission circuit, and 14 is a sub-processor according to the present invention.
is a gate circuit, and 15 and 16 are memories, respectively. Fig. 1 An example of a program control system using a multiprocessor according to the present invention Fig. 2 An example of the equipment configuration of a conventional passbook printer Fig. 3

Claims (1)

[Claims] The memory (6) in which the processing program is stored is connected to the bus (1a
), the main processor (1) is connected via a bus (
a sub-processor (10) connected via the main processor (1) and the sub-processor (10);
The main processor (1) is connected to the sub-processor (10).
a reset control circuit (11) that starts up the main processor (1) and the sub-processor (10);
a halt control circuit (12) for stopping the main processor (1) system and the sub-processor (10);
) system, and a gate circuit (14) for notifying the end of processing of the sub-processor (10), and the main processor (1) is connected to the halt control circuit (12).
After activating the sub-processor (10) and stopping the operation of the sub-processor (10), the processing program stored in the memory (6) is transferred to the memory (16) via the information transmission circuit (13), and the reset is performed. The sub-processor (10) is activated by the output of the control circuit (11), and after performing processing according to the processing program transferred to the memory (16), the sub-processor (10) starts the gate circuit (14). A program control method using a multiprocessor, characterized in that the main processor (1) is activated, notifies the main processor (1) of the completion of processing, and transfers the processing result to the main processor (1) via the information transmission circuit (13). .