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JPS62265728A - Anodic bonding method - Google Patents

Anodic bonding method

Info

Publication number
JPS62265728A
JPS62265728A JP61108544A JP10854486A JPS62265728A JP S62265728 A JPS62265728 A JP S62265728A JP 61108544 A JP61108544 A JP 61108544A JP 10854486 A JP10854486 A JP 10854486A JP S62265728 A JPS62265728 A JP S62265728A
Authority
JP
Japan
Prior art keywords
sio2
bonding method
anodic bonding
substrate
voids
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61108544A
Other languages
Japanese (ja)
Inventor
Masayoshi Kitamura
北村 昌良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP61108544A priority Critical patent/JPS62265728A/en
Publication of JPS62265728A publication Critical patent/JPS62265728A/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)

Abstract

PURPOSE:To eliminate voids in a part to be finally obtained by anodic bonding by separating in advance at least one SiO2 by grooves into a plurality of insular parts. CONSTITUTION:A plurality of insular SiO2 7 separated by grooves 6 are formed by patterning on one Si substrate 5, the surfaces of SiO2 7 and SiO2 3 are opposed to be bonded in this state. When temperature is raised in a furnace, the surface of the SiO2 7 is started to be bonded at the side of the substrate 5, so that voids resulted from bonding at multiple points are concentrated in the groove 6. Thus, when the grooves formed by the voids are thereafter removed, a small substrate having a bonded part without void can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、Si基板を重ね合わせて1枚の基板を得るア
ノ−ディックボンディング法に関し、特にそのポンディ
ングが良好に行われるようにした方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an anodic bonding method for stacking Si substrates to obtain a single substrate, and in particular to a method for achieving good bonding. Regarding.

(従来技術〕 アノ−ディックボンディング法は、第3図に示すように
、Si (シリコン)基板l、2の5iOz (酸化シ
リコン)3.4を炉内で対面接触させで、静電気力で加
圧すると共に高温加熱して相互に接着させる接着方法で
ある。
(Prior art) As shown in Fig. 3, in the anodic bonding method, Si (silicon) substrates 1 and 2 of 5iOz (silicon oxide) 3.4 are brought into face-to-face contact in a furnace, and pressure is applied using electrostatic force. This is an adhesion method in which both are heated at high temperature and bonded to each other.

この方法により、パワーICの素子弁n1等を行なうこ
とができ、従来のポリシリコンを使用する場合に比較し
てウェハの反りが小さく、また曵結晶であるため熱の放
散性が良い等の利点がある。
With this method, it is possible to perform the element valve n1 of power IC, etc., and it has advantages such as less warping of the wafer compared to the case of using conventional polysilicon, and good heat dissipation because it is a hollow crystal. There is.

ところが、このポンディング方法は、平坦なSiO□面
を接着させるので、その接着部分の内部にガスやパーテ
ィクルを含んだボイド(void)が発生し、欠陥が発
生するという問題がある。
However, since this bonding method bonds flat SiO□ surfaces, there is a problem in that voids containing gas and particles are generated inside the bonded portion, resulting in defects.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、ボイドが発生しないようにした7ノー
デイツクボンデイング法を提fJ%することである。
An object of the present invention is to provide a non-dick bonding method that does not generate voids.

〔発明の構成〕[Structure of the invention]

このために本発明は、予め少なくとも一方の5i02を
溝により複数の島状に分離しておくようにした。
For this reason, in the present invention, at least one 5i02 is separated into a plurality of islands by grooves in advance.

〔実施例〕〔Example〕

以下、本発明の実施例について説明する。第1図はその
一実施例を示す図である。本実施例では、一方のSi基
板5に溝6によって分離した複数の島状のSiO□7を
パターニングにより設けておいて、この状態でその5i
Oz 7の面と5iOz3の面とを対面させて接着させ
るようにした。
Examples of the present invention will be described below. FIG. 1 is a diagram showing one embodiment thereof. In this embodiment, a plurality of island-shaped SiO□7 separated by grooves 6 are provided on one Si substrate 5 by patterning, and in this state, the
The 7 Oz surface and the 5iOz 3 surface were made to face each other and adhered to each other.

炉内において温度を上昇させると、Si基板5の側にお
いては、5iOz 7の面から接着が開始し、多点での
接着の結果できるボイドは、溝6内に集中するようにな
る。
When the temperature is increased in the furnace, adhesion starts from the 5iOz 7 surface on the Si substrate 5 side, and voids formed as a result of adhesion at multiple points become concentrated in the grooves 6.

よって、このボイドのできた溝部分を後で除去すれば、
ボイドの無い接着部分を有する小基板を得ることができ
る。
Therefore, if you remove this voided groove later,
A small substrate having a void-free bonded portion can be obtained.

第2図は別の例を示す図であり、5i(h 7の上面に
更に凸部8を設けたものであり、この場合はこの凸部8
の部分から接着が開始し、ボイドをより正確に溝6内に
集中させることができるようになる。
FIG. 2 is a diagram showing another example, in which a convex portion 8 is further provided on the upper surface of 5i (h 7, and in this case, this convex portion 8
Adhesion starts from the portion , making it possible to more accurately concentrate the voids within the groove 6.

なお、上記したSiO□7の上面、或いは凸部8の上面
部分に、P(燐) 、As (砒素)、B (硼素)、
Ge (ゲルマニウム)等の添加層を形成すれば、軟化
点が低下して、より低い温度で接着を実現することがで
きる。
In addition, on the upper surface of the above-mentioned SiO□7 or the upper surface portion of the convex portion 8, P (phosphorus), As (arsenic), B (boron),
By forming an additive layer of Ge (germanium) or the like, the softening point is lowered and adhesion can be achieved at a lower temperature.

〔発明の効果〕〔Effect of the invention〕

以上から本発明によれば、アノーディンクボンディング
によって最終的に得るべき部分にボイドが発生しないよ
うにすることができる。
As described above, according to the present invention, it is possible to prevent voids from occurring in the portion to be finally obtained by anodically bonding.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の説明図、第2図は別の実施
例の説明図、第3図はアノ−ディ、クボンディング法の
説明図である。 1.2.5・・・Si基板、3.4.7・・・SiO□
、6・・・溝、8・・・凸部。
FIG. 1 is an explanatory diagram of one embodiment of the present invention, FIG. 2 is an explanatory diagram of another embodiment, and FIG. 3 is an explanatory diagram of the anode and bonding method. 1.2.5...Si substrate, 3.4.7...SiO□
, 6... Groove, 8... Convex portion.

Claims (3)

【特許請求の範囲】[Claims] (1)、個々のSi基板の上面に形成した各々のSiO
_2を相互に接着するアノーディックボンディング法に
おいて、 予め少なくとも一方のSiO_2を溝により複数の島状
に分離しておくことを特徴とするアノーディックボンデ
ィング法。
(1) Each SiO formed on the top surface of each Si substrate
An anodic bonding method for bonding SiO_2 to each other, the anodic bonding method is characterized in that at least one of the SiO_2 is separated into a plurality of islands by grooves in advance.
(2)、上記島状のSiO_2が、凸部を有することを
特徴とする特許請求の範囲第1項記載のアノーディック
ボンディング法。
(2) The anodic bonding method according to claim 1, wherein the island-shaped SiO_2 has a convex portion.
(3)、上記SiO_2が、その表面にP、As、B、
Ge、等の添加層を有することを特徴とする特許請求の
範囲第1項又は第2項記載のアノーディックボンディン
グ法。
(3), the above SiO_2 has P, As, B,
The anodic bonding method according to claim 1 or 2, characterized in that it has an additive layer of Ge or the like.
JP61108544A 1986-05-14 1986-05-14 Anodic bonding method Pending JPS62265728A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61108544A JPS62265728A (en) 1986-05-14 1986-05-14 Anodic bonding method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61108544A JPS62265728A (en) 1986-05-14 1986-05-14 Anodic bonding method

Publications (1)

Publication Number Publication Date
JPS62265728A true JPS62265728A (en) 1987-11-18

Family

ID=14487515

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61108544A Pending JPS62265728A (en) 1986-05-14 1986-05-14 Anodic bonding method

Country Status (1)

Country Link
JP (1) JPS62265728A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396042A (en) * 1991-12-25 1995-03-07 Rohm Co Ltd Anodic bonding process and method of producing an ink-jet print head using the same process
KR100490756B1 (en) * 2003-06-10 2005-05-24 전자부품연구원 Anodic bonding Method using cap
US7153759B2 (en) 2004-04-20 2006-12-26 Agency For Science Technology And Research Method of fabricating microelectromechanical system structures
US7192841B2 (en) 2002-04-30 2007-03-20 Agency For Science, Technology And Research Method of wafer/substrate bonding
US7259466B2 (en) 2002-12-17 2007-08-21 Finisar Corporation Low temperature bonding of multilayer substrates
US7361593B2 (en) 2002-12-17 2008-04-22 Finisar Corporation Methods of forming vias in multilayer substrates
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873166A (en) * 1981-10-13 1983-05-02 ユナイテツド・テクノロジ−ズ・コ−ポレイシヨン Capacitive pressure transducer and method of producing same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5873166A (en) * 1981-10-13 1983-05-02 ユナイテツド・テクノロジ−ズ・コ−ポレイシヨン Capacitive pressure transducer and method of producing same

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396042A (en) * 1991-12-25 1995-03-07 Rohm Co Ltd Anodic bonding process and method of producing an ink-jet print head using the same process
US6086188A (en) * 1991-12-25 2000-07-11 Rohm Co., Ltd. Ink-jet print head having parts anodically bonded
US7192841B2 (en) 2002-04-30 2007-03-20 Agency For Science, Technology And Research Method of wafer/substrate bonding
US7259466B2 (en) 2002-12-17 2007-08-21 Finisar Corporation Low temperature bonding of multilayer substrates
US7361593B2 (en) 2002-12-17 2008-04-22 Finisar Corporation Methods of forming vias in multilayer substrates
KR100490756B1 (en) * 2003-06-10 2005-05-24 전자부품연구원 Anodic bonding Method using cap
US7153759B2 (en) 2004-04-20 2006-12-26 Agency For Science Technology And Research Method of fabricating microelectromechanical system structures
US7405466B2 (en) 2004-04-20 2008-07-29 Agency For Science, Technology And Research Method of fabricating microelectromechanical system structures
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
US8389385B2 (en) 2009-02-04 2013-03-05 Micron Technology, Inc. Semiconductor material manufacture

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