JPS62252265A - Inproved picture processor concerning data selecting table - Google Patents

Abstract

PURPOSE:To eliminate the need for increasing the capacity of a table even when the accuracy of magnification is made fine by making a data selecting table into a rewritable memory, executing the calculation with an arithmetic means by the expanding reducing conditions instructed from the external part and writing the selecting table in the memory. CONSTITUTION:As the constituted part of a data selecting table 405, data selection RAM 4050 as a rewritable memory is used. In accordance with the magnification information (A channel is shown....) inputted through an I/O port 4053, selecting data SD for interpolation ROM 403 and a processing timing signal TD are calculated by a CPU 4051 and the data are written into the data selection RAM 4050. The writing channel is shown by.... Since by designating the magnification, the selecting data SD and the processing timing signal TD corresponding to the designated magnification are stored into the data selection RAM 4050 as the data selection table, next, when the processing of expansion and reduction is started, the address of a counter circuit 406 is selected by a selecting circuit 4052, given to the data selection RAM 4050 and reading is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that does not require an increase in memory capacity even when the accuracy of magnification becomes finer.

[Foreground of invention]

2. Description of the Related Art Japanese Patent Laid-Open No. 146358/1983 has been proposed as an image processing apparatus for enlarging/reducing image data.

This is designed to perform enlargement or reduction processing by changing successive clocks (that is, transfer locks) from an image reading element such as a CCD according to the magnification.

For example, if the time taken for one scan by a laser printer as a recording device is Tw, and the number of pixels present during scanning is N, then the printer's transfer opening/cutting frequency fo is fo-N/7w Similarly, If the transfer lock from the CCD is f, then f
= N/T where T is the period during which the CCD performs one scan.

Here, f>fo...Reduction f<fo...enlarge becomes.

However, in this method, in order to change the transfer lock, it is necessary to control the exposure amount of the CCD used, and the circuit tends to be complicated. Furthermore, the circuit for changing the frequency of the transfer lock is complicated, which poses a problem especially when the magnification step is made fine. Furthermore, since this method performs scaling simply by sampling, the image quality after processing is not good.

Therefore, the inventors prepared interpolation data in the ROM in advance for interpolating the data between pixels of the read image information, and combined the read image data with the interpolation data selection data according to the set magnification conditions. Based on this, we proposed a system in which the interpolated data is read out and enlarged/reduced.

In this method, there is no need to change the transfer lock depending on the magnification, so there is no need for a complicated lock generation circuit, there is no need to control the exposure amount, and the image quality is also improved.

However, in this method, it is necessary to configure a data selection table for selecting the interpolation data described above in ROM and store selection data according to the magnification in advance, so the ROM for the selection table has a large capacity. is necessary, and this becomes especially noticeable when using a fine magnification.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problems and to make it unnecessary to increase the capacity of the table even if the precision of the magnification is made finer.

[Structure of the invention]

To this end, the present invention provides an image processing apparatus that performs image scaling processing using an interpolation table for interpolating a plurality of pieces of image information and a data selection table for selecting specific interpolation data from the interpolation table. In the present invention, the data selection table is constructed of a rewritable memory, and the result of calculation by the calculation means according to the magnification conditions instructed from the outside is written into the memory as selection data.

〔Example〕

The present invention will be explained in detail below.

(1) Basic configuration of three image reading devices FIG. 1 shows a block diagram of the image reading device.

1 is an image reading device that performs enlargement/reduction processing on document information according to a specified magnification and outputs the result; 2 is a laser printer and LED that performs recording using binary data obtained by the image reading device 1;
It is a recording device such as a printer.

The image reading device 1 includes a document reading section 3 and an enlargement/reduction circuit 4.
is built-in. The document reading unit 3 reads the document using a photoelectric conversion element such as a CCD, converts it into an electrical signal, and converts the document into an electrical signal.
/D conversion and shading correction, etc., and then output as original image data. The enlargement/reduction circuit 4 performs an enlargement/reduction process on the original image data from the document reading section 3 in accordance with a magnification set from the outside in synchronization with a timing signal. This enlarged or reduced converted image data is then converted into binary data in accordance with the recording device 2 at the subsequent stage.

(2), Original reading section The configuration is shown in FIG. A document is read by CC0300, amplified to a predetermined level by amplifier 301, and then input to ^/D converter 302. This A/D converter 3
At step 02, the input analog signal is converted into a digital signal using the voltage of the reference power supply 303 as a reference.

In this example, 6 bits convert from 0 to 63 levels. A shading correction circuit 304 corrects optical illuminance unevenness in the image signal read by the CCD 300, and corrects the image signal converted into a 6-bit digital signal by the A/D converter 302. Thereafter, this shading-corrected image data is used as original image data D.
Call it a. This original image data Da is sent to the enlargement/reduction circuit 4. The above processing timing is performed by a signal from the synchronization control circuit 305. This synchronous control circuit 305 operates based on a signal from a crystal oscillator 306.

FIG. 3 is a timing chart showing timing signals generated in this synchronization control circuit 305. CLKI is an image transfer lock and serves as a clock for the A/D converter 302, shading correction circuit 304, and others. Also,
This clock CLKI is counted and the horizontal synchronization signal H-
SYNC occurs. This signal ll-3YNC is a CCD
It is also a read start shift pulse SH. φ11φ2 are signals having a period 1/2 times that of the image transfer lock CLKI and having different phases, and are clocks for shifting the analog shift registers of the odd and even parts of the CCD, respectively.

In the read image data signal VIDEO from the CCD 300, the first image data is read out from the output of the shift pulse SH, and then the second, third, and so on, 5000 bits are read out sequentially. The main scanning valid signal H-VALID becomes active only in the 5th to 4756th section and is extracted. Signal RS is a pulse that resets the shift register of CCD 300 for each shift, and is generated at the trailing edge of image data. MWE is a shading start signal, which is generated in the section of the first line signal H-VALID that becomes active immediately after image reading starts. The timing of the sub-scanning direction is determined by the sub-scanning valid signal V-VA during the document reading period.
LID becomes active.

(3) Shading correction The principle of shading correction is shown in FIG. In an apparatus that reads an image by irradiating a lamp onto a document and condensing the reflected light with a lens, an uneven optical image called shading is obtained due to optical problems with the lamp, lens, and the like. In FIG. 4, when the image data in the main scanning direction is Vl, V2, . . . Vn, the level is decreasing at both ends in the main scanning direction. Therefore,
In order to correct this, the shading correction circuit 304
The following processing is performed. In FIG. 4, VR is the maximum value of the image level, and Vl is the image level of the first bit when reading the white color of a white board with uniform density as a reference (not shown). If the image level when the image is actually read is dl, then the tone level of the corrected image is d1'
becomes as follows.

di' = dlX VR/Vl Correction is performed for each bit so that this correction formula holds true.

FIG. 5 shows the internal configuration of the shading correction circuit 304. 3042 is a shading amount storage RAM for reading one line of a signal corresponding to a white board, and 3041 is a shading correction ROM that corrects an image signal based on the information stored in the shading amount storage RAM 3042 when reading an image.

When performing shading correction, first, the read image data for one line of the white plate is stored in the shading amount storage RAM 3.
042. At this time, a shading start signal MWH and an address signal ADR are sent from the synchronization control circuit 305.
, the image transfer solo lock CLKI is input, and the signals MWE and clock CLKI are input to the Nant gate 304.
3 to the write enable terminal W of the shading amount storage RAM 3042, and the read image data is stored at the address specified by the address signal ADH.

Next, when reading a document, the A/D converted image data is input to address terminals 0 to A5 of the shading correction ROM 3041. In addition, shading amount storage RAM
The shading data stored in 3042 is controlled by the address signal ADR, and the shading data stored in each terminal T1 is controlled by the address signal ADR.
Shading correction ROM3041 from 01 to l106
output to terminals A6 to All. Shading correction R
Pre-calculated data is written in the OM 3041 so that calculations using the above correction formula can be performed.

As a result of the above, using the read image data and shading data as address signals, the shading correction ROM 30
41 is accessed, and shading-corrected original image data Da is obtained from output terminals 01 to 06.

(4) Principle of Enlargement/Reduction The principle of enlargement/reduction is as shown in FIG. 6, for example, when enlarging (sampling at a magnification of 124/64). That is, although this FIG. 6 shows the sampling timing, the step width of the sampling timing is set to 64/124 (=0.51613), and by comparing the positions of adjacent pixel data of the original image data,
Selection data for selecting predetermined interpolation data is obtained, thereby obtaining interpolation data, which is used as converted image data. In this example, the original image data is
, D2. D3, 04, and the respective gradation levels are O,
F, F, 0. It was set as O. The unit distance between each original image data is 1. Therefore, the selected data is normalized according to the sampling position and becomes 0.0QOQO-0(S(1) 0.5L613→8(SL) 1.03226-0(S2) 1.54839-8(S3). The left side is the sampling position.The brackets on the right side indicate the sampling order, and the symbol on the left side indicates the selected data.The interpolated data obtained by this selected data, that is, the converted image data, is 0 (SO )
, 8(Sl), F(S2), F(S3)... The symbol to the left of the parentheses is the converted image data.

On the other hand, in reduction (sampling at a magnification of 33/64),
Proceed as shown in FIG. Step width is 64/33
(=1.93939). Each original image data is the same as in FIG. In this case, the original image data is thinned out, and the number of obtained converted image data is reduced. The selection data in this case is normalized and becomes 0.00000-0(So) L, 93939→F (SL) 3.87879→E (S2), and the converted image data is O(SO), F(Sl) ,0
(S2)...

(5) Enlargement/reduction circuit In the following explanation, it is assumed that the input original image data Da is 4 bits, and the magnification is 0.5 to 2.0 in 1.5% increments, and as an approximation of 1.5%, Use.

In principle, the circuit is configured to perform the same operation as if the sampling period had changed; when enlarging, the converted image data increases more than the original image data, and when reducing, the original image data is thinned out. The number of converted image data decreases.

The enlargement/reduction of the original image in the main scanning direction is electrically performed using the enlargement/reduction circuit 4.The enlargement/reduction in the sub-scanning direction is performed by keeping the exposure time of the C0D 300 constant and changing the moving speed of the sub-scanning. Let's do it.

In other words, if the sub-scanning speed is slowed down, the image will be enlarged, and if it is made faster, it will be reduced.

The timing generation circuit 400 receives a clock CLKI which is a timing signal from the synchronization control circuit 305 of the document reading section 3.
, horizontal synchronization signal H-SYNC1 main scanning direction valid signal H-
VALID, and a timing signal for the entire circuit is generated based on the sub-scanning direction valid signal V-VALID. In that signal, there is a clock CL with twice the frequency of the clock CLKI.
There is also K2.

The input 4-bit original image data Da is shifted by latches 401 and 402 that receive the clock CLKI, and is obtained as Dal and Da2 shifted by one pixel, and the above interpolated data between the two points is stored in advance as a table. This becomes the address signal of the interpolation ROM 403 that is currently being used. Attachment 1 shows a part of the table contents of interpolated data, and in reality, it is stored in ROM403 as shown in Attachment 2.
The interpolated data ob obtained by linear interpolation between two points is stored. The addresses of this interpolation ROM 403 are terminals A4 to A7. Original image data Dal of each of the two points input to A8 to All.

Da2 and selection data S (input to terminals AO to 83) indicating which linearly interpolated position is to be output are given. When the interpolation ROM 403 receives the addresses from these three sources, it outputs the 4-bit interpolation data Db stored in advance to the latch 404.

On the other hand, the data selection table 405 includes a magnification set externally and a clock CL from the timing generation circuit 400.
It is addressed by the count value of the count circuit 406 that counts K2, and outputs the selection data signal SD and the processing timing signal TO during enlargement/reduction from the table. The processing timing signal TO is synchronized with the clock CLK2 by latches 407 and 408, and then input to the gate circuit 409, which controls whether the clock CLK2 is passed or blocked.

The clock controlled by the gate circuit 409 becomes a write clock CLK3, which will be described later.

124/64 (enlarged) in attached table-3, 33/ in attached table-4
Part of the contents of the data selection table 405 in the case of 64 (reduction) is shown. In these, among the 8 bits of output data, the upper 4 bits are the data that becomes the above-mentioned selection data SD of the interpolation ROM 403, and the lower 4 bits (
In this case, only 0 and 1) is the processing timing data TO for controlling whether the write clock CLK3 is output as "1" or "0" as not. Figure 9 (al,
(b) shows a timing chart for 124/64 (enlarged) and 33/64 (reduced).

The image data Db converted during enlargement (124/64) is shown in Appendix-5. At the time of this converted image data SO-S9, write black 7 CIJ3 is output and sent to the binarization circuit 410 at the subsequent stage.

On the other hand, in the case of reduction (33/64), since some data is thinned out, the converted image data ob is output as shown in Table 6. Here, when the converted image data is invalid data or thinned-out data, the write clock CLK3 is not output. Invalid data is the circuit reference clock CLK2.
data that is output during reduction because it is set to twice the reference clock CLK 1, and thinned data refers to the converted image data Db from the original image data Da during reduction.
This is data that is output at a time when no data is generated.

The converted image data Db obtained by the enlargement/reduction processing as described above is sent to the subsequent binarization circuit 410 in synchronization with the write clock, and is stored in the dither ROM 4.
11 and output to the recording device 2 as binary data. Dither ROM411 is a horizontal synchronization signal! 1-
A sub-scanning counter 412 that counts 5YNC and a main-scanning counter 413 that counts the write clock CLK3.
It is addressed by the count value of .

(6) 8 Main parts of the present invention As mentioned above, if the magnification is 0.5 to 2.0 times in 1.5% increments (X/64 is used), the enlargement shown in FIG. In the reduction circuit 4, when a ROM is used for the data selection table 405, 12k×8 bytes are required. Realistically, 4 x 8-byte ROM is 3
Consists of individuals.

However, if we consider the case where the magnification step is increased to double 1% (using X/128), the required ROM capacity will increase.

Therefore, naturally, the required number of ROMs will be doubled to 6,
The area of the circuit becomes very large, and the reliability decreases, making it impractical. Further, if a magnification other than the magnification step (for example, reduction to paper size A3-84) is prepared, a new ROM is required to store the value.

Therefore, in this embodiment, as shown in FIG. 8, a data selection RAM 4050 as a rewritable memory is used as a component of the data selection table 405. Then, the CPU 4051 calculates the selection data SO and the processing timing signal TD for the interpolation ROM 403 in accordance with the magnification information input via the I10 port 4053 (the path is indicated by ...), and selects this data. R
I started writing to AM4050. This write path is indicated by 11111.

In calculations with CPt14051, the reciprocal of the magnification becomes the sampling interval (for example, in the case of 124/64 times, 6
4/124=0.5613), the selection data S and processing timing data TD are determined from the original image data and the sampling position. For example, the magnification is 124
When /64 times is specified, the contents of Attached Table 3 are output, and when 33764 times is specified, the contents of Attached Table 4 are output, and these are written to the data selection RAM 4050. This operation is performed by the selection circuit 405
This is carried out with the address bus of the CPU 4051 selected by 2.

Now, by specifying the magnification, the selection data SrJ and processing timing signal TD corresponding to the specified magnification can be stored in the data selection RAM 4050 as a data selection table as described above, so the scaling process starts next. Then, the selection circuit 4052 selects the address of the counter circuit 406, and the data selection RAM 405 selects the address of the counter circuit 406.
It is given to 0 and the continuation is performed.

Therefore, the clock CLK2 is input to the counter circuit 406, and the selection data SD and processing timing signal T written in the data selection RAM 4050 as described above are inputted to the counter circuit 406.
D is read and the interpolation ROM 403 and Nochi 40B
will be sent to.

Note that if the calculation by the CPU 421 takes time, a ROM-based table may be prepared as a basic pattern. Furthermore, a CPU 4051 for magnification calculation can be provided alone, or a CPU 4051 for controlling the entire device can be provided.
It can also be shared with PU.

〔Effect of the invention〕

From the above, according to the present invention, the data selection table for selecting interpolation data in the memory storing interpolation data is made into a rewritable memory, and the calculation means calculates the data according to the enlargement/reduction conditions instructed from the outside. Since the selection table is written in the memory, even if the precision of the magnification is made finer, the table can be realized without increasing the memory capacity.

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[Brief explanation of drawings]

Figure 1 is a diagram showing the basic configuration of the image reading device. Figure 2 is an internal block diagram of the document reading device. Figures 3 (a) and (bl are timing charts for document reading. Figure 4 is the principle of shading correction. 5 is a detailed diagram of the shading correction circuit, FIG. 6 is an explanatory diagram of sampling in the case of enlargement magnification, FIG. 7 is an explanatory diagram of sampling in the case of reduction magnification,
Fig. 8 is a circuit diagram of the enlargement/reduction circuit, Fig. 9 (a), (bl
is a timing chart of enlargement and reduction. Agent Patent Attorney Tsuneaki Nagao (Figure 1) Iirogo ADRCLKIMWE Figure 9 (a) Patent Application No. 094422 2, image processing device 3 with improved invention name data selection table;
Relationship with the case of the person making the amendment Patent applicant address: 1-26-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo
Name (127) Konishiroku Photo Industry Co., Ltd. 4, Agent

Claims (2)

[Claims] (1) In an image processing device that performs image scaling processing using an interpolation table for interpolating a plurality of image information and a data selection table for selecting specific interpolation data from the interpolation table, the above-mentioned An image processing apparatus characterized in that a data selection table is constructed of a rewritable memory, and the result of calculation by a calculation means according to an externally instructed magnification condition is written into the memory as selection data. (2), the memory is comprised of RAM, and the calculation means is C
The image processing device according to claim 1, characterized in that it is made of PU.