JPS62250580A - Memory controller - Google Patents

Abstract

PURPOSE:To easily change a clock period ratio by forming the timing of data transfer start and the timing of stop in response to a clock recognition signal synchronously with the clock of an input/output device. CONSTITUTION:A clock distributer 1 supplies an input/output device clock recognition signal (c) synchronously with a clock signal (b) of an input/output device to a data sending timing signal forming section 3, the signal forming section 3 uses the signal to form respectively a data sending start timing signal (d) and a data sending stop timing signal (e), which are fed to input/output interface sections 4, 5 respectively. In receiving the signal (d) by the sections 4, 5, data is set to each output register by the signal and the set data is sent respectively to the input/output devices 6, 7 synchronously with the clock signal (b). In receiving the signal (e), the input/output interface sections 4, 5 reset the output register to stop the data transmission (f, g) to the input/output devices 6, 7.

Description

TECHNICAL FIELD The present invention relates to a memory control device, and more particularly to a memory control device that performs synchronous control of data transfer to input/output devices.

Prior Art Conventionally, in this type of memory control device, data is transferred between input and output devices via each interface section, but since the clock of the input and output device is slower than the clock of the memory control device, The timing of this data transfer was controlled by each interface section. The connection cycle ratio between this memory control device and the input/output device was fixed.

In data processing devices, it is necessary to slow down the clocks of memory control devices and arithmetic units during the prototype evaluation process or when constructing them using low-speed and inexpensive elements. It has to change. However, in conventional memory control devices, the timing of data transfer is controlled in each interface section, so changing the clock period ratio in each interface section requires a great deal of effort and time. The disadvantage is that it is difficult to change easily.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional devices as described above, and it is an object of the present invention to provide a memory control device that can easily change the clock cycle ratio in data transfer between input and output devices. With the goal.

A memory control device according to the present invention is a memory control device that transfers data between an input/output device, and the data transfer is performed in response to a clock recognition signal synchronized with a clock of the input/output device. The present invention is characterized by having timing generation means for generating a start timing and a termination timing.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, the memory control device @2 is provided with a data sending timing signal generating section 3 and an input/output interface section 4.5.

FIGS. 2 and 3 are time charts of an embodiment of the present invention. The operation of one embodiment of the present invention will be explained using FIG. 1, FIG. 2, and FIG. 3.

The clock distribution device 1 supplies the memory control device 2 with a clock signal a for the memory control device, and supplies the input/output device 6.7 with a clock signal a for the input/output device. The clock distribution device 1 also includes a data transmission timing signal generation section 3.
An input/output device clock recognition signal C synchronized with a clock signal for the input/output device is supplied, and the data transmission timing signal generation section 3 uses this signal to generate a data transmission start timing signal d and a data transmission abort timing signal e, respectively. These signals d and e are sent to the input/output interface section 4.5.

When the data transmission start timing signal d is input to the input/output interface sections 4 and 5, data is set in the respective output registers (not shown) by this signal, and
The set data is sent to the input/output devices 6 and 7, respectively, in synchronization with the clock signal (f, Q). Further, when the input/output interface sections 4 and 5 receive the data transmission abort timing signal e, they reset the output registers and stop the data transmission f and 0 to the input/output device 6.7.

FIG. 2 shows that the clock period ratio between the clock signal a of the memory control device 2 and the clock signal S of the input/output device 6.7 is 3:
1, and FIG. 3 is a time chart showing the case where the O-sock period ratio is 3.5=1. In FIG. 3, the clock period ratio is 3.
5:1, but data transmission f to the input/output devices 6 and 7,
Since Q can only be performed in a clock period that is an integral multiple of the clock period, data is sent to the terminal t2 of the clock signal cycle 111T.

We are also discontinuing q.

FIG. 4(a) is a configuration diagram of the data sending timing signal generating section 3 using the counter 8, and FIG. 4(b) is a block diagram of the data sending timing signal generating section 3 using the shift registers 11-1 to 11-6. This is a configuration diagram, and both have a clock period ratio of 3.
: The case of 1 is shown. In FIG. 4(a), the counter 8 is reset by the input of the input/output device clock recognition signal C, and the AND circuit 9.10 counts a certain number of clocks, thereby generating the data transmission start timing signal d and the data transmission abort timing. A signal e is sent out. In addition, in FIG. 4(b), the data transmission start timing signal d and the data transmission abort timing signal e are obtained by delaying the input/output device output recognition signal C by a certain number of stages in the shift registers 11-1 to 11-6. is sent.

By switching the count number when using the counter 8 and the number of shift stages when using the shift registers 11-1 to 11-6 using respective selectors (not shown), data sending start timing signal d and data sending abort can be set. The timing signal e can be created according to changes in the clock period ratio.

If the data transmission start timing signal d and the data transmission termination timing signal e do not reach the input/output interface unit 4.5 in one clock due to a delay, etc., these timing signals are sent out one clock earlier. By doing so, data transmission f and Q from the input/output interface unit 4.5 can be performed.

In this way, by controlling the data sending f and Q of the input/output interface section 4.5 using the data sending start timing signal d and the data sending abort timing signal @e, the memory control device 2 and the input/output device 6.7 Even if the clock cycle ratio between the input and output devices 6 and 7 changes, the clock cycle ratio in data transfer can be easily changed in response to this change, and the clock signal of the input/output device 6゜7 is changed to the clock signal of the memory control device 2. Even if it is not an integral multiple of a, it is possible to change the clock period ratio accordingly. Furthermore, it is possible to cope with changes in the cycle time of data reception by the input/output devices 6.7.

As explained above, according to the present invention, data transfer from each interface unit is started and terminated by controlling the timing signal in response to the recognition signal synchronized with the clock of the input/output device. , it is possible to provide a memory control system that can easily change the clock cycle ratio in data transfer between input and output devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
FIG. 3 is a time chart of one embodiment of the present invention, and FIG. 4 (
4(a) is a block diagram showing the data sending timing signal generating section of FIG. 1 using a counter, and FIG. 4(b) is a block diagram of the data sending timing signal generating section of FIG. 1 using a shift register. Explanation of symbols of main parts ・

Claims (1)

[Claims] A memory control device that transfers data with an input/output device, the timing of creating a start timing and a termination timing of the data transfer in response to a clock recognition signal synchronized with a clock of the input/output device. A memory control device characterized by having a creation means.