JPS62242255A - Information processor - Google Patents

Abstract

PURPOSE:To performs the dereference processing at high speed by introducing a dereference flag indicating the prefetch of data and using the inspection result of the tag part of a data processing block and the state of the dereference flag. CONSTITUTION:A branch control block 7 controls so as to invalidate a mistake occurrence signal from a cache memory 2 and an address converting buffer 4 according to the inspection result of the tag part by the data processing block 5 and the state of the dereference flag 6. Namely, when the dereference flag 6 is turned on and when the inspection result of the tag part by the data processing block 5 is pointer data and when the dereference flag 6 is turned off, the mistake generating signal is effective and during other period, it is invalid. by neglecting this mistake occurrence signal, a trap to an unnecessary swap processing or an address converting processing resulting from a memory access in which a value part such as integer data generated during the data prefetch processing is treated as a logical address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to the high-level programming language Prologue (Pr), which is attracting attention in the field of knowledge information processing.

The present invention relates to an information processing apparatus that uses a tagged data expression effective for language processing such as log) as an internal data expression.

[Conventional technology]

Recent high-level programming languages such as Prolog are
It has a data type consisting of multiple cells and a pointer that indicates that it has the same value as other data. FIG. 2 is an example of internal data expression of a structure data type, which is a typical example of a data type consisting of a plurality of cells, in the prologue. A structure is a data type that consists of a structure base and structure elements. In the figure, 20 is a data block of the structure "large box", 21 is a data block of the structure "middle box", 22
is a data block of the structure “small box”. 23 is a tag section indicating the data type, and 24 is a value section indicating the data value. The internal data representation of the structure stores the number of elements of the structure in the first cell, the structure base in the second cell, and the elements in the third and subsequent cells. Furthermore, as in the example shown in FIG. 2, the elements may be structures.

In the internal data representation of FIG. 2, the first element of the structure “Medium box (small box (apples, pears), oranges)” is a pointer to the data block 22 of the structure “Small box (apples, pears)”. It is.

FIG. 3 is an internal data representation in which variables X, Y, and Z have the same value using pointers. In the figure, tag section 34
"unb" is undefined data, "r" in tag parts 35 and 36
ef" represents pointer data. When variable Z is accessed, cell 33 is accessed and tag section 36 is inspected. As a result of inspecting tag section 36, cell 33 is found to be a pointer, and cell 32 is accessed. Similarly, as a result of checking the tag part 35 of the cell 32, accessing the cell 31 and checking the tag part 34 reveals that the variable Z is undefined. Data access processing that follows pointer data generated during access is called dereference processing.

FIG. 4 shows the processing flow of the dereference processing that occurred when accessing the variable Z. In the diagram, 40 is a processing step for accessing the cell 33, 41 is a processing step for inspecting the tag section 36, and 42 is a processing step for accessing the cell 32. 43 is a processing step for inspecting the tag section 35 , 44 is a processing step for accessing the cell 31 , 45 is a processing step for inspecting the tag section 3
This is a processing step for inspecting 4.

In this way, it is necessary to check the tag part after accessing a cell, so two points are required to process one pointer data.
Step processing time is required.

Conventionally, as a means to speed up dereference processing, there is a method of inspecting the tag portion of data read from memory on a data bus. This method is called the first conventional technique.

In the first conventional technique, cell access and tag part inspection are performed in the same step. Therefore, one pointer
Data processing is completed in one step of processing time. 1st
FIG. 5 shows the configuration of an information processing apparatus using the conventional technology. In the figure, l is a main memory block that stores data and machine language programs, 2 is a cache memory that is a buffer memory for speeding up data access on main memory block 1, and 3 is data on main memory block 1. 4 is a buffer memory that holds a pair of the logical address held by the memory address register 3 and the physical address used in accessing the main memory block 1 corresponding to the logical address. An address conversion buffer 5, a data processing proref for performing arithmetic and logical operations on data read from the main memory block 1 and checking of the tag part; 11, a microprogram in the state of the cache memory 2, address conversion buffer 4, and data processing block 5; 8 is a microsequence control block that controls the execution sequence of the microprogram in accordance with the branch request signal output from the branch control block 11; 9;
1 is a data selector for input selection of the memory address register 3, and 10 is a data bus.

In such an information processing device, data is read from the cache memory 2, passes through the data bus 10, and is sent to the memory address register 3 and data processing block 5. At the same time, the tag portion of the data is sent directly from the data bus 10 to the branch control block 11, where the tag portion is checked.

Another method for speeding up the dereference processing is to pre-fetch data by treating the value part of the data whose tag part is being tested as a logical address, in parallel with the tag part testing process.

This method is called the second conventional technique.

In the second conventional technique, data is pre-fetched on the assumption that the inspection result of the tag part is pointer data. The logical address used for data prefetching is the value part of the data whose tag part is being checked. FIG. 6 shows the flow of pipeline processing when the variable Z in FIG. 3 is accessed using the second conventional technique. In the figure, 60, 61, 62, and 63 are data prefetching processes, and 64, 65, and 66 are tag part inspection processes.

In the first step, a cell 33 reading process 60 is performed.

In the second step, tag part inspection processing 64 of the data read in the first step is performed. Furthermore, in parallel, the value part of the data read in the first step is treated as a logical address, and data prefetching processing 61- is performed. Since the result of the tag part inspection process 64 is the detection of pointer data, in the third step, the tag part inspection process 65 of the data prefetched in the second step is performed. In this way, dereference processing that follows a chain made up of several pieces of pointer data takes an average processing time of l steps per piece of pointer data.

[Problem that the invention seeks to solve]

To speed up the dereference processing using the first conventional technique, in one step, the cache memory is accessed, the tag part is inspected, and the microinstruction to be executed in the next step is read. Therefore, the time for l step becomes longer. In other words, the problem is that the cycle time of the processor becomes longer, and simple data transfer processing from one register to another becomes slower.

In the second conventional technique, in order to prefetch data, memory access is performed using the value part of the data before it is confirmed to be a pointer. Therefore, there is a possibility of performing memory access using a value part such as integer data. Memory access using a value part such as integer data has a high possibility of causing a cache memory error or an address translation buffer error. When a cache memory miss or an address translation buffer miss occurs, swap processing and address translation processing routines are activated to swap the block containing the miss data to the cache memory, or to swap the block containing the miss data into the physical memory from the logical address that caused the cache miss. Performs a conversion to obtain an address. but,
Swap processing and address conversion processing caused by memory access using value parts such as integer data are unnecessary processing and waste the processing power of the processor. For this reason, the problem was that the processing speed that had been improved by pre-fetching data deteriorated, and the expected performance improvement could not be obtained.

[Purpose of the invention]

The purpose of the present invention is to speed up the dereference processing that occurs due to the appearance of pointer data, and to reduce the slowdown in processing speed such as simple data transfer processing from register to register, which is provided in conventional general-purpose computers. The purpose of this invention is to provide a processing device.

[Means for solving problems]

The information processing device of the present invention includes a main memory block that stores data and a machine language program, which is composed of a tag section indicating a data type and a value section indicating a data value, and a main memory block that can perform high-speed data access on the main memory block. a cache memory that is a buffer memory for storing data on the main memory block, a memory address register that holds a logical address that specifies data on the main memory block, and a logical address held by the memory address register and the logical address corresponding to the logical address. an address conversion buffer that is a buffer memory that holds pairs of physical addresses used in accessing the main memory block; a data processing block that performs arithmetic and logical operations on data read from the main memory block and checks the tag section; a dereference flag indicating that prefetch processing is in progress; a branch control block that generates a microprogram branch request signal in the state of the cache memory, the address translation buffer, the data processing block, and the dereference flag;
and a microsequence control block that controls the execution sequence of a microprogram according to a branch request signal output by the branch control block, and a swap-in trap is generated when the cache memory misses while the dereference flag is off. occurs, and if both the cache memory and the address translation buffer miss, an address translation trap is generated, and when the dereference flag is on, the data processing block detects a specific data type by checking the tag section. The detection of swap-in traps and address translation trap causes is enabled only when detected, and the detection of swap-in traps and address translation trap causes is disabled when the data processing block detects other data types. Features.

[Effect]

The second conventional technology avoids a decrease in the processing speed of simple data transfer processing from register to register, and reduces the average processing time required for processing one piece of pointer data in dereference processing to one step. do. However, in order to pre-fetch data, a memory access using a value part such as integer data as a logical address occurs.

This memory access using the value part such as integer data causes a trap in cache memory swap processing or address conversion processing. This swap processing and address translation processing are unnecessary processing and waste the processing power of the processor.

In the information processing device of the present invention, a dereference flag is introduced to indicate that data is being prefetched, and swap processing and address conversion processing are performed by using the inspection result of the tag part of the data processing block and the state of the dereference flag. traps can be prohibited, and unnecessary processing such as swap processing and address conversion processing that may occur in memory access using the value part of data other than pointer data can be avoided.

In the data prefetching process, basically, if the inspection result of the tag part is pointer data, the prefetched data is used. That is, swap processing and address conversion processing that occur during memory access in data prefetch processing are necessary processing. If the inspection result of the tag section is other than pointer data, the pre-fetched data is unnecessary. That is, swap processing and address conversion processing that occur during memory access in data prefetch processing are unnecessary.

If the dereference flag is on and the result of the tag section check by the data processing block is other than pointer data, trapping to swap processing or address conversion processing is prohibited. This prohibition function makes it possible to avoid unnecessary processing and enhances the effectiveness of data prefetching.

〔Example〕

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an information processing device that is an embodiment of the present invention. In the figure, 1 is a main memory block that stores data and machine language programs, 2 is a cache memory that operates as a buffer memory to speed up data access on main memory block 1, and 3 is a main memory block on main memory block 1. A memory address register 4 holds a logical address that specifies data, and a buffer memory 4 holds a pair of the logical address held by the memory address register 3 and the physical address used to access the main memory block 1 corresponding to the logical address. 5 is a data processing block that performs arithmetic and logical operations on data read from the main memory block l and checks the tag section; 6 is a dereference flag indicating that data prefetch processing is in progress;
7 is a branch control block that generates a microprogram branch request signal in the states of the cache memory 2, address conversion buffer 4, data processing block 5, and dereference flag 6; 8 is a branch control block that generates a branch request signal output from the branch control block 7; A microsequence control block controls the execution sequence of the microprogram, 9 is a data selector for selecting an input of the memory address register 3, and 10 is a data bus.

In such an information processing device, it is assumed that the data held by the main memory block 1 is composed of a tag section indicating the data type and a value section indicating the data value. The data read from cache memory 2 is transferred to data bus 1.
0 and is sent to the data processing block 5. At the same time, in order to pre-fetch data in the next step, the value part of the data read from the cache memory 2 is passed through the data bus 10, passed through the memory address register input data selector 9, and set in the memory address register 3. do. Furthermore, since the data prefetching process is started from the next step, the dereference flag 6 is set. In the next step, the data processing block 5 inspects the tag part of the data received in the previous step and sends the inspection result to the branch control block 7. On the other hand, data is read from the cache memory 2 using the value part of the data set in the memory address register 3. In other words, data is prefetched. At this time, in case the cache memory 2 misses, the address translation buffer 4 is accessed and an attempt is made to read the physical address corresponding to the logical address held in the memory address register 3. especially,
Since data prefetch processing is performed, there is a high possibility that memory access will be performed using the value part such as integer data that does not have a logical address in the value part, and there is a possibility that a mistake in the cache memory 2 and a mistake in the address translation buffer 4 will occur. is large.

The miss occurrence signal from the cache memory 2, the miss occurrence signal from the address translation buffer 4, the state of the dereference flag 6, and the inspection result of the tag section by the data processing block 5 are sent to the branch control block 7, and the result is sent to the branch control block 7, where the microprogram is executed. Used for branch control decisions. The branch control block 7 performs control to invalidate the miss occurrence signal ' from the cache memory IJ 2 and the address translation buffer 4 based on the tag part inspection result by the data processing block 5 and the state of the dereference flag 6. That is, when the dereference flag 6 is on, it indicates that data is being prefetched, so when the dereference flag 6 is on,
In addition, when the inspection result of the tag section by the data processing block 5 is pointer data and when the dereference flag 6 is in the OFF state, the error occurrence signal from the cache memory 2 and the address translation buffer 4 is valid. It is.

During other periods, the miss occurrence signals from the cache memory 2 and address translation buffer 4 are invalid. By ignoring miss occurrence signals from the cache memory 2 and address translation buffer 4 by the branch control block 7, unnecessary errors occur due to memory accesses that treat the value part of integer data etc. that occurred during data prefetch processing as a logical address. Traps to swap or address translation processing can be removed.

FIG. 7 is a processing flow when a conventional information processing apparatus pipelines dereference processing using data prefetching. In a first processing step 70, data is read from the first cell, and in a second processing step 71, the tag of the read data is inspected and the data is prefetched using the value part. The third processing step branches in six directions depending on the result of tag inspection and the states of the cache memory and address translation buffer. The first step is when the tag is a reference representing pointer data and the cache memory is hit. In the processing step 72, the tag part of the data prefetched in the second step 71 is inspected, and the value part is used to check the data. Be proactive. Second, the tag is a pointer
In a processing step 73 when the reference representing data is a miss in the cache memory and the address translation buffer is a hit, a swap process is performed on the cache memory. Third, the tag is a reference,
In addition, in processing step 74 when there is a miss between the cache memory and the address translation buffer, address translation processing is performed to obtain a physical address to be used for main memory block access. Fourth, in processing step 75 when the tag is other than a reference and the cache memory is hit, the accessed data is processed. The fifth step is processing step 76 when there is a hit other than the reference, there is a cache miss, and there is a hit in the address translation buffer.
Even though data prefetching is no longer necessary, swap-in processing is performed for cache misses that occur during data prefetching processing. The sixth is processing step 77 when there is a miss between the cache memory and the address translation buffer in cases other than reference.Even though data prefetching is no longer necessary, the cache memory and address translation that occurred in the data prefetching process are Performs address translation processing for buffer misses.

Further, in processing step 72, the process branches in six directions depending on the result of tag inspection of the prefetched data and the states of the cache memory and address translation buffer.

Processing step 78 is swap processing similar to processing step 73, processing step 79 is address conversion processing similar to processing step 74, processing step 80 is data processing similar to processing step 75, and processing step 81 is This is a swap process similar to process step 76,
Processing step 82 is an address conversion process similar to processing step 77.

In the above processing flow, processing steps 76 and 77 and processing steps 81 and 82 are steps that perform unnecessary processing and cause performance degradation.

FIG. 8 shows a processing flow when dereference processing using data prefetching is converted into pipeline processing in the information processing apparatus of this embodiment. In this processing flow, the same processing steps as those in FIG. 7 are indicated with the same numbers. According to the processing flow of the information processing apparatus of this embodiment, processing steps 76 and 77 and processing steps 81 and 82, which caused performance deterioration when using a conventional information processing apparatus, are removed, and dereference is performed. It can be seen that the processing speed has been improved.

〔Effect of the invention〕

In order to speed up dereference processing, which is data access processing that follows pointer data, the information processing device of the present invention performs two processes, data access and data type inspection, which are the basic processes of dereference processing. We have implemented a pipeline process that consists of two stages: a data access stage that performs data processing, and a data type inspection stage, and achieved faster processing by prefetching data, as well as introducing a dereference flag that indicates when data prefetching is in progress. It is possible to prevent unnecessary traps in swap processing and address conversion processing caused by the use of value parts such as integer data in memory addresses used for data prefetching, which has been a problem with conventional information processing devices. The processing speed of dereference processing is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an information processing device of the present invention. FIG. 2 is a diagram showing internal data representation of structure data of a high-level programming language prologue. FIG. 3 is a diagram showing variables x, y. , z are the same value, Figure 4 is a diagram showing the processing flow when variable Z in Figure 3 is accessed, Figure 5 is a conventional information processing device Figure 6 is a diagram showing a timing chart when dereference processing is pipelined, and Figure 7 is a diagram showing the timing chart when dereference processing is pipelined using a conventional information processing device. FIG. 8 is a diagram showing a processing flow when dereference processing is pipelined using the information processing apparatus of the present invention. l... Main memory block 2... Cache memory 3... Memory address register 4... Address translation buffer 5... Data processing block 6... Dereference flag 7... Branch control block 8...Microsequence control block 9...Memory address/register input data selector Yoshiyuki Iwasa Patent attorney 1st figure @('P box (small box (Rishiko), pear), oyster, [Cli] Figure 3 also Figure 4 Figure 6

Claims (1)

[Claims] (1) A main memory block for storing data and a machine language program consisting of a tag section indicating the data type and a value section indicating the data value, and a buffer for speeding up data access on the main memory block. A cache memory that is a memory, a memory address register that holds a logical address specifying data on the main memory block, a logical address held by the memory address register, and access to the main memory block corresponding to the logical address. an address conversion buffer that is a buffer memory that holds pairs of physical addresses used in the main memory block; a data processing block that performs arithmetic and logical operations on data read from the main memory block and checks the tag section; a branch control block that generates a microprogram branch request signal in the state of the cache memory, the address translation buffer, the data processing block, and the dereference flag; and a microsequence control block that controls the execution sequence of the microprogram according to the output branch request signal, and when the cache memory misses while the dereference flag is off, a swap-in trap is generated and the cache If both the memory and the address translation buffer miss, an address translation trap is generated, and when the dereference flag is on, swapping is performed only when the data processing block detects a specific data type by checking the tag section. Information processing characterized in that detection of in-trap and address translation trap causes is enabled, and when the data processing block detects other data types, detection of swap-in traps and address translation trap causes is disabled. Device.