JPS6221249A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6221249A JPS6221249A JP16024985A JP16024985A JPS6221249A JP S6221249 A JPS6221249 A JP S6221249A JP 16024985 A JP16024985 A JP 16024985A JP 16024985 A JP16024985 A JP 16024985A JP S6221249 A JPS6221249 A JP S6221249A
- Authority
- JP
- Japan
- Prior art keywords
- gel
- diamond powder
- semiconductor device
- semiconductor chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置に係り、特に、半導体装置の冷却
技術に適用して有効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to a cooling technique for a semiconductor device.
半導体装置において、大規模の集積度を得るために、塔
載用基板上に複数の半導体チップを塔載する高密度実装
技術を採用する場合がある。2. Description of the Related Art In semiconductor devices, in order to obtain large-scale integration, high-density packaging technology in which a plurality of semiconductor chips are mounted on a mounting substrate is sometimes employed.
このような半導体装置では、半導体チップの発生する熱
が回路の電気特性に影響を与えないようにするために、
冷却手段を必要とする。In such semiconductor devices, in order to prevent the heat generated by the semiconductor chip from affecting the electrical characteristics of the circuit,
Requires cooling means.
この冷却手段として、確実に接触のための球状部を有す
るピストンを半導体チップに接触させ。As this cooling means, a piston having a spherical part for reliable contact is brought into contact with the semiconductor chip.
該半導体チップの発生する熱をピストン等を介して冷却
媒体に放出する冷却技術が提案されている。A cooling technique has been proposed in which heat generated by the semiconductor chip is released to a cooling medium via a piston or the like.
本発明者の検討によれば、前記半導体チップとピストン
の球状部とが点で接触されているので、 ・充分な冷
却効率を得ることができない可能性があると考えられる
。According to the study of the present inventor, since the semiconductor chip and the spherical portion of the piston are in contact with each other at a point, it is thought that: - Sufficient cooling efficiency may not be obtained.
なお、ピストンを半導体チップに接触させ、該半導体チ
ップの発生する熱をピストン等を介して冷却媒体に放出
する冷却技術は1日経マグロウヒル社発行、「日経エレ
クトロニクス」、1982年7月19日号、P233〜
P252に記載されている。The cooling technology in which a piston is brought into contact with a semiconductor chip and the heat generated by the semiconductor chip is released to a cooling medium through the piston, etc. is described in 1 Nikkei McGraw-Hill Publishing, "Nikkei Electronics", July 19, 1982 issue, P233~
It is described in P252.
本発明の目的は、半導体装置の冷却効率を向上させるこ
とが可能な技術手段を提供することにある。An object of the present invention is to provide technical means that can improve the cooling efficiency of a semiconductor device.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を説明すれば、下記のとおりである。Outline of typical inventions disclosed in this application is as follows.
すなわち、少なくとも半導体チップの一部を熱伝導率の
高いダイヤモンドの粉末を混入したゲルで覆うことによ
り、半導体装置の冷却効率を向上したものである。That is, the cooling efficiency of the semiconductor device is improved by covering at least a portion of the semiconductor chip with a gel mixed with diamond powder having high thermal conductivity.
以下1本発明の構成について、実施例とともに説明する
。The configuration of the present invention will be explained below along with examples.
なお、全図において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。In all the figures, parts having the same functions are denoted by the same reference numerals, and repeated explanations thereof will be omitted.
第1図は、本発明の実施例Iの概略構成を示す要部断面
図である。FIG. 1 is a sectional view of a main part showing a schematic configuration of Example I of the present invention.
本実施例Iの半導体装置を、第1図に示す。その表面に
集積回路が形成されたシリコン半導体チップ1が、フリ
ップ・チップ方式で、すなわち主表面の突起電極2を介
してシリコン単結晶等からなる配線基板(マザーチップ
)3上に実装されている。配線基板3上にフォトリング
ラフィ技術。A semiconductor device of Example I is shown in FIG. A silicon semiconductor chip 1 with an integrated circuit formed on its surface is mounted on a wiring board (mother chip) 3 made of silicon single crystal or the like by a flip-chip method, that is, via protruding electrodes 2 on the main surface. . Photo phosphorography technology on wiring board 3.
マスク蒸着等によって形成された多層構造を有する配線
とリード4とはワイヤ5で電気的に接続される。パッケ
ージ基板6の所定位置には、ダム7が低融点ガラス等の
接着剤によって固着され、該ダム7を流れ止めとして用
い熱伝導率の高いダイヤモンドの粉末8を混入したシリ
コンを主成分とする電気絶縁性ゲル9を満して半導体チ
ップ1を包囲している。キャップ10をダム7に低融点
ガラス等の接着剤(図示していない)で固着することに
よって封止したものである。なお、ゲル9とキャップl
oとの間は接している必要はない。この場合、不活性ガ
ス等の封止ガスを封入することが望ましい。The wiring having a multilayer structure formed by mask evaporation or the like and the lead 4 are electrically connected by a wire 5. A dam 7 is fixed to a predetermined position of the package substrate 6 with an adhesive such as low-melting point glass, and using the dam 7 as a flow stopper, an electric current mainly composed of silicon mixed with diamond powder 8 having high thermal conductivity is used. It is filled with an insulating gel 9 and surrounds the semiconductor chip 1. The cap 10 is sealed to the dam 7 by fixing it to the dam 7 with an adhesive (not shown) such as low melting point glass. In addition, gel 9 and cap l
There is no need to be in contact with o. In this case, it is desirable to fill in a sealing gas such as an inert gas.
前記パッケージ基板6としては、熱伝導率の高い(2、
7W/ CII−K)ベリリウムを少量含有した炭化シ
リコン(SiC)の焼結体(特開昭57−2591号に
その詳細が示されている)を用いる。The package substrate 6 is made of a material having high thermal conductivity (2,
7W/CII-K) A sintered body of silicon carbide (SiC) containing a small amount of beryllium (details thereof are shown in JP-A-57-2591) is used.
なお、これに代えて、アルミナセラミック、ガラスエポ
キシ等を基板6として用いてもよい。前記シリコンを主
成分とするゲル9としては、シリコーンゲルが望ましい
。シリコーンゲルは、ゲル状であるので、熱膨張率等の
差により生ずる機械的応力を吸収するように変成する。Note that instead of this, alumina ceramic, glass epoxy, or the like may be used as the substrate 6. As the gel 9 whose main component is silicone, silicone gel is desirable. Since silicone gel is gel-like, it is denatured to absorb mechanical stress caused by differences in coefficients of thermal expansion and the like.
したがって、ゲル9と、チップ1.it電極、基板3.
ワイヤ5及びリード4との間にすきまが生ずることがな
いので、水膜がこれらの領域に生じない。このために5
パツケージ内に浸入した水分や汚染等によって、電極2
.ワイヤ5.リード4.配線等が腐食して断線、短絡等
を起すことがない。Therefore, gel 9 and chip 1. IT electrode, substrate 3.
Since there is no gap between the wire 5 and the lead 4, no water film is formed in these areas. For this reason 5
The electrode 2 may be damaged due to moisture or contamination that has entered the package.
.. Wire 5. Lead 4. Wiring, etc. will not corrode and cause disconnections, short circuits, etc.
以上の説明かられかるように、本実施例では、半導体チ
ップ1への浸水を防止するための絶縁性ゲル9の中に熱
伝導率の高い(20W/c、、K)ダイヤモンドの粉末
8を混入して熱抵抗を小さくすることにより、半導体チ
ップ1で発生した熱を突起電極2だけでなく熱伝導率の
高いダイヤモンドの粉末8を混入した絶縁性ゲル9を介
してパッケージ基板6.さらにはダム7、キャップ10
等に伝達して放熱することができる。これにより、半導
体チップ1の冷却効率を向上させることができる。なお
、上記した20W/m・Kという値は型Uaとして知ら
れるダイヤモンドの熱伝導率である。この型naの熱伝
導率が最も高いので、これを混入することが望ましいが
、他の型のダイヤモンドを混入してもよいことはいうま
でもない。どの場合でも、基板6の熱伝導率よりは、大
きいからである。As can be seen from the above description, in this embodiment, diamond powder 8 with high thermal conductivity (20 W/c, , K) is included in the insulating gel 9 to prevent water from entering the semiconductor chip 1. By mixing the diamond powder 8 and reducing the thermal resistance, the heat generated in the semiconductor chip 1 is transferred not only to the protruding electrodes 2 but also to the package substrate 6. Furthermore, dam 7, cap 10
Heat can be radiated by transmitting heat to etc. Thereby, the cooling efficiency of the semiconductor chip 1 can be improved. Note that the value of 20 W/m·K mentioned above is the thermal conductivity of diamond known as type Ua. Since this type na has the highest thermal conductivity, it is desirable to mix it, but it goes without saying that other types of diamonds may also be mixed. This is because the thermal conductivity is higher than that of the substrate 6 in any case.
実施例■の半導体装置を、第2図に示す。パッケージ基
板6上にはチップ相互間及びチップとリードとの間の接
続のための配線が直接設けられる。The semiconductor device of Example (2) is shown in FIG. Wiring for connection between chips and between chips and leads is directly provided on the package substrate 6.
半導体チップ1はパッケージ基板6に配線基板3を用い
ないで直接塔載される。突起電極2の部分に前記ダイヤ
モンドの粉末8を混入したシリコーンケル9が浸入しな
いように、小さいダム11を半導体チップ1を囲むよう
に設ける。これによって、半導体チップlの主表面下に
部分的に空間を形成する。ダイヤモンドを混入したゲル
は、しないゲルよりも全体としての硬度が高くなる。一
方。The semiconductor chip 1 is directly mounted on the package substrate 6 without using the wiring board 3. A small dam 11 is provided to surround the semiconductor chip 1 so that the silicone gel 9 mixed with the diamond powder 8 does not enter into the protruding electrode 2 portion. As a result, a space is partially formed under the main surface of the semiconductor chip l. Gels containing diamonds have higher overall hardness than gels without diamonds. on the other hand.
半導体チップ1上の集積回路の動作により発生する熱に
起因する応力が最もかかりやすいのは電極2である。そ
こで、本実施例では、電極2の近傍にダイヤモンドを混
入したゲルを設けずに、熱応力による剥離等の可能性を
排除している。The electrodes 2 are most likely to be subjected to stress due to heat generated by the operation of the integrated circuit on the semiconductor chip 1. Therefore, in this embodiment, the gel containing diamond is not provided near the electrode 2 to eliminate the possibility of peeling due to thermal stress.
実施例■の半導体装置は、第3図に示すように、前記実
施例■の半導体装置の小さいダム11を省略して、少な
くとも突起!ti2の部分が沈没する位の所まで絶縁性
のシリコーンゲル12で覆い、その上に前記熱伝導率の
高いダイヤモンドの粉末8を混入したシリコーンゲル9
を覆ったものである。As shown in FIG. 3, the semiconductor device of Example (2) omits the small dam 11 of the semiconductor device of Example (2), and has at least a protrusion! Silicone gel 9 is covered with an insulating silicone gel 12 up to the point where the ti2 part sinks, and the diamond powder 8 with high thermal conductivity is mixed thereon.
It is covered.
このようにすることにより、突起電極2における熱応力
の影響を殆んど無視することができる。By doing so, the influence of thermal stress on the protruding electrode 2 can be almost ignored.
以上説明したように1本願で開示した新規な技術によれ
ば1次に述べるような効果を得ることができる。As explained above, according to the novel technology disclosed in this application, the following effects can be obtained.
(1)半導体チップ等への浸水を防止するための絶縁性
ゲルの中に熱伝導率の高いダイヤモンドの粉末を混入し
て熱抵抗を小さくすることにより、半導体チップで発生
した熱を突起電極だけでなく熱伝導率の高いダイヤモン
ドの粉末を混入した絶縁性ゲルを介してパッケージ基板
に伝達して放熱することができる。これにより、半導体
装置の冷却効率を向上させることができる。(1) By mixing diamond powder with high thermal conductivity into the insulating gel to prevent water from seeping into semiconductor chips, etc., and reducing thermal resistance, the heat generated in the semiconductor chips can be transferred only to the protruding electrodes. Instead, heat can be radiated by transmitting it to the package substrate through an insulating gel mixed with diamond powder, which has high thermal conductivity. Thereby, the cooling efficiency of the semiconductor device can be improved.
以上1本発明を実施例にもとずき具体的に説明したが1
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
はいうまでもない。The present invention has been specifically explained above based on examples.
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.
例えば、前記実施例では1本発明をフリップチップ方式
の半導体装置に適用した例で説明したが、本発明はワイ
ヤボンディング方式の半導体装置にも適用できることは
勿論である。For example, in the embodiment described above, the present invention is applied to a flip-chip type semiconductor device, but it goes without saying that the present invention can also be applied to a wire bonding type semiconductor device.
第1図は、本発明の実施例Iの概略構成を説明するため
の要部断面図、
第2図は、本発明の実施例■の概略構成を説明するため
の要部断面図、
第3図は、本発明の実施例■の概略構成を説明するため
の要部断面図である。
図中、1・・・半導体チップ、2・・・突起電極、3・
・・配線基板、4・・・リード、5・・・ワイヤ、6・
・・パッケージ基板、7・・・ダム、8・・・熱伝導率
の高いダイヤモンド、9・・・熱伝導率の高いダイヤモ
ンドの粉末を混入したシリコーンゲル、10・・・キャ
ップ、11・・・小さいダム、12・・・シリコーンゲ
ルである。
第 1 図
第 2 図
第 3 図FIG. 1 is a sectional view of a main part for explaining the schematic structure of Embodiment I of the present invention, FIG. The figure is a sectional view of a main part for explaining the schematic configuration of the embodiment (2) of the present invention. In the figure, 1... semiconductor chip, 2... protruding electrode, 3...
・・Wiring board, 4・Lead, 5・Wire, 6・
...Package substrate, 7...Dam, 8...Diamond with high thermal conductivity, 9...Silicone gel mixed with diamond powder with high thermal conductivity, 10...Cap, 11... Small dam, 12...Silicone gel. Figure 1 Figure 2 Figure 3
Claims (1)
て、前記半導体チップの少なくとも一部をダイヤモンド
の粉末を混入した電気絶縁性ゲルで覆ったことを特徴と
する半導体装置。 2、前記半導体チップの突起電極部分は空間又は電気絶
縁性ゲルで覆い、他の部分は前記ダイヤモンドの粉末を
混入した電気絶縁性ゲルで覆ったことを特徴とする特許
請求の範囲第1項記載の半導体装置。 3、前記半導体チップを複数個塔載したことを特徴とす
る特許請求の範囲第1項記載の半導体装置。 4、前記電気絶縁性ゲルは、シリコーンゲルであること
を特徴とする特許請求の範囲第1項乃至第3項のいずれ
かに記載の半導体装置。[Claims] 1. A semiconductor device in which a semiconductor chip is mounted on a substrate, characterized in that at least a portion of the semiconductor chip is covered with an electrically insulating gel mixed with diamond powder. . 2. The protruding electrode portion of the semiconductor chip is covered with a space or an electrically insulating gel, and the other portions are covered with an electrically insulating gel mixed with the diamond powder. semiconductor devices. 3. The semiconductor device according to claim 1, wherein a plurality of the semiconductor chips are mounted. 4. The semiconductor device according to any one of claims 1 to 3, wherein the electrically insulating gel is silicone gel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16024985A JPS6221249A (en) | 1985-07-22 | 1985-07-22 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16024985A JPS6221249A (en) | 1985-07-22 | 1985-07-22 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6221249A true JPS6221249A (en) | 1987-01-29 |
Family
ID=15710921
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16024985A Pending JPS6221249A (en) | 1985-07-22 | 1985-07-22 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6221249A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01248551A (en) * | 1988-03-30 | 1989-10-04 | Toshiba Corp | Semiconductor package |
US5008736A (en) * | 1989-11-20 | 1991-04-16 | Motorola, Inc. | Thermal protection method for a power device |
JPH0410315U (en) * | 1990-05-18 | 1992-01-29 | ||
JPH04349651A (en) * | 1991-05-28 | 1992-12-04 | Matsushita Electron Corp | Semiconductor device |
JPH05215058A (en) * | 1988-08-05 | 1993-08-24 | Mitsubishi Electric Corp | Ignition coil device for internal combustion engine |
US5821457A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Semiconductor die carrier having a dielectric epoxy between adjacent leads |
US5824950A (en) * | 1994-03-11 | 1998-10-20 | The Panda Project | Low profile semiconductor die carrier |
US6339191B1 (en) * | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
JP2006316754A (en) * | 2005-05-16 | 2006-11-24 | Mitsubishi Heavy Ind Ltd | Vehicular motor-driven compressor |
US9355930B2 (en) | 2012-12-18 | 2016-05-31 | Fuji Electric Co., Ltd. | Semiconductor device |
JP2021052134A (en) * | 2019-09-26 | 2021-04-01 | 株式会社デンソー | Electronic control device |
-
1985
- 1985-07-22 JP JP16024985A patent/JPS6221249A/en active Pending
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01248551A (en) * | 1988-03-30 | 1989-10-04 | Toshiba Corp | Semiconductor package |
JPH05215058A (en) * | 1988-08-05 | 1993-08-24 | Mitsubishi Electric Corp | Ignition coil device for internal combustion engine |
US5008736A (en) * | 1989-11-20 | 1991-04-16 | Motorola, Inc. | Thermal protection method for a power device |
JPH0410315U (en) * | 1990-05-18 | 1992-01-29 | ||
JPH04349651A (en) * | 1991-05-28 | 1992-12-04 | Matsushita Electron Corp | Semiconductor device |
US5824950A (en) * | 1994-03-11 | 1998-10-20 | The Panda Project | Low profile semiconductor die carrier |
US5821457A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Semiconductor die carrier having a dielectric epoxy between adjacent leads |
US6339191B1 (en) * | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
US6828511B2 (en) | 1994-03-11 | 2004-12-07 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
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