JPS62219665A - Superlattice thin-film transistor - Google Patents
Superlattice thin-film transistorInfo
- Publication number
- JPS62219665A JPS62219665A JP6084386A JP6084386A JPS62219665A JP S62219665 A JPS62219665 A JP S62219665A JP 6084386 A JP6084386 A JP 6084386A JP 6084386 A JP6084386 A JP 6084386A JP S62219665 A JPS62219665 A JP S62219665A
- Authority
- JP
- Japan
- Prior art keywords
- superlattice
- layers
- sinx
- semiconductor layer
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 7
- 239000010408 film Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 7
- 229910004205 SiNX Inorganic materials 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000000969 carrier Substances 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 239000011521 glass Substances 0.000 abstract description 3
- 238000010030 laminating Methods 0.000 abstract description 3
- 229910017872 a-SiO2 Inorganic materials 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
- H01L29/78687—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys with a multilayer structure or superlattice structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
本発明は、非晶質の半導体層を持つ薄膜トランジスタ(
以下、TPTと称す)において、上記半導体層をa−S
i:Hとa−SiNx:Hとからなる非晶質の超格子構
造とすることにより、従来のasiTFTに見られる光
導電性を抑制し、迷光の影響を受けに(いTFTの実現
を図ったものである。[Detailed Description of the Invention] [Summary] The present invention provides a thin film transistor (
(hereinafter referred to as TPT), the semiconductor layer is a-S
By creating an amorphous superlattice structure consisting of i:H and a-SiNx:H, we are aiming to suppress the photoconductivity seen in conventional ASI TFTs and to realize TFTs that are less affected by stray light. It is something that
本発明は、非晶質半導体を用いて形成したTPTに関す
る。The present invention relates to a TPT formed using an amorphous semiconductor.
これまで、特にa−3t系のTPTは、低温・大面積形
成が可能であるため、例えばマトリクス型液晶表示装置
やりニアイメージセンサ等を駆動するためのスイッチン
グ素子として、広く用いられている。Hitherto, a-3t type TPT in particular has been widely used as a switching element for driving, for example, a matrix type liquid crystal display device or a near image sensor, since it can be formed at low temperature and in a large area.
従来のTPTとしては、ソース電極とドレイン電極との
間にa−Si:Hの単膜を備え、この単膜内を流れるキ
ャリアを、ゲート絶縁膜を介して設けられたゲート電極
によって制御するようにしたものが知られている。Conventional TPTs include a single film of a-Si:H between a source electrode and a drain electrode, and carriers flowing within this single film are controlled by a gate electrode provided through a gate insulating film. It is known what has been done.
上記従来のTPTに用いられたa−3i:Hの単膜は、
光導電性が大きいため、光があたると、例えばオフにし
ていたにもかかわらず上記光でオンに切換ねってしまう
というように、迷光による誤動作を生じ易かった。The a-3i:H single film used in the above conventional TPT is
Because of their high photoconductivity, when exposed to light, they tend to malfunction due to stray light, for example, the light causes them to turn on even though they have been turned off.
本発明は、a−3i:H層とa−SiNx:H層とを交
互に多数積層して構成した超格子を半導体層として用い
たものである。The present invention uses a superlattice formed by alternately laminating a large number of a-3i:H layers and a-SiNx:H layers as a semiconductor layer.
上記構成からなる超格子は、従来のa−3i :Hの単
膜に比べて、光を当てたときに流れる電流(以下、光電
流と称す)と光を当てないときに流れる電流(以下、暗
電流と称す)との差が非常に小さい。そのため、この超
格子を半導体層として用いたTPTは、光導電性が抑制
され、迷光の影響を受けにくく、非常に安定した動作特
性を示すようになる。Compared to the conventional a-3i:H single film, the superlattice with the above structure has a different current flowing when exposed to light (hereinafter referred to as photocurrent) and a current flowing when not exposed to light (hereinafter referred to as photocurrent). (referred to as dark current) is very small. Therefore, TPT using this superlattice as a semiconductor layer has suppressed photoconductivity, is less susceptible to stray light, and exhibits extremely stable operating characteristics.
以下、本発明の実施例について、図面を参照しながら説
明する。Embodiments of the present invention will be described below with reference to the drawings.
第1図は、本発明の第1の実施例を示す概略構成図であ
る。同図では、ガラス等でできた基板1上の所定位置に
ゲート電極Gを形成し、その上からa SiO2等の
ゲート絶縁膜2および後述する超格子3を層状に設けて
、さらにその上の所定位置にソース電極Sおよびドレイ
ン電極りを形成したものであり、ソース電極Sとドレイ
ン電極りとの間で超格子3内を流れるキャリアを、ゲー
ト電極Gに対する印加電圧によって制御するようにして
いる。FIG. 1 is a schematic configuration diagram showing a first embodiment of the present invention. In the figure, a gate electrode G is formed at a predetermined position on a substrate 1 made of glass or the like, and a gate insulating film 2 such as a SiO2 and a superlattice 3 to be described later are provided in a layered manner on top of the gate electrode G. A source electrode S and a drain electrode are formed at predetermined positions, and the carriers flowing in the superlattice 3 between the source electrode S and the drain electrode are controlled by the voltage applied to the gate electrode G. .
上記超格子3は、所定の層厚(例えば、10人〜100
人)を持つa−3i:H層およびa−SiNx:H層を
交互に多数積層した構造とし、その全体の層厚を例えば
約2500人となるようにしたものである。このような
超格子3は、プラズマCVDや光CVD等により、各層
ごとにガスを切換えて作製していく。例えば、a−3i
:H層の作製時は水素希釈のSiH4ガスを用い、また
a−SiNx:H層の作製時は水素希釈の5iHaガス
およびNH3ガスを用いる。The superlattice 3 has a predetermined layer thickness (for example, 10 to 100 layers).
The structure has a structure in which a large number of a-3i:H layers and a-SiNx:H layers having a layer of 1000000000000000000 persons are laminated alternately, and the total layer thickness thereof is, for example, about 2,500000000000000000000000000000000000000000000000000000000000000000000 People. Such a superlattice 3 is manufactured by switching gas for each layer by plasma CVD, optical CVD, or the like. For example, a-3i
When producing the :H layer, SiH4 gas diluted with hydrogen is used, and when producing the a-SiNx:H layer, 5iHa gas and NH3 gas diluted with hydrogen are used.
そこで、上記構成からなる超格子3における、面内方向
の暗電流および光電流と、a−3trH層およびa−S
iNx:H層の各層厚く前者の層厚をLs、後者の層厚
をLNとする)との関係を測定した結果を第4図に示す
。なおここでは、Ls=L、とし、またa−SiNxs
H層を作る時の5iHaガスとNH3ガスとの流量比(
NNH3/ Ns、Hsr )を1に固定した。さラニ
、この超格子3の面内方向には100 Vの電圧を印加
し、また光電流を測定する時の照射光は25 L xの
白色光を用いた。Therefore, in the superlattice 3 having the above structure, the dark current and photocurrent in the in-plane direction, the a-3trH layer and the a-S
FIG. 4 shows the results of measuring the relationship between the iNx:H layer thickness (the thickness of the former layer is Ls and the thickness of the latter layer is LN). Note that here, Ls=L, and a-SiNxs
Flow rate ratio of 5iHa gas and NH3 gas when creating H layer (
NNH3/Ns, Hsr) was fixed at 1. A voltage of 100 V was applied in the in-plane direction of this superlattice 3, and white light of 25 L x was used as the irradiation light when measuring the photocurrent.
第4図において、参考のために示したa−3i:Hの単
膜の場合、暗電流(ム印で示す)と光電流(△印で示す
)とは3桁程度の非常に大きな差を持っており、すわな
ち光を当てただけで電流が大きく変動する(光導電性が
大きい)ことがわかる。一方、上述した超格子の場合は
、上記a−Si:H単膜と比べて、暗電流(・印で示す
)と光電流(○印で示す)との差が非常に小さく、光導
電性が抑えられている。従って、このような超格子を使
用した本実施例のTPTは、迷光の影響を受けにくり、
非常に安定した動作特性を持つ。In Figure 4, in the case of the a-3i:H single film shown for reference, there is a very large difference of about 3 orders of magnitude between the dark current (indicated by the square mark) and the photocurrent (indicated by the △ mark). In other words, it can be seen that the current changes significantly just by shining light on it (high photoconductivity). On the other hand, in the case of the above-mentioned superlattice, the difference between the dark current (indicated by .) and the photocurrent (indicated by ○) is very small compared to the above-mentioned a-Si:H single film, and the photoconductivity is is suppressed. Therefore, the TPT of this example using such a superlattice is not affected by stray light,
It has very stable operating characteristics.
なお同図では、層厚Ls (−L、)を100人。In addition, in the same figure, the layer thickness Ls (-L,) is 100 people.
30人、10人と減少させるに従って、暗電流および光
電流が共に低下するとともに、光導電性がより抑制され
るのが見られる。この点を考慮すれば、上記層厚Ls、
L、は30Å以下であることが望ましい。As the number of participants decreases from 30 to 10, it can be seen that both the dark current and the photocurrent decrease, and the photoconductivity is further suppressed. Considering this point, the above layer thickness Ls,
It is desirable that L is 30 Å or less.
次に、本発明の第2の実施例の概略構成を第2図に示す
。同図では、ソース電極Sおよびドレイン電極りで超格
子13を両端から挾んだ構成としたものである。上記超
格子13は、前述した超格子3と同様な構成であり、第
4図に示した関係を持っている。このような構成にして
も、光導電性を非常に小さく抑えることができ、従って
迷光の影響を受けにくくなる。Next, FIG. 2 shows a schematic configuration of a second embodiment of the present invention. In the figure, a superlattice 13 is sandwiched between a source electrode S and a drain electrode from both ends. The superlattice 13 has the same structure as the superlattice 3 described above, and has the relationship shown in FIG. 4. Even with such a configuration, the photoconductivity can be suppressed to a very low level, making it less susceptible to stray light.
次に、本発明の第3の実施例の概略構成を第3図に示す
。同図では、第1図に示したものからゲート絶縁膜2を
除去した構成となっており、すなわち、ガラス基板1お
よびゲート電極G上に超格子23を直接形成したもので
ある。この超格子23も、前述した超格子3.13と同
様にして作製したものであり、第4図に示した関係を有
している。ここで、ゲート絶縁膜2を除去することがで
きるのは、以下の理由による。Next, FIG. 3 shows a schematic configuration of a third embodiment of the present invention. In this figure, the structure shown in FIG. 1 is obtained by removing the gate insulating film 2, that is, the superlattice 23 is directly formed on the glass substrate 1 and the gate electrode G. This superlattice 23 was also produced in the same manner as the superlattice 3.13 described above, and has the relationship shown in FIG. 4. The reason why the gate insulating film 2 can be removed here is as follows.
まず、全体の膜厚が2400人である超格子において、
その膜厚方向に印加された電圧と、そのときに膜厚方向
に流れる電流との関係を第3図に示す。First, in a superlattice with a total film thickness of 2400 layers,
FIG. 3 shows the relationship between the voltage applied in the film thickness direction and the current flowing in the film thickness direction at that time.
なお、このときの電極面積は3 va X 3 vmで
ある。Note that the electrode area at this time was 3 va x 3 vm.
同図において、L 、 = L 、 = 100人の場
合(曲線I)は、印加電圧の大きさによらず、10”’
Ω・cm以上の大きな抵抗率を有する。L、=Ls=3
0人の場合(曲線■)およびり、=Ls=10人の場合
(曲線■)は、曲線Iの場合と比べて各層厚が序々に薄
くなり、それに従ってトンネル効果によるリーク電流を
生じるが、印加電圧が5〜IOV付近では1013Ω・
印以上の大きな抵抗率を保っている。In the same figure, in the case of L, = L, = 100 people (curve I), the voltage is 10"' regardless of the magnitude of the applied voltage.
It has a large resistivity of Ω·cm or more. L,=Ls=3
In the case of 0 people (curve ■) and the case of = Ls = 10 people (curve ■), the thickness of each layer becomes gradually thinner compared to the case of curve I, and leakage current due to the tunneling effect occurs accordingly. When the applied voltage is around 5 to IOV, it is 1013Ω・
It maintains a resistivity higher than the mark.
これら膜厚方向の抵抗率は、面内方向の抵抗率が10幻
Ω・cm以下であるのに比べると、著しく大きい。従っ
て、抵抗率のこのような非等方的な性質により、膜厚方
向は実質的に絶縁されていることになり、ゲート電極G
と超格子23との間にはゲート絶縁膜が不要になる。These resistivities in the film thickness direction are significantly larger than the resistivity in the in-plane direction, which is less than 10 Ω·cm. Therefore, due to this anisotropic property of resistivity, the film is substantially insulated in the thickness direction, and the gate electrode G
There is no need for a gate insulating film between the superlattice 23 and the superlattice 23.
このようにゲート絶縁膜が不要になれば、構成が非常に
簡単になるため、信頼性および低価格化の面で非常に有
利になる。また、上記第1および第2の実施例と同様に
光導電性をも抑えることができるので、迷光の影響も受
けにく(なる。If the gate insulating film is not required in this way, the structure becomes very simple, which is very advantageous in terms of reliability and cost reduction. Furthermore, as in the first and second embodiments, photoconductivity can also be suppressed, making it less susceptible to stray light.
本発明によれば、超格子構造により光導電性を小さく抑
制することができるので、迷光の影響を受けない安定し
た動作特性を持つTPTを実現できる。さらに、上記超
格子における電気抵抗の非等方性を利用すれば、ゲート
絶縁膜のない簡単な構成のTPTを実現することもでき
る。According to the present invention, since photoconductivity can be suppressed to a small level by the superlattice structure, it is possible to realize a TPT with stable operating characteristics that are not affected by stray light. Furthermore, by utilizing the anisotropy of electrical resistance in the superlattice, a simple TPT without a gate insulating film can be realized.
第1図、第2図、第3図はそれぞれ本発明の第1、第2
、第3の実施例を示す概略構成図、第4図は本発明に係
る超格子における、面内方向の暗電流および光電流と、
各層厚(L、、t、s)との関係を示す図、
第5図は上記超格子の膜厚方向における、印加電圧と電
流との関係を示す図である。
1・・・基板、
2・・・ゲート絶縁膜、
3.13.23・・・超格子、
S・・・ソース電極、
D・・・ドレイン電極、
G・・・ゲート電極、1, 2, and 3 are the first and second embodiments of the present invention, respectively.
, a schematic configuration diagram showing the third embodiment, and FIG. 4 shows in-plane dark current and photocurrent in the superlattice according to the present invention,
FIG. 5 is a diagram showing the relationship between each layer thickness (L, t, s). FIG. 5 is a diagram showing the relationship between applied voltage and current in the thickness direction of the superlattice. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Gate insulating film, 3.13.23...Superlattice, S...Source electrode, D...Drain electrode, G...Gate electrode,
Claims (1)
て、 前記半導体層をa−Si:Hとa−SiN_x:Hとを
交互に多数積層してなる超格子(3、13、23)とし
たことを特徴とする超格子薄膜トランジスタ。 2)前記a−Si:H層の層厚が30Å以下であること
を特徴とする特許請求の範囲第1項記載の超格子薄膜ト
ランジスタ。 3)前記a−Si:H層および前記a−SiN_x:H
層の各層厚がいずれも30Å以下であることを特徴とす
る特許請求の範囲第1項記載の超格子薄膜トランジスタ
。 4)前記超格子とゲート電極(G)との間にゲート絶縁
膜(2)を有しないことを特徴とする特許請求の範囲第
1項乃至第3項のいずれか1つに記載の超格子薄膜トラ
ンジスタ。[Claims] 1) In a thin film transistor using an amorphous semiconductor layer, the semiconductor layer is a superlattice (3, 13 , 23). 2) The superlattice thin film transistor according to claim 1, wherein the a-Si:H layer has a thickness of 30 Å or less. 3) The a-Si:H layer and the a-SiN_x:H
2. The superlattice thin film transistor according to claim 1, wherein each of the layers has a thickness of 30 Å or less. 4) The superlattice according to any one of claims 1 to 3, characterized in that there is no gate insulating film (2) between the superlattice and the gate electrode (G). Thin film transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6084386A JPS62219665A (en) | 1986-03-20 | 1986-03-20 | Superlattice thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6084386A JPS62219665A (en) | 1986-03-20 | 1986-03-20 | Superlattice thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62219665A true JPS62219665A (en) | 1987-09-26 |
Family
ID=13154048
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6084386A Pending JPS62219665A (en) | 1986-03-20 | 1986-03-20 | Superlattice thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62219665A (en) |
Cited By (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6377158A (en) * | 1986-09-19 | 1988-04-07 | Sanyo Electric Co Ltd | Thin film transistor |
US5021839A (en) * | 1986-10-08 | 1991-06-04 | Semiconductor Energy Laboratory Co., Ltd. | FET with a super lattice channel |
US5081513A (en) * | 1991-02-28 | 1992-01-14 | Xerox Corporation | Electronic device with recovery layer proximate to active layer |
WO2005018004A1 (en) * | 2003-06-26 | 2005-02-24 | Rj Mears, Llc | Method for making semiconductor device including band-engineered superlattice |
WO2005018005A1 (en) * | 2003-06-26 | 2005-02-24 | Rj Mears, Llc | Semiconductor device including mosfet having band-engineered superlattice |
WO2005034245A1 (en) * | 2003-06-26 | 2005-04-14 | Rj Mears, Llc | Semiconductor device including band-engineered superlattice |
US6993222B2 (en) | 1999-03-05 | 2006-01-31 | Rj Mears, Llc | Optical filter device with aperiodically arranged grating elements |
US7045377B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
US7045813B2 (en) | 2003-06-26 | 2006-05-16 | Rj Mears, Llc | Semiconductor device including a superlattice with regions defining a semiconductor junction |
US7123792B1 (en) | 1999-03-05 | 2006-10-17 | Rj Mears, Llc | Configurable aperiodic grating device |
US7202494B2 (en) | 2003-06-26 | 2007-04-10 | Rj Mears, Llc | FINFET including a superlattice |
US7227174B2 (en) | 2003-06-26 | 2007-06-05 | Rj Mears, Llc | Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction |
US7229902B2 (en) | 2003-06-26 | 2007-06-12 | Rj Mears, Llc | Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction |
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-
1986
- 1986-03-20 JP JP6084386A patent/JPS62219665A/en active Pending
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