JPS62199033A - Formation of thin-film - Google Patents
Formation of thin-filmInfo
- Publication number
- JPS62199033A JPS62199033A JP4034786A JP4034786A JPS62199033A JP S62199033 A JPS62199033 A JP S62199033A JP 4034786 A JP4034786 A JP 4034786A JP 4034786 A JP4034786 A JP 4034786A JP S62199033 A JPS62199033 A JP S62199033A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- deposited
- hole
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 239000010408 film Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000004544 sputter deposition Methods 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 17
- 239000002245 particle Substances 0.000 claims abstract description 15
- 238000009826 distribution Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 9
- 230000000694 effects Effects 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 206010019133 Hangover Diseases 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 238000005477 sputtering target Methods 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000004020 conductor Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- -1 molybdenum Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、薄膜形成方法に関するもので、特に急峻な側
面を持ち微細でアスペクト比の高い凹凸のある基板表面
に、表面平坦性の良い薄膜を形成する方法に関するもの
である。Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a method for forming a thin film, in particular a method for forming a thin film with good surface flatness on the surface of a substrate with steep sides and fine, high aspect ratio irregularities. It relates to a method of forming a .
(従来の技術)
半導体装置において配線を行う場合には、基板101上
の表面を保護する絶縁膜にコンタクトホールを開けて、
その上に導体膜を堆積することによりなされる。最近の
LSI等におけるコンタクトホールの形成は、露光技術
やドライエツチング技術の進歩により、膜厚1〜2pm
の絶縁膜102に約1pm角程度のものが可能となって
いる。このようなコンタクトホールは側面が急峻で段差
が大きいため、従来の平行平板型のスパッタ法あるいは
蒸着法で導体膜を堆積させると第2図に示すように、コ
ンタクトホールの段差の屑蔀分に多く堆積された導体膜
201自身のシャドー効果のため段差被覆性が悪くなり
、配線が切れたり薄くなったりし易く、LSIの製造歩
留まりや信頼性が著しく低下していた。こうした欠点を
防ぐため、微細なコンタクトホールの側面をテーパー形
状として傾斜を持たせ導体膜が均一に堆積するような形
状が用いられるようになってきているが、微細なコンタ
クトホールの側面に傾斜を持たせることはLSIの高集
積化を阻害することになり、好ましい改善法ではない。(Prior Art) When performing wiring in a semiconductor device, contact holes are opened in an insulating film that protects the surface of a substrate 101, and
This is done by depositing a conductive film thereon. Due to advancements in exposure technology and dry etching technology, the formation of contact holes in recent LSIs, etc. has been reduced to a film thickness of 1 to 2 pm.
It is possible to make the insulating film 102 about 1 pm square. Such contact holes have steep sides and large steps, so if a conductor film is deposited using the conventional parallel plate sputtering method or vapor deposition method, as shown in Fig. Due to the shadow effect of the conductor film 201 itself, which has been deposited in large quantities, the step coverage is poor, the wiring is easily cut or thinned, and the manufacturing yield and reliability of the LSI are significantly lowered. In order to prevent these drawbacks, the side surfaces of minute contact holes are tapered and sloped so that the conductor film can be deposited uniformly. This is not a preferable improvement method because it will hinder the high integration of LSI.
その為、急峻で高アスペクト比の溝あるいはコンタクト
ホールに対して段差被覆性の良い状態で導体膜を堆積す
る方法が提案されており、そのうちの1つとしては、プ
ラネタリ−型の基板ホルダーを用いるスパッタ法がある
。この方法ではスパッタ粒子の飛来方向を乱雑にして段
差被覆性をよくしている。プラネタリ−型のスパッタ法
が平行平板型のスパッタ法に比べて、段差被覆性の良い
事は実験的に検証されている。さらに最近では、膜形成
時に基板側にも電力を印加し、基板表面で、膜堆積とス
パッタエツチングを同時に行うというバイアススパッタ
法により、表面に凹凸のある基板上に薄膜を段差被覆性
良く、あるいはコンタクトホール内を密に埋め込み、表
面平坦に堆積することも行われている。Therefore, methods have been proposed for depositing a conductive film with good step coverage on steep, high aspect ratio grooves or contact holes, and one method uses a planetary-type substrate holder. There is a sputtering method. In this method, the flying direction of sputtered particles is made random to improve step coverage. It has been experimentally verified that the planetary sputtering method provides better step coverage than the parallel plate sputtering method. Furthermore, recently, a bias sputtering method that applies power to the substrate side during film formation and simultaneously performs film deposition and sputter etching on the substrate surface has been used to form thin films on substrates with uneven surfaces with good step coverage or It is also practiced to densely fill the inside of the contact hole and deposit it on a flat surface.
(発明が解決しようとしている問題点)ンと実験との比
較がエイ・アール・ノイロイター(A、R。A.R. Neureuther (A.R.
Neureuther)らによりアイ・イー・イー・イ
ー・トランザクションズオンエレクトロンデバイス(I
EEETrans、 on ED、)27.1449(
1980)に報告されている。その報告によれば幅21
1m、アスペクト比(深さ1幅)065の溝に対してプ
ラネタリ−型のスパッタ法で膜を堆積すると、シャドー
効果のために段差被覆性が極めて悪化することが述べら
れている。さらに最上らにより、1985プロシーデイ
ングセカンドインターナシヨナルアイ、イー・イー・イ
ーブイエルエスアイマルチレベルインターコネクション
カンファ(1985)に示されているように、バイアス
スパッタ法による薄膜形成においても、表面の凹凸のア
スペクト比がある程度以上大きくなると、通常のスパッ
タ法の場合と同様に凹部に薄膜の堆積しない領域が残る
という問題があった。IE Transactions on Electron Devices (I
EEE Trans, on ED,) 27.1449 (
1980). According to the report, width 21
It is stated that when a film is deposited by planetary sputtering on a groove of 1 m and an aspect ratio (depth: 1 width) of 065, the step coverage is extremely deteriorated due to the shadow effect. Furthermore, as shown by Mogami et al. in the 1985 Proceedings Second International Eye, EEBBLSI Multilevel Interconnection Conference (1985), even in thin film formation by bias sputtering, it is possible to reduce surface irregularities. When the aspect ratio becomes larger than a certain level, there is a problem in that, as in the case of normal sputtering, there remains a region in the recess where no thin film is deposited.
本発明の目的は以上述べたごとき、従来の薄膜形成方法
の問題点に関して、特に高アスペクト比で微細な凹凸に
導体堆積膜を平坦性良く堆積する方法を提供することに
ある。SUMMARY OF THE INVENTION An object of the present invention is to address the problems of conventional thin film forming methods as described above, and to provide a method for depositing a conductor deposited film with good flatness, particularly on fine irregularities with a high aspect ratio.
(問題を解決するための手段)
本発明によれば、少なくとも基板表面の凹凸の凹部より
スパッタターゲットを見込む領域以外からのスパッタ粒
子の進入を遮断し、基板表面の凹凸の凸部の肩より生じ
る堆積膜の基板水平方向へのせりだしを抑制するバイア
ススパッタ条件で導体薄膜を堆積する第1の工程と、ス
パッタ粒子の飛来方向分布を広げ、該凹凸の凹部の導体
膜の膜堆積速度が該凹凸の凸部の導体膜の膜堆積速度よ
りも大きいバイアススパッタ条件で導体薄膜を堆積し、
該凹凸の凹部の導体薄膜の膜厚を該凹凸の凸部の高さと
該凹凸の凸部上の導体薄膜の膜厚との和にほぼ等しくす
る第2の工程とを含むことを特徴とする薄膜形成方法が
得られる。(Means for Solving the Problem) According to the present invention, at least the entrance of sputtered particles from other than the area where the sputter target is expected from the concave portion of the unevenness on the substrate surface is blocked, and the sputtered particles generated from the shoulder of the convex portion of the unevenness on the substrate surface are blocked. A first step of depositing a conductive thin film under bias sputtering conditions that suppresses the protrusion of the deposited film in the horizontal direction of the substrate, and a first step of depositing a conductive thin film under bias sputtering conditions that suppresses the protrusion of the deposited film in the horizontal direction of the substrate, and expanding the distribution of the flying direction of sputtered particles so that the film deposition rate of the conductive film on the concave portions of the unevenness is controlled. A conductive thin film is deposited under bias sputtering conditions that are higher than the film deposition rate of the conductive film on the convex portions of the unevenness,
A second step of making the thickness of the conductive thin film in the concave portion of the concave and convex portion approximately equal to the sum of the height of the convex portion of the concave and convex portion and the thickness of the conductive thin film on the convex portion of the concave and convex portion. A method for forming a thin film is obtained.
(作用)
従来のスパッタ法あるいはバイアススパッタ法を用いた
薄膜形成方法においては、表面の凹凸の程度に応じて、
基板に対するスパッタ粒子の飛来方向分布を変化させた
り、あるいは基板表面の凹凸のアスペクト比が大きい場
合に、基板に対して基板垂直方向から太き(傾いた方向
から入射するスパッタ粒子を遮断するといったことは、
実施さ“紅ていなかった。(Function) In the conventional thin film forming method using sputtering method or bias sputtering method, depending on the degree of surface unevenness,
When changing the distribution of sputtered particles in the flying direction relative to the substrate, or when the aspect ratio of irregularities on the substrate surface is large, it is possible to block sputtered particles that are incident from a direction perpendicular to the substrate (i.e., from a direction that is tilted). teeth,
It was not carried out.
本発明においては、以下のような原理で基板表面の凹凸
を密に埋め込むことができる。従来凸部の方がたくさん
スパッタ粒子が飛来してきていたが、少なくとも基板表
面の凹凸の凹部よりスパッタターゲットを見込む領域以
外からのスパッタ粒子の進入を遮断することで、凹凸の
凸部と凹部とでターゲットから飛来するスパッタ粒子の
数が等しくなり、凹凸の凸部と凹部とで膜堆積速度とが
等しくなる。さらに、同時にバイアススパッタ条件を調
整して凹凸の凸部の肩より生じる堆積膜の基板水平方向
へのせりだしを抑制する。この2つの制限により、凹凸
の凸部の肩からの堆積膜のせりだしが無く、凸部の肩部
分の角がとれ、凹凸の凸部と凹部とで厚さがほぼ等しい
膜が堆積される。In the present invention, irregularities on the surface of the substrate can be densely filled in based on the following principle. Conventionally, more sputtered particles came flying into the convex parts, but by blocking the entry of sputtered particles from areas other than the area where the sputter target is expected from the concave parts of the irregularities on the substrate surface, it is possible to reduce the distance between the convex parts and the concave parts of the irregularities. The number of sputtered particles flying from the target becomes equal, and the film deposition rate becomes equal between the convex portions and the concave portions of the unevenness. Furthermore, at the same time, the bias sputtering conditions are adjusted to suppress the protrusion of the deposited film from the shoulders of the convex portions of the unevenness in the horizontal direction of the substrate. Due to these two restrictions, the deposited film does not protrude from the shoulders of the convex portions of the unevenness, the shoulders of the convex portions are rounded, and a film is deposited with approximately the same thickness on the convex and concave portions of the unevenness. .
このようにすると凹凸の深さは変らないけれど肩部分の
角がとれているので、凹部の間口は広がる。したがって
第2の工程で表面が平坦になるように膜を堆積するとき
シャドー効果で堆積しない領域が残るようなことはない
。このようにして、アスペクト比の高い凹凸のある基板
表面も表面平担性よく密に薄膜を形成することができる
。By doing this, the depth of the depressions and depressions will not change, but the corners of the shoulders will be rounded, so the width of the depressions will increase. Therefore, when a film is deposited to make the surface flat in the second step, no region remains where no deposit is deposited due to a shadow effect. In this way, it is possible to form a dense thin film with good surface flatness even on the surface of a substrate having irregularities with a high aspect ratio.
(発明の実施例)
102をCVD法で厚さ約1pm堆積した後、通常のホ
トレジスト工程とドライエツチング工程を経て直径11
1mの開孔部を形成した状態を示す。次いで第1図(b
)に示すように、スパッタターゲットと基板との間に遮
蔽板を設け、その遮蔽板の穴を狭め、基板に対し、基板
垂直方向から大きく傾゛いた方向から入射するスパッタ
粒子を遮断し、基板水平面上の膜堆積速度とコンタクト
ホールの底面の膜堆積速度が同程度となり、かつコンタ
クトホールの段差の肩より生じる堆積膜の基板水平方向
へのせりだしを抑制するバイアススパッタ条件(アルゴ
ンガス圧:3mTorr、電極間距離二95mm、ター
ゲット側電力密度:5.7W/am2、バイアス電圧ニ
ー300V、ターゲット形状:円形、ターゲットの大き
さ:直径6インチ、遮蔽板の位置二基板面より40mm
、遮蔽板の穴の直径:40mm)でアルミニウム膜10
3を0.5pm堆積する。その結果、段差被覆性は悪い
が、コンタクトホールの段差の肩からの堆積膜のせりだ
しが無く、段差の肩部分の角がとれ、コンタクトホール
内にも基板水平面と同程度の膜厚のアルミニウム膜が堆
積される。さらに第1図(c)に示すように、コンタク
トホールの底部の導体薄膜の膜厚がコンタクトホールの
段差の高さとコンタクトホール段差上の導体薄膜の膜厚
との和にほぼ等しくなるように、遮蔽板の穴を広げ、か
つコンタクトホールの底部の導体膜の膜堆積速度が該コ
ンタクトホール段差上の導体膜の膜堆積速度よりも大き
いバイアススパッタ条件(アルゴンガス圧3mTorr
、電極間距離95mm、ターゲット側電力密度5.7W
/cm2、バイアス電圧ニー600V、遮蔽板の穴の直
径:90mm)でアルミニウム膜104を堆積する゛。(Embodiment of the Invention) After depositing 102 to a thickness of about 1 pm using the CVD method, a film with a diameter of 11
A state in which a 1 m open hole is formed is shown. Next, Figure 1 (b
), a shielding plate is provided between the sputter target and the substrate, and the hole in the shielding plate is narrowed to block sputtered particles that enter the substrate from a direction that is greatly tilted from the vertical direction of the substrate. Bias sputtering conditions (argon gas pressure: 3 mTorr, distance between electrodes 295 mm, target side power density: 5.7 W/am2, bias voltage 300 V, target shape: circular, target size: 6 inches in diameter, shielding plate position 2 40 mm from the substrate surface
, hole diameter of shielding plate: 40mm) and aluminum film 10
Deposit 0.5 pm of 3. As a result, although the step coverage is poor, the deposited film does not protrude from the shoulder of the contact hole step, the shoulder part of the step is rounded, and the aluminum film inside the contact hole has the same thickness as the horizontal surface of the substrate. A film is deposited. Further, as shown in FIG. 1(c), the thickness of the conductive thin film at the bottom of the contact hole is approximately equal to the sum of the height of the contact hole step and the thickness of the conductive thin film above the contact hole step. Bias sputtering conditions (argon gas pressure of 3 mTorr) in which the hole in the shielding plate is enlarged and the film deposition rate of the conductor film at the bottom of the contact hole is higher than the film deposition rate of the conductor film on the step of the contact hole.
, interelectrode distance 95mm, target side power density 5.7W
/cm2, bias voltage knee 600V, diameter of the hole in the shielding plate: 90mm).
この結果、コンタクトホール内には約2pmのアルミニ
ウム膜が堆積し、コンタクトホールの段差上の平坦面に
は約1pmのアルミニウム膜が堆積し、コンタクトホー
ルを有するシリコン酸化膜上のアルミニウム膜表面は殆
ど平坦になる。As a result, an aluminum film with a thickness of about 2 pm is deposited inside the contact hole, an aluminum film with a thickness of about 1 pm is deposited on the flat surface above the step of the contact hole, and the surface of the aluminum film on the silicon oxide film with the contact hole is almost completely covered. Become flat.
前記実施例においてはアルミニウム膜を堆積したが何も
これに限る必要はなく、モリブデン等の他の金属、不純
物をドープした多結晶シリコン、シリサイド等の合金も
用いることができる。Although an aluminum film was deposited in the above embodiments, there is no need to limit it to this, and other metals such as molybdenum, polycrystalline silicon doped with impurities, alloys such as silicide, etc. can also be used.
前記実施例においては穴が1つの遮蔽板を用いたが、複
数の穴をもつ遮蔽板を用いてもよい。複数の穴によって
基板への堆積膜の膜均一性は向上する。In the embodiment described above, a shielding plate with one hole was used, but a shielding plate with a plurality of holes may also be used. The plurality of holes improves the film uniformity of the deposited film on the substrate.
(発明の効果)
以上説明したごとく、本発明によれば急峻な側面を持ち
高アスペクト比で微細なコンタクトホールにおいても、
シャドー効果を生じることなく堆積導体膜を表面平坦性
良く堆積できる。その結果、2〜3層の多層配線構造に
おいて配線の段切れや接触不良等を回避でき、それをL
SIに使用した場合、信頼性、歩留りを飛躍的に向上す
ることができる。(Effects of the Invention) As explained above, according to the present invention, even in a fine contact hole with a steep side surface and a high aspect ratio,
The conductor film can be deposited with good surface flatness without producing a shadow effect. As a result, it is possible to avoid wiring breakage and poor contact in a multilayer wiring structure of 2 to 3 layers.
When used for SI, reliability and yield can be dramatically improved.
第1図(a)〜(c)は本発明の方法の一実施例を説明
するための模式的断面図、第2図は従来の平行平板型の
スパッタ法による膜堆積の一実施例を示した模式的断面
図である。
101・・・シリコン基板 102・・・シリコ
ン酸化膜103.104・・・アルミニウム膜 201
・・・堆積導体膜第 1 図
(b)
(C1
兜 2 図FIGS. 1(a) to (c) are schematic cross-sectional views for explaining an embodiment of the method of the present invention, and FIG. 2 shows an embodiment of film deposition by a conventional parallel plate sputtering method. FIG. 101...Silicon substrate 102...Silicon oxide film 103.104...Aluminum film 201
...Deposited conductor film Fig. 1 (b) (C1 Kabuto 2 Fig. 2)
Claims (1)
ットを見込む領域以外からのスパッタ粒子の進入を遮断
し、基板表面の凹凸の凸部の肩より生じる堆積膜の基板
水平方向へのせりだしを抑制するバイアススパッタ条件
で導体薄膜を堆積する第1の工程と、スパッタ粒子の飛
来方向分布を広げ、該凹凸の凹部の導体膜の膜堆積速度
が該凹凸の凸部の導体膜の膜堆積速度よりも大きいバイ
アススパッタ条件で導体薄膜を堆積し、該凹凸の凹部の
導体薄膜の膜厚を該凹凸の凸部の高さと該凹凸の凸部上
の導体薄膜の膜厚との和にほぼ等しくする第2の工程と
を含むことを特徴とする薄膜形成方法。Bias sputtering that blocks the entry of sputtered particles from areas other than the area where the sputter target is expected from at least the concave portions of the substrate surface irregularities, and suppresses the protrusion of the deposited film from the shoulders of the convex portions of the substrate surface in the horizontal direction of the substrate. a first step of depositing a conductive thin film under the conditions, and a bias that widens the distribution of sputtered particles in the flying direction so that the film deposition rate of the conductive film on the concave portions of the concave and convex portions is higher than the film deposition rate of the conductive film on the convex portions of the concave and convex portions; A second method in which a conductive thin film is deposited under sputtering conditions, and the thickness of the conductive thin film in the concave portions of the concave and convex portions is approximately equal to the sum of the height of the convex portions of the concave and convex portions and the thickness of the conductive thin film on the convex portions of the concave and convex portions. A method for forming a thin film, comprising the steps of:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61040347A JPH084088B2 (en) | 1986-02-27 | 1986-02-27 | Thin film formation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61040347A JPH084088B2 (en) | 1986-02-27 | 1986-02-27 | Thin film formation method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62199033A true JPS62199033A (en) | 1987-09-02 |
JPH084088B2 JPH084088B2 (en) | 1996-01-17 |
Family
ID=12578099
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61040347A Expired - Lifetime JPH084088B2 (en) | 1986-02-27 | 1986-02-27 | Thin film formation method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH084088B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5401675A (en) * | 1991-04-19 | 1995-03-28 | Lee; Pei-Ing P. | Method of depositing conductors in high aspect ratio apertures using a collimator |
US5529670A (en) * | 1991-04-19 | 1996-06-25 | International Business Machines Corporation | Method of depositing conductors in high aspect ratio apertures under high temperature conditions |
US5885425A (en) * | 1995-06-06 | 1999-03-23 | International Business Machines Corporation | Method for selective material deposition on one side of raised or recessed features |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6052043A (en) * | 1983-09-01 | 1985-03-23 | Nec Corp | Manufacture of wiring structure |
-
1986
- 1986-02-27 JP JP61040347A patent/JPH084088B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6052043A (en) * | 1983-09-01 | 1985-03-23 | Nec Corp | Manufacture of wiring structure |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5401675A (en) * | 1991-04-19 | 1995-03-28 | Lee; Pei-Ing P. | Method of depositing conductors in high aspect ratio apertures using a collimator |
US5529670A (en) * | 1991-04-19 | 1996-06-25 | International Business Machines Corporation | Method of depositing conductors in high aspect ratio apertures under high temperature conditions |
US5885425A (en) * | 1995-06-06 | 1999-03-23 | International Business Machines Corporation | Method for selective material deposition on one side of raised or recessed features |
Also Published As
Publication number | Publication date |
---|---|
JPH084088B2 (en) | 1996-01-17 |
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EXPY | Cancellation because of completion of term |